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1. 发明授权

US5146112A Semiconductor integrated circuit with analogue signal processing circuit and digital signal processing circuit formed on single semiconductor substrate 失效
标题翻译：半导体集成电路与模拟信号处理电路和数字信号处理电路形成在单个半导体衬底上
公开(公告)号：US5146112A
公开(公告)日：1992-09-08
申请号：US708019
申请日：1991-05-31
申请人： Masao Ito , Shiro Hosotani
发明人： Masao Ito , Shiro Hosotani
IPC分类号： G06G7/12 , H01L21/822 , H01L21/8238 , H01L27/02 , H01L27/04 , H01L27/088 , H01L27/092 , H03K5/24 , H03K17/16
CPC分类号： H01L27/088 , H03K5/2481 , H03K5/249 , H01L27/0203
摘要： A semiconductor integrated circuit device having an analogue signal processing circuit and a digital signal processing circuit formed on a single semiconductor substrate is disclosed. As an example of the analogue signal processing circuit, a voltage comparator is described. Being liable to be affected by noise, an inverter 2 is formed of an NMOS transistor 41 and a resistance R. For transistor 41 is formed in a well region having a conductivity type (p) opposite to the conductivity type of the substrate (n), it is not easily influenced by noise transmitted through the substrate. Therefore, a voltage comparator independent of the adverse effect of noise from the digital signal processing circuit is obtained.
摘要翻译：公开了一种具有模拟信号处理电路和形成在单个半导体衬底上的数字信号处理电路的半导体集成电路器件。作为模拟信号处理电路的示例，描述了电压比较器。容易受到噪声的影响，逆变器2由NMOS晶体管41和电阻R形成。晶体管41形成在具有与衬底（n）的导电类型相反的导电类型（p）的阱区中，，不容易受到透过基板的噪声的影响。因此，获得独立于来自数字信号处理电路的噪声的不利影响的电压比较器。

2. 发明授权

US06359660B1 Semiconductor integrated circuit for converting macro-block data into raster data which is adaptable to various formats 失效
标题翻译：用于将宏块数据转换成适用于各种格式的光栅数据的半导体集成电路
公开(公告)号：US06359660B1
公开(公告)日：2002-03-19
申请号：US08914192
申请日：1997-08-19
申请人： Natsuko Matsuo , Shiro Hosotani , Minobu Yazawa
发明人： Natsuko Matsuo , Shiro Hosotani , Minobu Yazawa
IPC分类号： H04N701
CPC分类号： H04N19/85 , H04N19/423 , H04N19/61
摘要： A block to raster converting circuit which is adaptable to all formats with a single circuit is realized. Macro-block data is mapped into a frame memory (13) on the basis of a particular format whose data size (X) in the horizontal direction provides a max condition. When writing, for each macro-block row (MBRi), the address of the first data in the initial macro-block (IMBi) is specified, on the basis of which address the column and row addresses are regularly switched according to the data array in the macro-block (MB). When reading, for each macro-block row (MBRi), the address of the initial data is specified, on the basis of which address the row address is switched every time data in each horizontal line in the macro-block row (MBRi) has been read and every time data at a turn of the column address in the frame memory (13) has been read. The column address is sequentially switched.
摘要翻译：实现了适用于单个电路的所有格式的块到光栅转换电路。基于在水平方向上的数据大小（X）提供最大条件的特定格式，将宏块数据映射到帧存储器（13）。当写入时，对于每个宏块行（MBRi），指定初始宏块（IMBi）中第一个数据的地址，根据哪个地址根据数据阵列定期切换列和行地址在宏块（MB）中。当读取每个宏块行（MBRi）时，指定初始数据的地址，根据宏块行（MBRi）中的每个水平行中的每个数据的哪个地址切换行地址的地址并且每当读取帧存储器（13）中的列地址的转动时的每一次数据。列地址被顺序切换。

3. 发明授权

US6157739A Displaying format converter for digitally encoded video signal data 失效
标题翻译：显示用于数字编码视频信号数据的格式转换器
公开(公告)号：US6157739A
公开(公告)日：2000-12-05
申请号：US956368
申请日：1997-10-23
申请人： Minobu Yazawa , Shiro Hosotani , Natsuko Matsuo
发明人： Minobu Yazawa , Shiro Hosotani , Natsuko Matsuo
IPC分类号： H04N5/46 , H04N7/01 , H04N19/00 , H04N19/423 , H04N19/44 , H04N19/625 , H04N19/85 , G06K9/36 , H04N5/91 , H04N11/20
CPC分类号： H04N7/01 , H04N19/423 , H04N19/427 , H04N19/61
摘要： A decoder for converting packet data into raster data is provided. The packet data includes data about a picture-compressed video signal and data about a picture format including a picture rate. The decoder comprising a first processing means, second processing means and a storage means. The first processing means converts the packet data into intermediate data such that picture compression is eliminated from the picture-compressed video signal and outputs the intermediate data. The second processing means receives the intermediate data from the first processing means and processes the intermediate data to output raster data for one frame at a frame frequency. The storage means stores the intermediate data for processing the intermediate data in the second processing means. The second processing means writes the intermediate data into the storage means at a frequency related to the picture rate and reads the raster data for one frame from the storage means at the frequency equal to the frame frequency.
摘要翻译：提供了一种用于将分组数据转换为光栅数据的解码器。分组数据包括关于图像压缩视频信号的数据和关于包括图像速率的图像格式的数据。解码器包括第一处理装置，第二处理装置和存储装置。第一处理装置将分组数据转换成中间数据，使得从图像压缩视频信号中消除图像压缩并输出中间数据。第二处理装置从第一处理装置接收中间数据，并处理中间数据，以帧频率输出一帧的光栅数据。存储装置将用于处理中间数据的中间数据存储在第二处理装置中。第二处理装置以与图像速率相关的频率将中间数据写入存储装置，并以等于帧频的频率从存储装置读取一帧的光栅数据。

4. 发明授权

US5652728A Dynamic memory 失效
标题翻译：动态内存
公开(公告)号：US5652728A
公开(公告)日：1997-07-29
申请号：US524930
申请日：1995-09-08
申请人： Shiro Hosotani , Minobu Yazawa , Kazuya Yamanaka
发明人： Shiro Hosotani , Minobu Yazawa , Kazuya Yamanaka
IPC分类号： G11C11/405 , G11C7/00 , G11C11/401 , G11C11/4099
CPC分类号： G11C11/4099
摘要： Dummy information of a third level, which is between first and second levels written in a plurality of memory cells, is written in a dummy memory cell from a source node through transistors. Thus, a potential difference is caused between a read bit line and a dummy read bit line in reading. A potential comparison circuit indicates the level of information read from any memory cell on the basis of the comparison result as to the potentials of the dummy read bit line and the read bit line. Thus, the read rate is increased, the read operation is stabilized and increase of the chip area is suppressed.
摘要翻译：写入多个存储单元的第一级和第二级之间的第三级的虚拟信息通过晶体管从源节点写入虚拟存储单元。因此，读取中的读取位线和虚拟读取位线之间产生电位差。潜在的比较电路根据关于虚拟读取位线和读取位线的电位的比较结果来指示从任何存储器单元读取的信息的电平。因此，读取速率增加，读取操作稳定，并且抑制了芯片面积的增加。

5. 发明授权

US5010338A Comparator circuit and analog to digital converter 失效
标题翻译：比较器电路和模数转换器
公开(公告)号：US5010338A
公开(公告)日：1991-04-23
申请号：US260126
申请日：1988-10-18
申请人： Takahiro Miki , Shiro Hosotani
发明人： Takahiro Miki , Shiro Hosotani
IPC分类号： H03K5/08 , H03K5/24 , H03M1/36
CPC分类号： H03K5/249 , H03M1/365
摘要： A comparator circuit capable of high-speed and accurate operation is disclosed. The comparator circuit includes an amplifier section 4, an inverter 5 connected to the output of the amplifier section 4, and a switching circuit 11 connected across the inverter 5. The amplifier section 4 contains a capacitor 1, an inverter 2 and a switching circuit 3 connected across the inverter 2. Coupled to the input of the amplifier section 4 are switching circuits 8 and 9 for supplying voltages V.sub.1 and V.sub.2 to be compared under timing control. During the first half cycle of comparing operation, the switching circuits 8, 3 and 11 are turned on while the switch circuit 9 is turned off. During the second half cycle of comparing operation, the switching circuit 9 is turned on while the switching circuits 8, 3 and 11 are turned off. The inverter 5, being short circuited by the switching circuit 11, produces a predetermined intermediate voltage during the first half of operating cycle, which is effective to generate voltage outputs accurately and exactly representing the compared results during the second half of the operating cycle.
摘要翻译：公开了一种能够高速且精确地操作的比较器电路。比较器电路包括放大器部分4，连接到放大器部分4的输出的反相器5和连接在反相器5两端的开关电路11.放大器部分4包含电容器1，反相器2和开关电路3 连接到逆变器2.耦合到放大器部分4的输入端，是用于提供电压V1和V2的开关电路8和9，以在定时控制下进行比较。在比较操作的前半周期期间，开关电路8,3和11在开关电路9断开时导通。在比较操作的第二个半周期期间，开关电路9导通，而开关电路8,3和11断开。由开关电路11短路的逆变器5在操作周期的前半部分期间产生预定的中间电压，这对于在操作周期的后半期期间精确地和准确地表示比较结果来产生电压输出是有效的。

6. 发明授权

US4900952A Voltage comparison apparatus 失效
标题翻译：电压比较装置
公开(公告)号：US4900952A
公开(公告)日：1990-02-13
申请号：US303778
申请日：1989-01-27
申请人： Shiro Hosotani , Takahiro Miki , Toshio Kumamoto
发明人： Shiro Hosotani , Takahiro Miki , Toshio Kumamoto
IPC分类号： G01R19/165 , H03K5/08 , H03K5/24
CPC分类号： H03K5/249
摘要： The voltage comparison apparatus of the invention features a timing control of clocks by which individual switches are ON/OFF controlled so that before a preceding amplifier circuit goes into comparison mode from auto zero mode, a successive amplifier circuit may go into auto zero mode from comparison mode, or before the preceding amplifier circuit goes into auto zero mode from comparison mode, the successive amplifier circuit may go into comparison mode from auto zero mode, whereby before the preceding amplifier circuit undergoes transition from the auto zero mode to the comparison mode, the successive amplifier circuit goes into the auto zero mode from the comparison mode, or before the preceding amplifier circuit undergoes transition from the comparison mode to the auto zero mode, the successive amplifier circuit goes into the comparison mode from the auto zero mode, and even when considerable variation occurs in input voltage difference during each clock cycle or clock time lags occurs, stable operation can be assured.
摘要翻译：本发明的电压比较装置具有对各个开关进行ON / OFF控制的时钟的定时控制，使得在前一放大器电路从自动归零模式进入比较模式之前，连续的放大器电路可以从比较进入自动零模式模式，或在比较模式之前的前一放大器电路进入自动归零模式之前，连续的放大器电路可以从自动调零模式进入比较模式，由此在之前的放大器电路经历从自动调零模式转换到比较模式之前，连续放大器电路从比较模式进入自动归零模式，或者在前一放大器电路从比较模式转换到自动归零模式之前，连续放大器电路从自动归零模式进入比较模式，甚至当在每个时钟周期或时钟时间滞后时，输入电压差异会发生相当大的变化遏制，稳定运行可以放心。

7. 发明授权

US5818380A Analog-digital converter capable of reducing a conversation error of an output signal 失效
标题翻译：模数转换器能够减少输出信号的转换误差
公开(公告)号：US5818380A
公开(公告)日：1998-10-06
申请号：US824549
申请日：1997-03-25
申请人： Masao Ito , Takahiro Miki , Shiro Hosotani
发明人： Masao Ito , Takahiro Miki , Shiro Hosotani
IPC分类号： H03M1/10 , H03K19/23 , H03M1/06 , H03M1/36
CPC分类号： H03M1/0602 , H03M1/361
摘要： A majority logic circuit is supplied with output values of adjacent three comparators. The majority logic circuit outputs, as an output signal, the supplied three output values including at least two equal output values. Inverter circuits and AND circuits produce and output a read signal of an encoder which is a logical product between the output signal and an inverted signal of the output signal.
摘要翻译：多数逻辑电路提供相邻三个比较器的输出值。多数逻辑电路作为输出信号输出所提供的三个输出值，包括至少两个相等的输出值。逆变器电路和AND电路产生并输出编码器的读取信号，该编码器是输出信号和输出信号的反相信号之间的逻辑积。

8. 发明授权

US5225837A A/D converter 失效
标题翻译： A / D转换器
公开(公告)号：US5225837A
公开(公告)日：1993-07-06
申请号：US706834
申请日：1991-05-29
申请人： Shiro Hosotani , Takahiro Miki , Masao Ito
发明人： Shiro Hosotani , Takahiro Miki , Masao Ito
IPC分类号： H03M1/36 , H03M1/78
CPC分类号： H03M1/362
摘要： An A/D converter includes a resistor network generating a reference voltage, a level detector for detecting the level of an input analogue signal with a reference voltage from the resistor network as a reference, and an encoder for providing a digital signal by encoding the output of the level detector. The level detector includes a plurality of comparators for bilevel-processing the input analogue signal with a preselected voltage from the resistor connection nodes of the resistor network as a reference voltage. The resistor network comprises a plurality of resistor elements between a first node receiving a first reference voltage and a second node receiving a second reference voltage, which are interconnected to provide a voltage from an associated connection node that is 1/2.sup.j times the difference between said first reference voltage and said second reference voltage. The comparator includes capacitors for providing the difference between the input analogue signal and the reference voltage by a capacitor coupling, and an inverter amplifier for determining the positive or negative of the voltage change generated by the capacitors. This structure implements an A/D converter of high precision with less elements.
摘要翻译： A / D转换器包括产生参考电压的电阻网络，用于以来自电阻器网络的参考电压作为参考来检测输入模拟信号的电平的电平检测器，以及用于通过对输出进行编码来提供数字信号的编码器的电平检测器。电平检测器包括多个比较器，用于以来自电阻器网络的电阻器连接节点的预选电压作为参考电压对输入的模拟信号进行二维处理。电阻网络包括在接收第一参考电压的第一节点和接收第二参考电压的第二节点之间的多个电阻器元件，其互连以提供来自相关联的连接节点的电压，所述相关联的连接节点是所述第一参考电压和所述第二参考电压。比较器包括用于通过电容器耦合提供输入模拟信号和参考电压之间的差异的电容器，以及用于确定由电容器产生的电压变化的正或负的反相放大器。该结构实现了具有较低元件精度的A / D转换器。

9. 发明授权

US5075688A Binary signal generating circuit with parallel sample and hold circuits and common sampling switch 失效
标题翻译：具有并行采样和保持电路的二进制信号发生电路和公共采样开关
公开(公告)号：US5075688A
公开(公告)日：1991-12-24
申请号：US622071
申请日：1990-12-04
申请人： Shiro Hosotani , Takahiro Miki
发明人： Shiro Hosotani , Takahiro Miki
IPC分类号： H03M1/36 , H03M1/06
CPC分类号： H03M1/0646 , H03M1/36
摘要： A single sampling switch i provided for a plurality of sample/hold function-equipped comparators. Thus, when the sampling switch is turned on, an analog signal is fed to each sample and hold circuit, and when it is turned off, the analog signal fed in at that time is sampled and held in each sample/hold function-equipped comparator. The analog signal values sampled and held in the sample/hold function-equipped comparators are averaged when the averaging switch is turned on. In this manner, since the timing for sampling and holding is controlled by the single sampling switch, a smaller number of switching elements are sufficient and the possibility of the timing for sampling and holding differing between the sample/hold function-equipped comparators is eliminated.
摘要翻译：单个采样开关i设置用于多个采样/保持功能的比较器。因此，当采样开关接通时，模拟信号被馈送到每个采样和保持电路，并且当其被截止时，馈入的模拟信号在该时间被采样并保持在每个采样保持功能的比较器。采样保持在采样/保持功能的比较器中的模拟信号值在平均开关导通时被平均。以这种方式，由于采样和保持的定时由单采样开关控制，所以较少数量的开关元件是足够的，并且消除了具有采样/保持功能的比较器之间的取样和保持定时不同的可能性。

10. 发明授权

US4912470A Ad converter 失效
标题翻译：广告转换器
公开(公告)号：US4912470A
公开(公告)日：1990-03-27
申请号：US260130
申请日：1988-10-18
申请人： Shiro Hosotani , Takahiro Miki
发明人： Shiro Hosotani , Takahiro Miki
IPC分类号： H03M1/14 , H03M1/06
CPC分类号： H03M1/0602 , H03M1/147
摘要： A serial-parallel type AD converter comprises a first parallel type AD converting portion determining a higher order bit of a digital signal, a second parallel type AD converting portion determining a lower order bit of the digital signal and error correcting circuit. In the first parallel type Ad converting portion, a shifter is connected between a first determining circuit and a first encoder. In the second parallel type AD converting portion, a selector is connected between three second voltage comparator groups and a second determining circuit. The error correcting circuit applies control signals to the shifter and the selector for correcting errors derived from sampling skew of analog input voltages. The shifter determines the connection between the first determining circuit and first encoder in response to the control signal. The selector connects one of the three voltage comparator groups to the second determining circuit in response to the control signal.
摘要翻译：串行并行型AD转换器包括确定数字信号的较高阶位的第一并行型AD转换部分，确定数字信号的低位位的第二并行型AD转换部分和纠错电路。在第一并行型Ad转换部分中，移位器连接在第一确定电路和第一编码器之间。在第二并联型AD转换部分中，选择器连接在三个第二电压比较器组和第二确定电路之间。误差校正电路向移位器和选择器施加控制信号，用于校正由模拟输入电压的采样偏差导出的误差。移位器响应于控制信号确定第一确定电路和第一编码器之间的连接。选择器响应于控制信号将三个电压比较器组中的一个连接到第二确定电路。

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