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1. 发明授权

US06359660B1 Semiconductor integrated circuit for converting macro-block data into raster data which is adaptable to various formats 失效
标题翻译：用于将宏块数据转换成适用于各种格式的光栅数据的半导体集成电路
公开(公告)号：US06359660B1
公开(公告)日：2002-03-19
申请号：US08914192
申请日：1997-08-19
申请人： Natsuko Matsuo , Shiro Hosotani , Minobu Yazawa
发明人： Natsuko Matsuo , Shiro Hosotani , Minobu Yazawa
IPC分类号： H04N701
CPC分类号： H04N19/85 , H04N19/423 , H04N19/61
摘要： A block to raster converting circuit which is adaptable to all formats with a single circuit is realized. Macro-block data is mapped into a frame memory (13) on the basis of a particular format whose data size (X) in the horizontal direction provides a max condition. When writing, for each macro-block row (MBRi), the address of the first data in the initial macro-block (IMBi) is specified, on the basis of which address the column and row addresses are regularly switched according to the data array in the macro-block (MB). When reading, for each macro-block row (MBRi), the address of the initial data is specified, on the basis of which address the row address is switched every time data in each horizontal line in the macro-block row (MBRi) has been read and every time data at a turn of the column address in the frame memory (13) has been read. The column address is sequentially switched.
摘要翻译：实现了适用于单个电路的所有格式的块到光栅转换电路。基于在水平方向上的数据大小（X）提供最大条件的特定格式，将宏块数据映射到帧存储器（13）。当写入时，对于每个宏块行（MBRi），指定初始宏块（IMBi）中第一个数据的地址，根据哪个地址根据数据阵列定期切换列和行地址在宏块（MB）中。当读取每个宏块行（MBRi）时，指定初始数据的地址，根据宏块行（MBRi）中的每个水平行中的每个数据的哪个地址切换行地址的地址并且每当读取帧存储器（13）中的列地址的转动时的每一次数据。列地址被顺序切换。

2. 发明授权

US6157739A Displaying format converter for digitally encoded video signal data 失效
标题翻译：显示用于数字编码视频信号数据的格式转换器
公开(公告)号：US6157739A
公开(公告)日：2000-12-05
申请号：US956368
申请日：1997-10-23
申请人： Minobu Yazawa , Shiro Hosotani , Natsuko Matsuo
发明人： Minobu Yazawa , Shiro Hosotani , Natsuko Matsuo
IPC分类号： H04N5/46 , H04N7/01 , H04N19/00 , H04N19/423 , H04N19/44 , H04N19/625 , H04N19/85 , G06K9/36 , H04N5/91 , H04N11/20
CPC分类号： H04N7/01 , H04N19/423 , H04N19/427 , H04N19/61
摘要： A decoder for converting packet data into raster data is provided. The packet data includes data about a picture-compressed video signal and data about a picture format including a picture rate. The decoder comprising a first processing means, second processing means and a storage means. The first processing means converts the packet data into intermediate data such that picture compression is eliminated from the picture-compressed video signal and outputs the intermediate data. The second processing means receives the intermediate data from the first processing means and processes the intermediate data to output raster data for one frame at a frame frequency. The storage means stores the intermediate data for processing the intermediate data in the second processing means. The second processing means writes the intermediate data into the storage means at a frequency related to the picture rate and reads the raster data for one frame from the storage means at the frequency equal to the frame frequency.
摘要翻译：提供了一种用于将分组数据转换为光栅数据的解码器。分组数据包括关于图像压缩视频信号的数据和关于包括图像速率的图像格式的数据。解码器包括第一处理装置，第二处理装置和存储装置。第一处理装置将分组数据转换成中间数据，使得从图像压缩视频信号中消除图像压缩并输出中间数据。第二处理装置从第一处理装置接收中间数据，并处理中间数据，以帧频率输出一帧的光栅数据。存储装置将用于处理中间数据的中间数据存储在第二处理装置中。第二处理装置以与图像速率相关的频率将中间数据写入存储装置，并以等于帧频的频率从存储装置读取一帧的光栅数据。

3. 发明授权

US5677860A Overflow and underflow processing circuit of a binary adder 失效
标题翻译：二进制加法器的溢出和下溢处理电路
公开(公告)号：US5677860A
公开(公告)日：1997-10-14
申请号：US324643
申请日：1994-10-18
申请人： Minobu Yazawa , Natsuko Matsuo
发明人： Minobu Yazawa , Natsuko Matsuo
IPC分类号： G06F7/38 , G06F7/50 , G06F7/505 , G06F7/507 , G06F7/508 , G06F7/509 , G06F11/00
CPC分类号： G06F7/509 , G06F7/505 , G06F7/49921
摘要： Two input data X (7), Y (7), . . . , X (0), Y (0) are input to a plurality of full adders, and an overflow/underflow signal of each full adder is input to a full adder of a higher level. An overflow/underflow signal Co of the full adder of the most significant bit and data Y (7) are applied to an EXOR gate to obtain an exclusive OR. According to an output signal of the EXOR gate, an added output of each full adder or data Y (7) is selected by a selector, whereby a straight binary signal is output.
摘要翻译：两个输入数据X（7），Y（7），。。。，X（0），Y（0）被输入到多个全加器，并且每个全加器的溢出/下溢信号被输入到较高电平的全加器。最高有效位的全加器的溢出/下溢信号Co和数据Y（7）被施加到EXOR门以获得异或。根据EXOR门的输出信号，通过选择器选择每个全加器或数据Y（7）的相加输出，由此输出直的二进制信号。

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