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1. 发明授权

US06538237B1 Apparatus for holding a quartz furnace 有权
标题翻译：用于保持石英炉的装置
公开(公告)号：US06538237B1
公开(公告)日：2003-03-25
申请号：US10043057
申请日：2002-01-08
申请人： Ming-Hsun Yang , Chen-Mei Fan , Allan Wang , June-Yie Kao
发明人： Ming-Hsun Yang , Chen-Mei Fan , Allan Wang , June-Yie Kao
IPC分类号： F27B508
CPC分类号： H01L21/67098 , C30B25/08 , C30B31/10 , H01L21/68728
摘要： An apparatus for fixing the position of a quartz furnace tube in a semiconductor processing furnace is described. The furnace is of the type that has a cylindrical body possessing an open end through which the tube may be withdrawn, and a base postioned on the open end, wherein the tube includes a flange portion secured to the base through which gas may be withdrawn from or introduced into the furnace tube. The tube is coaxially disposed within the furnace body. The apparatus may include two clamp halves each has a half-circular shape for engaging the flange portion of the furnace tube onto the base, and a mounting means for mounting the two clamp halves to the base.
摘要翻译：描述了一种将石英炉管的位置固定在半导体加工炉中的装置。该炉具有一个具有开口端的圆柱形主体，管可以被抽出，并且一个基座位于开口端，其中该管包括固定到底部的凸缘部分，气体可通过该凸缘部分被从或引入炉管。管同轴地设置在炉体内。该装置可以包括两个夹具半部，每个具有用于将炉管的凸缘部分接合到基座上的半圆形形状，以及用于将两个夹具半部安装到基座的安装装置。

2. 发明申请

US20100276774A1 INTEGRATED CIRCUIT PACKAGE AND METHOD FOR FABRICATION THEREOF 有权
标题翻译：集成电路封装及其制造方法
公开(公告)号：US20100276774A1
公开(公告)日：2010-11-04
申请号：US12836477
申请日：2010-07-14
申请人： Yu-Lin YEN , Chen-Mei Fan
发明人： Yu-Lin YEN , Chen-Mei Fan
IPC分类号： H01L31/0203 , H01L31/02
CPC分类号： H01L27/14618 , H01L24/05 , H01L24/13 , H01L24/29 , H01L24/32 , H01L27/14683 , H01L2224/0401 , H01L2924/01019 , H01L2924/01078 , H01L2924/14
摘要： The invention provides an integrated circuit package and method of fabrication thereof. The integrated circuit package comprises an integrated circuit chip having a photosensitive device thereon; a bonding pad formed on an upper surface of the integrated circuit chip and electrically connected to the photosensitive device; a barrier formed between the bonding pad and the photosensitive device; and a conductive layer formed on a sidewall of the integrated circuit chip and electrically connected to the bonding pad. The barrier layer blocks overflow of the adhesive layer into a region, on which the photosensitive device is formed, to improve yield for fabricating the integrated circuit package.
摘要翻译：本发明提供一种集成电路封装及其制造方法。集成电路封装包括其上具有光敏器件的集成电路芯片; 焊盘，形成在集成电路芯片的上表面上并电连接到感光器件; 在焊盘和感光装置之间形成的屏障; 以及形成在集成电路芯片的侧壁上并电连接到接合焊盘的导电层。阻挡层阻止粘合剂层溢出到形成有感光装置的区域中，以提高制造集成电路封装的成品率。

3. 发明授权

US06191035B1 Recipe design to prevent tungsten (W) coating on wafer backside for those wafers with poly Si on wafer backside 有权
标题翻译：配方设计，以防止晶圆背面上的钨（W）涂层用于晶圆背面的多晶硅晶圆
公开(公告)号：US06191035B1
公开(公告)日：2001-02-20
申请号：US09313303
申请日：1999-05-17
申请人： Kuo-Hsien Cheng , Chen-Mei Fan
发明人： Kuo-Hsien Cheng , Chen-Mei Fan
IPC分类号： H01L2144
CPC分类号： H01L21/28568
摘要： In a CVD vacuum chamber processing system for depositing a blanket of refractory material, such as tungsten, upon a frontside of a semiconductor wafer, an inert gas, such as argon is directed to the backside of the wafer in a manner so as to prevent the chamber reaction gases from reacting with polysilicon or other materials on the backside of the wafer as well as to prevent the deposition of the blanket material on the backside of the wafer. This method alleviates the problems of particulate generation and loss of wafer backside datum surface due to the inadvertent buildup of unwanted materials. The wafer is placed on a heater platen and is secured by a specified range of vacuum pressures. The wafer is exposed to specified ranges of chamber pressure during the deposition phase. During the purge phase, the chamber pressure is reduced and the wafer chucking pressure is increased to a specified range. The method is terminated with the equalization of pressure between the front and backside of the wafer.
摘要翻译：在CVD真空室处理系统中，用于在半导体晶片的前侧沉积耐火材料（例如钨）的毯子，惰性气体例如氩气以这样的方式被引导到晶片的背面，以防止室反应气体与晶片背面的多晶硅或其他材料反应，以及防止覆盖材料沉积在晶片的背面。该方法由于无意的材料的无意积累而减轻了颗粒产生和晶片背面基准表面损失的问题。将晶片放置在加热器台板上并通过特定范围的真空压力固定。在沉积阶段，晶片暴露于规定范围的室压力。在清洗阶段期间，腔室压力降低，并且晶片夹紧压力增加到指定范围。该方法通过晶片的前侧和后侧之间的压力均衡来终止。

4. 发明授权

US08624383B2 Integrated circuit package and method for fabrication thereof 有权
标题翻译：集成电路封装及其制造方法
公开(公告)号：US08624383B2
公开(公告)日：2014-01-07
申请号：US12836477
申请日：2010-07-14
申请人： Yu-Lin Yen , Chen-Mei Fan
发明人： Yu-Lin Yen , Chen-Mei Fan
IPC分类号： H01L23/12
CPC分类号： H01L27/14618 , H01L24/05 , H01L24/13 , H01L24/29 , H01L24/32 , H01L27/14683 , H01L2224/0401 , H01L2924/01019 , H01L2924/01078 , H01L2924/14
摘要： The invention provides an integrated circuit package and method of fabrication thereof. The integrated circuit package comprises an integrated circuit chip having a photosensitive device thereon; a bonding pad formed on an upper surface of the integrated circuit chip and electrically connected to the photosensitive device; a barrier formed between the bonding pad and the photosensitive device; and a conductive layer formed on a sidewall of the integrated circuit chip and electrically connected to the bonding pad. The barrier layer blocks overflow of the adhesive layer into a region, on which the photosensitive device is formed, to improve yield for fabricating the integrated circuit package.
摘要翻译：本发明提供一种集成电路封装及其制造方法。集成电路封装包括其上具有光敏器件的集成电路芯片; 焊盘，形成在集成电路芯片的上表面上并电连接到感光器件; 在焊盘和感光装置之间形成的屏障; 以及形成在集成电路芯片的侧壁上并电连接到接合焊盘的导电层。阻挡层阻止粘合剂层溢出到形成有感光装置的区域中，以提高制造集成电路封装的成品率。

5. 发明授权

US08003442B2 Integrated cirucit package and method for fabrication thereof 有权
标题翻译：集成cirucit封装及其制造方法
公开(公告)号：US08003442B2
公开(公告)日：2011-08-23
申请号：US11878568
申请日：2007-07-25
申请人： Yu-Lin Yen , Chen-Mei Fan
发明人： Yu-Lin Yen , Chen-Mei Fan
IPC分类号： H01L21/00
CPC分类号： H01L27/14618 , H01L24/05 , H01L24/13 , H01L24/29 , H01L24/32 , H01L27/14683 , H01L2224/0401 , H01L2924/01019 , H01L2924/01078 , H01L2924/14
摘要： The invention provides an integrated circuit package and method of fabrication thereof. The integrated circuit package comprises an integrated circuit chip having a photosensitive device thereon; a bonding pad formed on an upper surface of the integrated circuit chip and electrically connected to the photosensitive device; a barrier formed between the bonding pad and the photosensitive device; and a conductive layer formed on a sidewall of the integrated circuit chip and electrically connected to the bonding pad. The barrier layer blocks overflow of the adhesive layer into a region, on which the photosensitive device is formed, to improve yield for fabricating the integrated circuit package.
摘要翻译：本发明提供一种集成电路封装及其制造方法。集成电路封装包括其上具有光敏器件的集成电路芯片; 焊盘，形成在集成电路芯片的上表面上并电连接到感光器件; 在焊盘和感光装置之间形成的屏障; 以及形成在集成电路芯片的侧壁上并电连接到接合焊盘的导电层。阻挡层阻止粘合剂层溢出到形成有感光装置的区域中，以提高制造集成电路封装的成品率。

6. 发明授权

US06742532B2 Cleaning container and method for cleaning LP furnace thermocouple sleeves 失效
标题翻译：清洗容器及清洗LP炉热电偶套筒的方法
公开(公告)号：US06742532B2
公开(公告)日：2004-06-01
申请号：US10043859
申请日：2002-01-09
申请人： Yung-Pin Lin , Chung-Ray Chen , Chen-Mei Fan , Chan-Chung Shu
发明人： Yung-Pin Lin , Chung-Ray Chen , Chen-Mei Fan , Chan-Chung Shu
IPC分类号： B08B304
CPC分类号： B08B3/04 , H01L21/67057 , H01L21/6735
摘要： A cleaning container and method for using the same for chemically cleaning elongated members including quartz thermocouple sleeves including a first body member and a second body member said first body member and second body member respectively forming a first containing space and a second containing space including a first means for reversibly compressively sealing the first body member and the second body member to a form a combined containing space for sealably holding a cleaning solution level; a cap member disposed at a distal end of the first body member said cap member including a second means for reversibly compressively sealing a first opening in communication with the first containing space; and, a second opening centrally disposed in a distal end of the second containing space said second opening including a third means for reversibly compressively sealing around at least one elongated member penetrating through said second opening.
摘要翻译：一种清洁容器及其用于化学清洁细长构件的方法，包括石英热电偶套管，包括第一主体构件和第二主体构件，所述第一主体构件和第二主体构件分别形成第一容纳空间和第二容纳空间，所述第二容纳空间包括第一用于将第一本体构件和第二本体构件可逆地压缩密封成用于密封地保持清洁溶液水平的组合容纳空间的装置; 帽构件，其设置在所述第一主体构件的远端处，所述盖构件包括用于可逆地压缩地密封与所述第一容纳空间连通的第一开口的第二装置; 并且中心地设置在所述第二容纳空间的远端中的第二开口，所述第二开口包括用于可逆地压缩地密封穿透所述第二开口的至少一个细长构件的第三装置。

7. 发明申请

US20080230860A1 Integrated cirucit package and method for fabrication thereof 有权
标题翻译：集成cirucit封装及其制造方法
公开(公告)号：US20080230860A1
公开(公告)日：2008-09-25
申请号：US11878568
申请日：2007-07-25
申请人： Yu-Lin Yen , Chen-Mei Fan
发明人： Yu-Lin Yen , Chen-Mei Fan
IPC分类号： H01L31/0216 , H01L31/18
CPC分类号： H01L27/14618 , H01L24/05 , H01L24/13 , H01L24/29 , H01L24/32 , H01L27/14683 , H01L2224/0401 , H01L2924/01019 , H01L2924/01078 , H01L2924/14
摘要： The invention provides an integrated circuit package and method of fabrication thereof. The integrated circuit package comprises an integrated circuit chip having a photosensitive device thereon; a bonding pad formed on an upper surface of the integrated circuit chip and electrically connected to the photosensitive device, a barrier formed between the bonding pad and the photosensitive device; and a conductive layer formed on a sidewall of the integrated circuit chip and electrically connected to the bonding pad. The barrier layer blocks overflow of the adhesive layer into a region, on which the photosensitive device is formed, to improve yield for fabricating the integrated circuit package.
摘要翻译：本发明提供一种集成电路封装及其制造方法。集成电路封装包括其上具有光敏器件的集成电路芯片; 形成在所述集成电路芯片的上表面上并且电连接到所述感光装置的焊盘，形成在所述焊盘和所述感光装置之间的屏障; 以及形成在集成电路芯片的侧壁上并电连接到接合焊盘的导电层。阻挡层阻止粘合剂层溢出到形成有感光装置的区域中，以提高制造集成电路封装的成品率。

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