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1. 发明申请

US20060184772A1 Lookahead mode sequencer 失效
标题翻译：前瞻模式音序器
公开(公告)号：US20060184772A1
公开(公告)日：2006-08-17
申请号：US11055862
申请日：2005-02-11
申请人： Miles Dooley , Scott Frommer , Hung Le , Sheldon Levenstein , Anthony Saporito
发明人： Miles Dooley , Scott Frommer , Hung Le , Sheldon Levenstein , Anthony Saporito
IPC分类号： G06F9/30
CPC分类号： G06F9/3836 , G06F9/3855 , G06F9/3857 , G06F9/3867
摘要： A method, system, and computer program product for enhancing performance of an in-order microprocessor with long stalls. In particular, the mechanism of the present invention provides a data structure for storing data within the processor. The mechanism of the present invention comprises a data structure including information used by the processor. The data structure includes a group of bits to keep track of which instructions preceded a rejected instruction and therefore will be allowed to complete and which instructions follow the rejected instruction. The group of bits comprises a bit indicating whether a reject was a fast or slow reject; and a bit for each cycle that represents a state of an instruction passing through a pipeline. The processor speculatively continues to execute a set bit's corresponding instruction during stalled periods in order to generate addresses that will be needed when the stall period ends and normal dispatch resumes.
摘要翻译：一种方法，系统和计算机程序产品，用于增强具有长档位的按顺序微处理器的性能。特别地，本发明的机构提供了一种用于在处理器内存储数据的数据结构。本发明的机构包括包括由处理器使用的信息的数据结构。数据结构包括一组比特，用于跟踪被拒绝指令之前的哪些指令，因此将被允许完成，以及哪些指令遵循被拒绝的指令。该比特组包括指示拒绝是否是快速或慢速拒绝的位; 以及表示通过管道的指令的状态的每个周期的一点。处理器推测地在停滞时段期间继续执行设置位的相应指令，以便产生在停滞期结束并且恢复正常调度时将需要的地址。

2. 发明申请

US20060184739A1 Mechanism in a multi-threaded microprocessor to maintain best case demand instruction redispatch 有权
公开(公告)号：US20060184739A1
公开(公告)日：2006-08-17
申请号：US11055818
申请日：2005-02-11
申请人： Scott Frommer , Sheldon Levenstein , Bruce Ronchetti , Anthony Saporito
发明人： Scott Frommer , Sheldon Levenstein , Bruce Ronchetti , Anthony Saporito
IPC分类号： G06F12/00
CPC分类号： G06F9/383 , G06F9/3836 , G06F9/384 , G06F9/3842 , G06F9/3851 , G06F9/3857 , G06F9/3861 , G06F12/0897
摘要： A method and system for maintaining a best-case demand redispatch of an instruction to allow for maximizing the time a rejected thread may execute in lookahead execution mode, while maintaining the smallest L1 cache miss penalty supported by the memory subsystem. In response to a demand miss, a load/store unit sends a fetch request to the next level cache. The cache line of the demand miss is examined to identify the critical sector. Once the critical sector is identified, a best-case data return time is determined based on the fastest time the next level cache is able to return the critical sector of the cache line. The load/store unit then sends a speculative warning to the dispatch unit to coincide with the best-case data return, wherein the speculative warning prepares the dispatch unit to resend the instruction for execution as soon as data is available to the processor core.

3. 发明申请

US20060184741A1 Method, apparatus, and computer program product for sharing data in a cache among threads in an SMT processor 有权
标题翻译：用于在SMT处理器的线程之间共享缓存中的数据的方法，装置和计算机程序产品
公开(公告)号：US20060184741A1
公开(公告)日：2006-08-17
申请号：US11055820
申请日：2005-02-11
申请人： David Hrusecky , Sheldon Levenstein , Bruce Ronchetti , Anthony Saporito
发明人： David Hrusecky , Sheldon Levenstein , Bruce Ronchetti , Anthony Saporito
IPC分类号： G06F12/00
CPC分类号： G06F12/0842 , G06F12/084 , G06F12/0862
摘要： A method, apparatus, and computer program product are disclosed in a data processing system for sharing data in a cache among multiple threads in a simultaneous multi-threaded (SMT) processor. The SMT processor executes multiple threads concurrently during each clock cycle. The cache is dynamically allocated for use among the multiple threads. Portions of the cache are capable of being designated to store private data that is used exclusively by only a first one of the threads. The portions of the cache are capable of being designated to store shared data that can be used by any one of the multiple threads. The size of the portions can be changed dynamically during execution of the threads.
摘要翻译：在用于在同时多线程（SMT）处理器中的多个线程之间的高速缓存中共享数据的数据处理系统中公开了一种方法，装置和计算机程序产品。 SMT处理器在每个时钟周期内同时执行多个线程。动态分配缓存以在多个线程之间使用。高速缓存的一部分能够被指定为仅存储第一个线程专用的专用数据。高速缓存的部分能够被指定为存储可由多个线程中的任何一个使用的共享数据。在执行线程期间，可以动态地更改部分的大小。

4. 发明申请

US20060179227A1 Mechanism and apparatus allowing an N-way set associative cache, implementing a hybrid pseudo-LRU replacement algorithm, to have N L1 miss fetch requests simultaneously inflight regardless of their congruence class 有权
标题翻译：允许N路组关联高速缓存的机制和装置，实现混合伪LRU替换算法，以使N L1未命中提取请求同时运行，而不管其一致等级
公开(公告)号：US20060179227A1
公开(公告)日：2006-08-10
申请号：US11054293
申请日：2005-02-09
申请人： David Hrusecky , Sheldon Levenstein , Bruce Ronchetti , Anthony Saporito
发明人： David Hrusecky , Sheldon Levenstein , Bruce Ronchetti , Anthony Saporito
IPC分类号： G06F12/00
CPC分类号： G06F12/0859 , G06F12/124 , G06F12/125 , G06F12/127
摘要： A method, system, and computer program product for supporting multiple fetch requests to the same congruence class in an n-way set associative cache. Responsive to receiving an incoming fetch instruction at a load/store unit, outstanding valid fetch entries in the n-way set associative cache that have the same cache congruence class as the incoming fetch instruction are identified. SetIDs in used by these identified outstanding valid fetch entries are determined. A resulting setID is assigned to the incoming fetch instruction based on the identified setIDs, wherein the resulting setID assigned is a setID not currently in use by the outstanding valid fetch entries. The resulting setID for the incoming fetch instruction is written in a corresponding entry in the n-way set associative cache.
摘要翻译：一种方法，系统和计算机程序产品，用于在n路组关联高速缓存中支持对同一个同余类的多个提取请求。响应于在加载/存储单元处接收到传入的取指令，识别n路组关联高速缓冲存储器中具有与传入获取指令相同的高速缓存一致类的未完成的有效提取条目。确定这些识别的未完成的有效提取条目使用的SetID。所得到的setID被分配给基于所识别的setID的传入获取指令，其中分配的所得到的setID是未被提交的有效提取条目当前未使用的setID。用于传入提取指令的结果setID写入n路组关联高速缓存中的相应条目。

5. 发明申请

US20060179221A1 System and method for tracking changes in L1 data cache directory 有权
标题翻译：用于跟踪L1数据缓存目录中的更改的系统和方法
公开(公告)号：US20060179221A1
公开(公告)日：2006-08-10
申请号：US11054273
申请日：2005-02-09
申请人： Sheldon Levenstein , Anthony Saporito
发明人： Sheldon Levenstein , Anthony Saporito
IPC分类号： G06F12/00
CPC分类号： G06F12/0855
摘要： Method, system and computer program product for tracking changes in an L1 data cache directory. A method for tracking changes in an L1 data cache directory determines if data to be written to the L1 data cache is to be written to an address to be changed from an old address to a new address. If it is determined that the data to be written is to be written to an address to be changed, a determination is made if the data to be written is associated with the old address or the new address. If it is determined that the data is to be written to the new address, the data is allowed to be written to the new address following a prescribed delay after the address to be changed is changed. The method is preferably implemented in a system that provides a Store Queue (STQU) design that includes a Content Addressable Memory (CAM)-based store address tracking mechanism that includes early and late write CAM ports. The method eliminates time windows and the need for an extra copy of the L1 data cache directory.
摘要翻译：方法，系统和计算机程序产品，用于跟踪L1数据缓存目录中的更改。用于跟踪L1数据高速缓存目录中的变化的方法确定要写入L1数据高速缓存的数据是否被写入要从旧地址改变到新地址的地址。如果确定要写入的数据要写入要改变的地址，则确定要写入的数据是否与旧地址或新地址相关联。如果确定要将数据写入新地址，则在要更改的地址改变之后，允许将数据写入到遵循规定延迟的新地址。该方法优选地在提供包括基于内容寻址存储器（CAM）的存储地址跟踪机制的存储队列（STQU）设计的系统中实现，该机制包括早期和晚期写入CAM端口。该方法消除了时间窗口，并需要额外的L1数据高速缓存目录副本。

6. 发明申请

US20060184822A1 Auxiliary mechanism to manage instruction restart and restart coming in a lookahead processor 有权
标题翻译：辅助机制，用于管理指令重新启动和重新启动进入前瞻处理器
公开(公告)号：US20060184822A1
公开(公告)日：2006-08-17
申请号：US11055844
申请日：2005-02-11
申请人： Miles Dooley , Joaquin Hinojosa , Bruce Ronchetti , Anthony Saporito
发明人： Miles Dooley , Joaquin Hinojosa , Bruce Ronchetti , Anthony Saporito
IPC分类号： G06F11/00
CPC分类号： G06F9/3861 , G06F9/3842 , G06F11/141
摘要： A management system that controls a restart interface in a data processing system. The management system switches control of the interface from a distributed network managed by the caches to the management system. The management system is capable of detecting errors and seizing control of the interface in order to remedy any errors that occur within the interface.
摘要翻译：控制数据处理系统中的重启界面的管理系统。管理系统将接口控制从高速缓存管理的分布式网络切换到管理系统。管理系统能够检测错误并占用接口的控制，以补救接口内发生的任何错误。

7. 发明授权

US09442737B2 Restricting processing within a processor to facilitate transaction completion 有权
公开(公告)号：US09442737B2
公开(公告)日：2016-09-13
申请号：US13524833
申请日：2012-06-15
申请人： Khary J. Alexander , Brenton F. Belmar , Christian Jacobi , Randall W. Philley , Anthony Saporito , Timothy J. Slegel
发明人： Khary J. Alexander , Brenton F. Belmar , Christian Jacobi , Randall W. Philley , Anthony Saporito , Timothy J. Slegel
IPC分类号： G06F9/30 , G06F9/38 , G06F9/52 , G06F9/46
CPC分类号： G06F9/3861 , G06F9/3004 , G06F9/30087 , G06F9/38 , G06F9/3857 , G06F9/466 , G06F9/467 , G06F9/52 , G06F9/524
摘要： Processing of transactions within a computing environment is facilitated by taking actions to increase the chances of successfully executing a transaction. A counter is maintained that provides a count of how often a transaction has aborted. The counter increments the count each time the transaction is aborted, and it is reset to zero upon successful completion of the transaction or an interruption leading to no more re-executions of the transaction. If the count reaches a threshold value, then an interrupt is presented and transaction execution is unsuccessful. However, before the count reaches the threshold, a number of actions may be taken to increase the chances of successfully executing the transaction. These actions include actions to be performed within the processor executing the transaction, and/or actions to be performed against conflicting processors.

8. 发明授权

US08972665B2 Cache set selective power up 有权
标题翻译：缓存设置选择上电
公开(公告)号：US08972665B2
公开(公告)日：2015-03-03
申请号：US13524574
申请日：2012-06-15
申请人： Brian R. Prasky , Anthony Saporito , Aaron Tsai
发明人： Brian R. Prasky , Anthony Saporito , Aaron Tsai
IPC分类号： G06F1/32 , G06F21/81 , G06F17/30
CPC分类号： G06F1/3275 , G06F9/3802 , G06F12/0864 , G06F17/30982 , G06F2212/1028 , G06F2212/6082 , Y02D10/13
摘要： Embodiments of the disclosure include selectively powering up a cache set of a multi-set associative cache by receiving an instruction fetch address and determining that the instruction fetch address corresponds to one of a plurality of entries of a content addressable memory. Based on determining that the instruction fetch address corresponds to one of a plurality of entries of a content addressable memory a cache set of the multi-set associative cache that contains a cache line referenced by the instruction fetch address is identified and only powering up a subset of cache. Based on the identified cache set not being powered up, selectively powering up the identified cache set of the multi-set associative cache and transmitting one or more instructions stored in the cache line referenced by the instruction fetch address to a processor.
摘要翻译：本公开的实施例包括通过接收指令获取地址并且确定指令获取地址对应于内容可寻址存储器的多个条目之一来选择性地加电多组关联高速缓存的高速缓存组。基于确定指令获取地址对应于内容可寻址存储器的多个条目中的一个，识别包含由指令获取地址引用的高速缓存行的多组关联高速缓存的高速缓存集，并且仅为子集的缓存。基于所识别的未被加电的高速缓存集，选择性地加电多组关联高速缓存的所识别的高速缓存集，并且将由指令提取地址引用的高速缓存行中存储的一个或多个指令发送到处理器。

9. 发明授权

US08874885B2 Mitigating lookahead branch prediction latency by purposely stalling a branch instruction until a delayed branch prediction is received or a timeout occurs 有权
标题翻译：通过故意停止分支指令，直到接收到延迟的分支预测或发生超时来减轻前瞻分支预测等待时间
公开(公告)号：US08874885B2
公开(公告)日：2014-10-28
申请号：US12029543
申请日：2008-02-12
申请人： James J. Bonanno , David S. Hutton , Brian R. Prasky , Anthony Saporito
发明人： James J. Bonanno , David S. Hutton , Brian R. Prasky , Anthony Saporito
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/3844 , G06F9/3806 , G06F9/3836 , G06F9/3848
摘要： Embodiments relate to mitigation of lookahead branch predication latency. An aspect includes receiving an instruction address in an instruction cache for fetching instructions in a microprocessor pipeline. Another aspect includes receiving the instruction address in a branch presence predictor coupled to the microprocessor pipeline. Another aspect includes determining, by the branch presence predictor, presence of a branch instruction in the instructions being fetched, wherein the branch instruction is predictable by the branch target buffer, and any indication of the instruction address not written to the branch target buffer is also not written to the branch presence predictor. Another aspect includes, based on receipt of an indication that the branch instruction is present from the branch presence predictor, holding the branch instruction. Another aspect includes, based on receipt of a branch prediction corresponding to the branch instruction from the branch target buffer, releasing said held branch instruction to the pipeline.
摘要翻译：实施例涉及减轻前瞻分支预测延迟。一个方面包括在指令高速缓存中接收用于在微处理器流水线中取指令的指令地址。另一方面包括在耦合到微处理器流水线的分支存在预测器中接收指令地址。另一方面包括通过分支存在预测器确定在所取出的指令中存在分支指令，其中分支指令可由分支目标缓冲器预测，并且未写入分支目标缓冲器的指令地址的任何指示也是没有写入分支存在预测器。另一方面包括：基于从分支存在预测器接收到分支指令的指示，保持分支指令。另一方面包括基于从分支目标缓冲器接收到与分支指令相对应的分支预测，将所述保持的分支指令释放到流水线。

10. 发明申请

US20130339696A1 SELECTIVELY BLOCKING BRANCH INSTRUCTION PREDICTION 有权
标题翻译：选择性阻塞分支指导预测
公开(公告)号：US20130339696A1
公开(公告)日：2013-12-19
申请号：US13524402
申请日：2012-06-15
申请人： James J. Bonanno , Ulrich Mayer , Anthony Saporito , Chung-Lung K. Shum , Timothy J. Slegel
发明人： James J. Bonanno , Ulrich Mayer , Anthony Saporito , Chung-Lung K. Shum , Timothy J. Slegel
IPC分类号： G06F9/38
CPC分类号： G06F9/38 , G06F9/30076 , G06F9/3844 , G06F9/3848
摘要： Embodiments relate to selectively blocking branch instruction predictions. An aspect includes a computer system for performing selective branch prediction. The system includes memory and a processor, and the system is configured to perform a method. The method includes detecting a branch-prediction blocking instruction in a stream of instructions and blocking branch prediction of a predetermined number of branch instructions following the branch-prediction blocking instruction based on the detecting the branch-prediction blocking instruction.
摘要翻译：实施例涉及选择性地阻止分支指令预测。一个方面包括用于执行选择性分支预测的计算机系统。系统包括存储器和处理器，并且系统被配置为执行方法。该方法包括：根据检测分支预测阻断指令，在分支预测阻塞指令之后检测指令流中的分支预测分块指令并阻止预分支数量的分支指令的分支预测。

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