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1. 发明申请

US20190171380A1 Combined Transparent/Non-Transparent Cache 审中-公开
公开(公告)号：US20190171380A1
公开(公告)日：2019-06-06
申请号：US16266320
申请日：2019-02-04
申请人： Apple Inc.
发明人： James Wang , Zongjian Chen , James B. Keller , Timothy J. Millet
IPC分类号： G06F3/06 , G06F12/0846 , G06F12/0864 , G06F12/123 , G06F12/0877 , G06F12/0831 , G06F12/0802 , G06F12/0853
CPC分类号： G06F3/0631 , G06F3/0604 , G06F3/0638 , G06F3/0673 , G06F12/0802 , G06F12/0831 , G06F12/0848 , G06F12/0853 , G06F12/0864 , G06F12/0877 , G06F12/125 , G06F2212/1021 , G06F2212/2515 , G06F2212/282 , G06F2212/601 , G06F2212/62 , Y02D10/13
摘要： In one embodiment, a memory that is delineated into transparent and non-transparent portions. The transparent portion may be controlled by a control unit coupled to the memory, along with a corresponding tag memory. The non-transparent portion may be software controlled by directly accessing the non-transparent portion via an input address. In an embodiment, the memory may include a decoder configured to decode the address and select a location in either the transparent or non-transparent portion. Each request may include a non-transparent attribute identifying the request as either transparent or non-transparent. In an embodiment, the size of the transparent portion may be programmable. Based on the non-transparent attribute indicating transparent, the decoder may selectively mask bits of the address based on the size to ensure that the decoder only selects a location in the transparent portion.

2. 发明申请

US20170132131A1 Combined Transparent/Non-Transparent Cache 审中-公开
公开(公告)号：US20170132131A1
公开(公告)日：2017-05-11
申请号：US15352693
申请日：2016-11-16
申请人： Apple Inc.
发明人： James Wang , Zongjian Chen , James B. Keller , Timothy J. Millet
IPC分类号： G06F12/0846 , G06F12/0853
CPC分类号： G06F3/0631 , G06F3/0604 , G06F3/0638 , G06F3/0673 , G06F12/0802 , G06F12/0831 , G06F12/0848 , G06F12/0853 , G06F12/0864 , G06F12/0877 , G06F12/125 , G06F2212/1021 , G06F2212/2515 , G06F2212/282 , G06F2212/601 , G06F2212/62 , Y02D10/13
摘要： In one embodiment, a memory that is delineated into transparent and non-transparent portions. The transparent portion may be controlled by a control unit coupled to the memory, along with a corresponding tag memory. The non-transparent portion may be software controlled by directly accessing the non-transparent portion via an input address. In an embodiment, the memory may include a decoder configured to decode the address and select a location in either the transparent or non-transparent portion. Each request may include a non-transparent attribute identifying the request as either transparent or non-transparent. In an embodiment, the size of the transparent portion may be programmable. Based on the non-transparent attribute indicating transparent, the decoder may selectively mask bits of the address based on the size to ensure that the decoder only selects a location in the transparent portion.

3. 发明申请

US20160321189A1 MRU BATCHING TO REDUCE LOCK CONTENTION 有权
标题翻译： MRU批量减少锁定内容
公开(公告)号：US20160321189A1
公开(公告)日：2016-11-03
申请号：US14701182
申请日：2015-04-30
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Kevin J. ASH , Lokesh M. GUPTA , Matthew J. KALOS
IPC分类号： G06F12/12 , G06F12/08
CPC分类号： G06F12/125 , G06F12/0833 , G06F12/128 , G06F2212/62
摘要： Data operations, requiring a lock, are batched into a set of operations to be performed on a per-core basis under a single lock. A Most Recently Used (MRU) listing is used to conduct a demotion scan using an MRU flush, a processor identification (ID), and a track change characteristic algorithm.
摘要翻译：需要锁定的数据操作被分批到一组操作中，以在单个锁定下在每个核心的基础上执行。最近使用的（MRU）列表用于使用MRU刷新，处理器标识（ID）和轨道变化特征算法进行降级扫描。

4. 发明授权

US07627719B2 Cache device and method for determining LRU identifier by pointer values 失效
标题翻译：用于通过指针值确定LRU标识符的缓存设备和方法
公开(公告)号：US07627719B2
公开(公告)日：2009-12-01
申请号：US11597494
申请日：2005-02-18
申请人： Deyuan Wang
发明人： Deyuan Wang
IPC分类号： G06F12/00
CPC分类号： G06F12/125 , G06F12/0866 , G06F12/123
摘要： The invention provides a cache device and method for performing a cache process on a cache memory having a high capacity in a high speed. The cache processing section performs a cache process composed of two-stage processes, a query process (P1) and a subsequent process (P2). In the query process (P1), the respective index tables and the identifier table are used to query whether the target identifier is present in the cache memory at a step (S101). If it is present, a data address of the target identifier in the cache memory is transmitted to the CPU. Otherwise, a data address of an identifier for a previously prepared ultimate LRU in the cache memory is transmitted to the CPU at a step (S102). In a subsequent process (P2), adjustment operations for the respective tables, regarding insertion of an identifier for a new data and deletion of the identifier for the ultimate LRU data, are performed at a step (S201).
摘要翻译：本发明提供了一种用于在具有高容量的高速缓冲存储器中执行高速缓存处理的缓存装置和方法。高速缓存处理部分执行由两阶段处理，查询处理（P1）和后续处理（P2）组成的高速缓存处理。在查询处理（P1）中，使用相应的索引表和标识符表来在步骤（S101）查询目标标识符是否存在于高速缓冲存储器中。如果存在，则将高速缓冲存储器中的目标标识符的数据地址发送到CPU。否则，在步骤（S102）向CPU发送高速缓冲存储器中预先准备的最终LRU的标识符的数据地址。在后续处理（P2）中，在步骤（S201）中执行关于插入新数据的标识符和删除最终LRU数据的各个表的调整操作。

5. 发明授权

US07321954B2 Method for software controllable dynamically lockable cache line replacement system 有权
标题翻译：软件可控动态锁定缓存线替换系统的方法
公开(公告)号：US07321954B2
公开(公告)日：2008-01-22
申请号：US10915982
申请日：2004-08-11
申请人： James N. Dieffenderfer , Richard W. Doing , Brian E. Frankel , Kenichi Tsuchiya
发明人： James N. Dieffenderfer , Richard W. Doing , Brian E. Frankel , Kenichi Tsuchiya
IPC分类号： G06F13/16 , G06F13/00
CPC分类号： G06F12/126 , G06F12/125
摘要： An LRU array and method for tracking the accessing of lines of an associative cache. The most recently accessed lines of the cache are identified in the table, and cache lines can be blocked from being replaced. The LRU array contains a data array having a row of data representing each line of the associative cache, having a common address portion. A first set of data for the cache line identifies the relative age of the cache line for each way with respect to every other way. A second set of data identifies whether a line of one of the ways is not to be replaced. For cache line replacement, the cache controller will select the least recently accessed line using contents of the LRU array, considering the value of the first set of data, as well as the value of the second set of data indicating whether or not a way is locked. Updates to the LRU occur after each pre-fetch or fetch of a line or when it replaces another line in the cache memory.
摘要翻译：用于跟踪关联高速缓存行的访问的LRU数组和方法。缓存中最近访问的行在表中标识，并且可以阻止缓存行被替换。 LRU阵列包含具有代表相关高速缓存的每行的数据行的数据阵列，其具有公共地址部分。高速缓存行的第一组数据相对于每隔一个方式识别每个方式的高速缓存行的相对年龄。第二组数据识别一条路线是否不被替换。对于高速缓存行替换，高速缓存控制器将使用LRU阵列的内容来选择最近访问的行，考虑第一组数据的值，以及第二组数据的值，指示一种方式是否为锁定对LRU的更新发生在每个预取或提取行之后，或者替换高速缓存中的另一行时。

6. 发明授权

US07284094B2 Mechanism and apparatus allowing an N-way set associative cache, implementing a hybrid pseudo-LRU replacement algorithm, to have N L1 miss fetch requests simultaneously inflight regardless of their congruence class 有权
标题翻译：允许N路组关联高速缓存的机制和装置，实现混合伪LRU替换算法，以使N L1未命中获取请求同时运行，而不管其一致等级
公开(公告)号：US07284094B2
公开(公告)日：2007-10-16
申请号：US11054293
申请日：2005-02-09
申请人： David Allen Hrusecky , Sheldon B. Levenstein , Bruce Joseph Ronchetti , Anthony Saporito
发明人： David Allen Hrusecky , Sheldon B. Levenstein , Bruce Joseph Ronchetti , Anthony Saporito
IPC分类号： G06F12/00
CPC分类号： G06F12/0859 , G06F12/124 , G06F12/125 , G06F12/127
摘要： A method, system, and computer program product for supporting multiple fetch requests to the same congruence class in an n-way set associative cache. Responsive to receiving an incoming fetch instruction at a load/store unit, outstanding valid fetch entries in the n-way set associative cache that have the same cache congruence class as the incoming fetch instruction are identified. SetIDs in used by these identified outstanding valid fetch entries are determined. A resulting setID is assigned to the incoming fetch instruction based on the identified setIDs, wherein the resulting setID assigned is a setID not currently in use by the outstanding valid fetch entries. The resulting setID for the incoming fetch instruction is written in a corresponding entry in the n-way set associative cache.
摘要翻译：一种方法，系统和计算机程序产品，用于在n路组关联高速缓存中支持对同一个同余类的多个提取请求。响应于在加载/存储单元处接收到传入的取指令，识别n路组关联高速缓冲存储器中具有与传入获取指令相同的高速缓存一致类的未完成的有效提取条目。确定这些识别的未完成的有效提取条目使用的SetID。所得到的setID被分配给基于所识别的setID的传入获取指令，其中分配的所得到的setID是未被提交的有效提取条目当前未使用的setID。用于传入提取指令的结果setID写入n路组关联高速缓存中的相应条目。

7. 发明授权

US06338120B1 Apparatus for cache use history encoding and decoding including next lru and next mru and method therefor 失效
标题翻译：用于缓存使用历史编码和解码的装置，包括下一个下一个mru及其方法
公开(公告)号：US06338120B1
公开(公告)日：2002-01-08
申请号：US09259177
申请日：1999-02-26
申请人： Brian Patrick Hanley
发明人： Brian Patrick Hanley
IPC分类号： G06F1200
CPC分类号： G06F12/128 , G06F12/0862 , G06F12/125
摘要： An apparatus for encoding/decoding an associative cache set use history, and method therefor, is implemented. A five-bit signal is used to fully encode a four-way cache. A least recently used (LRU) set is encoded using a first bit pair, and a second bit pair encodes a most recently used (MRU) set. The sets having intermediate usage are encoded by a remaining single bit. The single bit has a first predetermined value when the sets having intermediate usage have an in-order relationship in accordance with a predetermined ordering of the cache sets. The single bit has a second predetermined value when the sets having intermediate usage have an out-of-order relationship.
摘要翻译：一种用于编码/解码关联高速缓存集使用历史的装置及其方法。五位信号用于对四路缓存进行完全编码。使用第一位对编码最近最少使用的（LRU）集合，并且第二位对对最近使用的（MRU）集合进行编码。具有中间使用的集合由剩余的单个位编码。当具有中间使用的集合根据高速缓存集的预定顺序具有顺序关系时，单个位具有第一预定值。当具有中间使用的集合具有无序关系时，单个位具有第二预定值。

8. 发明授权

US5471605A Apparatus for updating a multi-way set associative cache memory status array 失效
标题翻译：用于更新多路组关联chache存储器状态阵列中的状态位的装置
公开(公告)号：US5471605A
公开(公告)日：1995-11-28
申请号：US384622
申请日：1995-02-06
申请人： William M. Ruby
发明人： William M. Ruby
IPC分类号： G06F12/08 , G06F12/12 , G06F12/00 , G11C7/00
CPC分类号： G06F12/0893 , G06F12/125 , G06F12/0864
摘要： A method and apparatus for updating cache memory status bits that depend on match signals of a multi-way set associative cache are disclosed. Faster updating of the status bits is provided by utilizing the fact that there is a match in at most one way of the cache for any read cycle. A first status bit is set to its previous value if no match occurs in any way of the cache. The first status bit is set to a first value if a match has occurred in a first way of the cache and is set to a second value if a match has occurred in a second way of the cache. Fewer transistors are needed to implement the update circuits which, in a preferred embodiment, are realized using complementary metal oxide semiconductor (CMOS) technology. The update circuits may be implemented in an instruction cache translation look aside buffer of a microprocessor for updating least recently used (LRU) array status bits or any cache memory status signals that depend on match signals.
摘要翻译：公开了一种用于更新取决于多路组相关高速缓存的匹配信号的高速缓冲存储器状态位的方法和装置。通过利用对于任何读取周期最多只有一种缓存的方式匹配的事实来提供状态位的更快更新。如果高速缓存中没有任何匹配，则将第一个状态位设置为其先前的值。如果匹配发生在高速缓存的第一种方式中，则将第一个状态位设置为第一个值，如果以高速缓存的第二种方式发生了匹配，则将其设置为第二个值。需要更少的晶体管来实现在优选实施例中使用互补金属氧化物半导体（CMOS）技术实现的更新电路。更新电路可以在用于更新最近最少使用（LRU）阵列状态位或依赖于匹配信号的任何高速缓存存储器状态信号的微处理器的指令高速缓存转换旁边的缓冲器中实现。

9. 发明授权

US4229789A System for transferring data between high speed and low speed memories 失效
标题翻译：用于在高速和低速存储器之间传输数据的系统
公开(公告)号：US4229789A
公开(公告)日：1980-10-21
申请号：US863637
申请日：1977-12-22
申请人： Douglas J. Morgan , Barry S. Manis
发明人： Douglas J. Morgan , Barry S. Manis
IPC分类号： G06F12/12 , G11C9/06 , G06F13/00
CPC分类号： G06F12/125
摘要： A data transfer or replacement system for shifting blocks of data or pages between a high speed, low capacity, working memory and a low speed, high capacity backup store of a data processing system. Each block in the working memory is associated with an "A" and a "B" single bit register. Usage bits are initially inserted into the "A" registers as information from the block is utilized. After one-half of the "A" registers have been identified by associated usage bits, the "B" single bit registers are cleared, and usage bits are inserted into these "B" registers. When one-half of the "B" usage registers are "marked", the "A" registers are cleared and usage bits are then inserted in these "A" registers. Upon the necessity for introduction of additional data from the backup store into the high speed, low capacity working memory, least recently used blocks are identified as those whose associated "A" and "B" registers have not been marked. The new blocks of information are transferred from the backup store into one of the spaces in the high speed store containing such a block of least recently used data.
摘要翻译：数据传输或更换系统，用于在数据处理系统的高速，低容量，工作存储器和低速，高容量备份存储之间移动数据块或页面。工作存储器中的每个块与“A”和“B”单位寄存器相关联。使用位最初被插入到“A”寄存器中，因为来自块的信息被使用。在“A”寄存器的一半已经被关联的使用位识别后，“B”个单个寄存器被清零，并且使用位被插入到这些“B”寄存器中。当“B”使用寄存器的一半被“标记”时，“A”寄存器被清零，然后在这些“A”寄存器中插入使用位。在需要从备份存储器引入附加数据到高速，低容量工作存储器中时，最近最少使用的块被识别为没有标记其相关联的“A”和“B”寄存器的块。新的信息块从备份存储转移到高速存储器中的一个空间，其中包含最近最少使用的数据块。

10. 发明授权

US11960408B2 Semiconductor memory device including unit page buffer blocks having four page buffer pairs 有权
公开(公告)号：US11960408B2
公开(公告)日：2024-04-16
申请号：US18053003
申请日：2022-11-07
申请人： SK hynix Inc.
发明人： Dong Hyuk Kim , Tae Sung Park , Sang Hyun Sung , Sung Lae Oh , Soo Nam Jung
IPC分类号： G06F12/00 , G06F12/0882 , G06F12/0895 , G06F12/123
CPC分类号： G06F12/0895 , G06F12/0882 , G06F12/125
摘要： A unit page buffer block includes first to fourth page buffer pairs. Each of the page buffer pairs includes a common column decoder block; and an upper page buffer stage and a lower page buffer stage electrically and commonly connected to the common column decoder block. Each of the upper page buffer stages includes an upper selection block; an upper latch block; and an upper cache block. Each of the lower page buffer stage includes a lower selection block; a lower latch block; and a lower cache block. Each of the upper selection blocks includes first to fourth sub-selection blocks. Each of the upper and lower latch blocks includes first to twelfth upper sub-latch blocks. Each of the upper and lower cache blocks includes first to twelfth upper sub-cache blocks. Each of the common column decoder block includes first to third sub-common column decoder blocks arranged in a row direction.

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