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1. 发明授权

US08874885B2 Mitigating lookahead branch prediction latency by purposely stalling a branch instruction until a delayed branch prediction is received or a timeout occurs 有权
标题翻译：通过故意停止分支指令，直到接收到延迟的分支预测或发生超时来减轻前瞻分支预测等待时间
公开(公告)号：US08874885B2
公开(公告)日：2014-10-28
申请号：US12029543
申请日：2008-02-12
申请人： James J. Bonanno , David S. Hutton , Brian R. Prasky , Anthony Saporito
发明人： James J. Bonanno , David S. Hutton , Brian R. Prasky , Anthony Saporito
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/3844 , G06F9/3806 , G06F9/3836 , G06F9/3848
摘要： Embodiments relate to mitigation of lookahead branch predication latency. An aspect includes receiving an instruction address in an instruction cache for fetching instructions in a microprocessor pipeline. Another aspect includes receiving the instruction address in a branch presence predictor coupled to the microprocessor pipeline. Another aspect includes determining, by the branch presence predictor, presence of a branch instruction in the instructions being fetched, wherein the branch instruction is predictable by the branch target buffer, and any indication of the instruction address not written to the branch target buffer is also not written to the branch presence predictor. Another aspect includes, based on receipt of an indication that the branch instruction is present from the branch presence predictor, holding the branch instruction. Another aspect includes, based on receipt of a branch prediction corresponding to the branch instruction from the branch target buffer, releasing said held branch instruction to the pipeline.
摘要翻译：实施例涉及减轻前瞻分支预测延迟。一个方面包括在指令高速缓存中接收用于在微处理器流水线中取指令的指令地址。另一方面包括在耦合到微处理器流水线的分支存在预测器中接收指令地址。另一方面包括通过分支存在预测器确定在所取出的指令中存在分支指令，其中分支指令可由分支目标缓冲器预测，并且未写入分支目标缓冲器的指令地址的任何指示也是没有写入分支存在预测器。另一方面包括：基于从分支存在预测器接收到分支指令的指示，保持分支指令。另一方面包括基于从分支目标缓冲器接收到与分支指令相对应的分支预测，将所述保持的分支指令释放到流水线。

2. 发明申请

US20090204797A1 METHOD AND SYSTEM FOR MITIGATING LOOKAHEAD BRANCH PREDICTION LATENCY WITH BRANCH PRESENCE PREDICTION AT THE TIME OF INSTRUCTION FETCHING 有权
标题翻译：用于在指示期间缓解分支预测的预测分支预测方法和系统
公开(公告)号：US20090204797A1
公开(公告)日：2009-08-13
申请号：US12029543
申请日：2008-02-12
申请人： James J. Bonanno , David S. Hutton , Brian R. Prasky , Anthony Saporito
发明人： James J. Bonanno , David S. Hutton , Brian R. Prasky , Anthony Saporito
IPC分类号： G06F9/32
CPC分类号： G06F9/3844 , G06F9/3806 , G06F9/3836 , G06F9/3848
摘要： System and method for mitigating lookahead branch prediction latency with branch presence prediction at the time of instruction fetching. An exemplary embodiment includes a method for mitigating lookahead branch prediction latency, the method including receiving an instruction address in an instruction cache for fetching instructions in the microprocessor pipeline, receiving the instruction address in a branch presence predictor coupled to the microprocessor pipeline, and releasing instructions extracted from the instruction cache after determining that a branch prediction is available or unlikely to occur for instructions identified as potential predictable branches by the branch presence prediction.
摘要翻译：用于在指令获取时用分支存在预测来减轻前瞻分支预测延迟的系统和方法。一个示例性实施例包括一种用于减轻前瞻分支预测等待时间的方法，所述方法包括：在指令高速缓存中接收指令地址以获取微处理器流水线中的指令，在耦合到微处理器流水线的分支存在预测器中接收指令地址，以及释放指令在通过分支存在预测识别为潜在可预测分支的指令之后，在确定分支预测可用或不太可能发生之后从指令高速缓存提取。

3. 发明授权

US08443176B2 Method, system, and computer program product for reducing cache memory pollution 有权
标题翻译：方法，系统和计算机程序产品，用于减少缓存内存污染
公开(公告)号：US08443176B2
公开(公告)日：2013-05-14
申请号：US12037042
申请日：2008-02-25
申请人： Robert J. Sonnelitter, III , James J. Bonanno , David S. Hutton , Brian R. Prasky , Anthony Saporito
发明人： Robert J. Sonnelitter, III , James J. Bonanno , David S. Hutton , Brian R. Prasky , Anthony Saporito
IPC分类号： G06F9/00
CPC分类号： G06F9/3804 , G06F9/30058 , G06F12/0862 , G06F2212/1021
摘要： A method for reducing cache memory pollution including fetching an instruction stream from a cache line, preventing a fetching for the instruction stream from a sequential cache line, searching for a next predicted taken branch instruction, determining whether a length of the instruction stream extends beyond a length of the cache line based on the next predicted taken branch instruction, continuing preventing the fetching for the instruction stream from the sequential cache line if the length of the instruction stream does not extend beyond the length of the cache line, and allowing the fetching for the instruction stream from the sequential cache line if the length of the instruction stream extends beyond the length of the cache line, whereby the fetching from the sequential cache line and a resulting polluting of a cache memory that stores the instruction stream is minimized. A corresponding system and computer program product.
摘要翻译：一种用于减少高速缓冲存储器污染的方法，包括从高速缓存线取出指令流，阻止从顺序高速缓存线取出指令流，搜索下一个预测的分支指令，确定指令流的长度是否延伸超过基于下一个预测的分支指令的高速缓存线的长度，如果指令流的长度不超过高速缓存线的长度，则继续阻止从顺序高速缓存行获取指令流，并且允许取出如果指令流的长度延伸超过高速缓存行的长度，则来自顺序高速缓存行的指令流被最小化，从而从顺序高速缓存行的取出和存储指令流的高速缓冲存储器的产生的污染最小化。相应的系统和计算机程序产品。

4. 发明申请

US20090217003A1 METHOD, SYSTEM, AND COMPUTER PROGRAM PRODUCT FOR REDUCING CACHE MEMORY POLLUTION 有权
标题翻译：用于减少高速缓存存储器污染的方法，系统和计算机程序产品
公开(公告)号：US20090217003A1
公开(公告)日：2009-08-27
申请号：US12037042
申请日：2008-02-25
申请人： Robert J. Sonnelitter, III , James J. Bonanno , David S. Hutton , Brian R. Prasky , Anthony Saporito
发明人： Robert J. Sonnelitter, III , James J. Bonanno , David S. Hutton , Brian R. Prasky , Anthony Saporito
IPC分类号： G06F9/30
CPC分类号： G06F9/3804 , G06F9/30058 , G06F12/0862 , G06F2212/1021
摘要： A method for reducing cache memory pollution including fetching an instruction stream from a cache line, preventing a fetching for the instruction stream from a sequential cache line, searching for a next predicted taken branch instruction, determining whether a length of the instruction stream extends beyond a length of the cache line based on the next predicted taken branch instruction, continuing preventing the fetching for the instruction stream from the sequential cache line if the length of the instruction stream does not extend beyond the length of the cache line, and allowing the fetching for the instruction stream from the sequential cache line if the length of the instruction stream extends beyond the length of the cache line, whereby the fetching from the sequential cache line and a resulting polluting of a cache memory that stores the instruction stream is minimized. A corresponding system and computer program product.
摘要翻译：一种用于减少高速缓冲存储器污染的方法，包括从高速缓存线取出指令流，阻止从顺序高速缓存线取出指令流，搜索下一个预测的分支指令，确定指令流的长度是否延伸超过基于下一个预测的分支指令的高速缓存线的长度，如果指令流的长度不超过高速缓存线的长度，则继续阻止从顺序高速缓存行获取指令流，并且允许取出如果指令流的长度延伸超过高速缓存行的长度，则来自顺序高速缓存行的指令流被最小化，从而从顺序高速缓存行的取出和存储指令流的高速缓冲存储器的产生的污染最小化。相应的系统和计算机程序产品。

5. 发明申请

US20090217017A1 METHOD, SYSTEM AND COMPUTER PROGRAM PRODUCT FOR MINIMIZING BRANCH PREDICTION LATENCY 审中-公开
标题翻译：用于最小化分支预测延迟的方法，系统和计算机程序产品
公开(公告)号：US20090217017A1
公开(公告)日：2009-08-27
申请号：US12037137
申请日：2008-02-26
申请人： Khary J. Alexander , David S. Hutton , Brian R. Prasky , Anthony Saporito , Robert J. Sonnelitter, III , John W. Ward, III
发明人： Khary J. Alexander , David S. Hutton , Brian R. Prasky , Anthony Saporito , Robert J. Sonnelitter, III , John W. Ward, III
IPC分类号： G06F9/30
CPC分类号： G06F9/381 , G06F9/3806 , G06F9/3814
摘要： A method, system, and computer program product for minimizing branch prediction latency in a pipelined computer processing environment are provided. The method includes detecting a branch loop utilizing branch instruction addresses and corresponding target addresses stored in a branch target buffer (BTB). The method also includes fetching the branch loop into a pre-decode instruction buffer and qualifying the branch loop for loop lockdown. The method further includes locking an instruction stream that forms the branch loop in the pre-decode instruction buffer and processing qualified branch loop instructions from the buffer and powering down instruction fetching and branch prediction logic (BPL) associated with the BTB.
摘要翻译：提供了一种用于在流水线计算机处理环境中最小化分支预测延迟的方法，系统和计算机程序产品。该方法包括利用转移指令地址和存储在分支目标缓冲器（BTB）中的对应目标地址来检测分支回路。该方法还包括将分支循环读取到预解码指令缓冲器中，并对分支循环进行限定循环锁定。该方法还包括将形成分支循环的指令流锁定在预解码指令缓冲器中，并且处理来自缓冲器的限定分支循环指令并且断电与BTB相关联的指令获取和分支预测逻辑（BPL）。

6. 发明授权

US07971034B2 Reduced overhead address mode change management in a pipelined, recycling microprocessor 失效
标题翻译：在流水线回收微处理器中减少开销地址模式更改管理
公开(公告)号：US07971034B2
公开(公告)日：2011-06-28
申请号：US12051415
申请日：2008-03-19
申请人： David S. Hutton , Michael Billeci , Fadi Y. Busaba , Brian R. Prasky , John G. Rell, Jr. , Chung-Lung Kevin Shum , Charles F. Webb
发明人： David S. Hutton , Michael Billeci , Fadi Y. Busaba , Brian R. Prasky , John G. Rell, Jr. , Chung-Lung Kevin Shum , Charles F. Webb
IPC分类号： G06F9/00 , G06F9/44 , G06F9/30
CPC分类号： G06F9/30189 , G06F9/30076 , G06F9/342 , G06F9/3802 , G06F9/3824 , G06F9/3836 , G06F9/3861 , G06F9/3867
摘要： A method, system, and computer program product for reduced overhead address mode change management in a pipelined, recycling microprocessor are provided. The recycling microprocessor includes logic executing thereon. The microprocessor also includes an instruction fetch unit (IFU) supporting computation of address adds in selected address modes and reporting non-equal comparison of the computation to the logic. The microprocessor further includes a fixed point unit determining whether the mode has changed and reporting changes to the logic. Upon determining the comparison yields an equal result but the mode has changed, a recycle event is triggered to ensure subsequent ofetches are relaunched in the correct mode and that no execution writebacks occur from work performed in an incorrect mode. For comparisons yielding a non-equal result and a changed mode, the logic clears bits set in response to the determinations, and a serialization event is taken to reset a corresponding pipeline for operation in the correct mode.
摘要翻译：提供了一种用于在流水线式回收微处理器中减少开销地址模式改变管理的方法，系统和计算机程序产品。回收微处理器包括在其上执行的逻辑。微处理器还包括一个指令提取单元（IFU），用于支持在所选择的地址模式中添加的地址的计算，并且将该计算的不相等的比较报告给逻辑。微处理器还包括确定模式是否改变并且对逻辑进行报告改变的固定点单元。在确定比较时，产生相等的结果，但是模式已经改变，触发一个循环事件，以确保以正确的模式重新启动后续的提取，并且在不正确的模式下执行的工作不会执行执行回写。为了比较产生不相等的结果和改变的模式，逻辑清除响应于确定的位设置，并且采用串行化事件来复位相应的流水线以便以正确的模式进行操作。

7. 发明申请

US20090240929A1 METHOD, SYSTEM AND COMPUTER PROGRAM PRODUCT FOR REDUCED OVERHEAD ADDRESS MODE CHANGE MANAGEMENT IN A PIPELINED, RECYLING MICROPROCESSOR 失效
标题翻译：方法，系统和计算机程序产品，用于在管道，回收微处理器中减少地址模式更改管理
公开(公告)号：US20090240929A1
公开(公告)日：2009-09-24
申请号：US12051415
申请日：2008-03-19
申请人： David S. Hutton , Michael Billeci , Fadi Y. Busaba , Brian R. Prasky , John G. Rell, JR. , Chung-Lung Kevin Shum , Charles F. Webb
发明人： David S. Hutton , Michael Billeci , Fadi Y. Busaba , Brian R. Prasky , John G. Rell, JR. , Chung-Lung Kevin Shum , Charles F. Webb
IPC分类号： G06F9/312
CPC分类号： G06F9/30189 , G06F9/30076 , G06F9/342 , G06F9/3802 , G06F9/3824 , G06F9/3836 , G06F9/3861 , G06F9/3867
摘要： A method, system, and computer program product for reduced overhead address mode change management in a pipelined, recycling microprocessor are provided. The recycling microprocessor includes logic executing thereon. The microprocessor also includes an instruction fetch unit (IFU) supporting computation of address adds in selected address modes and reporting non-equal comparison of the computation to the logic. The microprocessor further includes a fixed point unit determining whether the mode has changed and reporting changes to the logic. Upon determining the comparison yields an equal result but the mode has changed, a recycle event is triggered to ensure subsequent ofetches are relaunched in the correct mode and that no execution writebacks occur from work performed in an incorrect mode. For comparisons yielding a non-equal result and a changed mode, the logic clears bits set in response to the determinations, and a serialization event is taken to reset a corresponding pipeline for operation in the correct mode.
摘要翻译：提供了一种用于在流水线式回收微处理器中减少开销地址模式改变管理的方法，系统和计算机程序产品。回收微处理器包括在其上执行的逻辑。微处理器还包括一个指令提取单元（IFU），用于支持在所选择的地址模式中添加的地址的计算，并且将该计算的不相等的比较报告给逻辑。微处理器还包括确定模式是否改变并且对逻辑进行报告改变的固定点单元。在确定比较时，产生相等的结果，但是模式已经改变，触发一个循环事件，以确保以正确的模式重新启动后续的提取，并且在不正确的模式下执行的工作不会执行执行回写。为了比较产生不相等的结果和改变的模式，逻辑清除响应于确定的位设置，并且采用串行化事件来复位相应的流水线以便以正确的模式进行操作。

8. 发明授权

US07895538B2 System and method for providing a common instruction table 有权
标题翻译：用于提供通用指令表的系统和方法
公开(公告)号：US07895538B2
公开(公告)日：2011-02-22
申请号：US12033974
申请日：2008-02-20
申请人： David S. Hutton , James J. Bonanno , Michael P. Mullen , Chung-Lung Kevin Shum
发明人： David S. Hutton , James J. Bonanno , Michael P. Mullen , Chung-Lung Kevin Shum
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F2217/68
摘要： A system includes a storage device including a human readable common instruction table (CIT) stored as a text file. The system also includes CIT access software for performing a method including receiving a request from a first user for all or a subset of the CIT table relating to logic design and for providing the requested data to the first user. The method also includes receiving a request from a second user is received for all or a subset of the CIT table relating to performance analysis and for providing the requested data to the second user. A request is received from a third user for all or a subset of the CIT data relating to design verification and the requested data is provided to the third user.
摘要翻译：系统包括存储装置，该存储装置包括作为文本文件存储的人可读公用指令表（CIT）。该系统还包括用于执行方法的CIT访问软件，该方法包括从第一用户接收与逻辑设计相关的CIT表的全部或子集的请求，以及向第一用户提供所请求的数据。该方法还包括接收来自与用于性能分析相关的CIT表的全部或子集的第二用户的请求，以及向第二用户提供所请求的数据。对于与设计验证相关的CIT数据的全部或子集，从第三用户接收请求，并且将所请求的数据提供给第三用户。

9. 发明申请

US20090210387A1 SYSTEM AND METHOD FOR PROVIDING A COMMON INSTRUCTION TABLE 有权
标题翻译：用于提供通用指令表的系统和方法
公开(公告)号：US20090210387A1
公开(公告)日：2009-08-20
申请号：US12033974
申请日：2008-02-20
申请人： David S. Hutton , James J. Bonanno , Michael P. Mullen , Chung-Lung Kevin Shum
发明人： David S. Hutton , James J. Bonanno , Michael P. Mullen , Chung-Lung Kevin Shum
IPC分类号： G06F17/30
CPC分类号： G06F17/5045 , G06F2217/68
摘要： A system includes a storage device including a human readable common instruction table (CIT) stored as a text file. The system also includes CIT access software for performing a method including receiving a request from a first user for all or a subset of the CIT table relating to logic design and for providing the requested data to the first user. The method also includes receiving a request from a second user is received for all or a subset of the CIT table relating to performance analysis and for providing the requested data to the second user. A request is received from a third user for all or a subset of the CIT data relating to design verification and the requested data is provided to the third user.
摘要翻译：系统包括存储装置，该存储装置包括作为文本文件存储的人可读公用指令表（CIT）。该系统还包括用于执行方法的CIT访问软件，该方法包括从第一用户接收与逻辑设计相关的CIT表的全部或子集的请求，以及向第一用户提供所请求的数据。该方法还包括接收来自与用于性能分析相关的CIT表的全部或子集的第二用户的请求，以及向第二用户提供所请求的数据。对于与设计验证相关的CIT数据的全部或子集，从第三用户接收请求，并且将所请求的数据提供给第三用户。

10. 发明申请

US20090240922A1 METHOD, SYSTEM, COMPUTER PROGRAM PRODUCT, AND HARDWARE PRODUCT FOR IMPLEMENTING RESULT FORWARDING BETWEEN DIFFERENTLY SIZED OPERANDS IN A SUPERSCALAR PROCESSOR 失效
标题翻译：方法，系统，计算机程序产品和用于在超级处理器中执行不同尺寸操作之前的结果的硬件产品
公开(公告)号：US20090240922A1
公开(公告)日：2009-09-24
申请号：US12051792
申请日：2008-03-19
申请人： David S. Hutton , Fadi Y. Busaba , Bruce C. Giamei , Christopher A. Krygowski , Edward T. Malley , Jeffrey S. Plate , John G. Rell, JR. , Chung-Lung Kevin Shum , Timothy J. Slegel
发明人： David S. Hutton , Fadi Y. Busaba , Bruce C. Giamei , Christopher A. Krygowski , Edward T. Malley , Jeffrey S. Plate , John G. Rell, JR. , Chung-Lung Kevin Shum , Timothy J. Slegel
IPC分类号： G06F9/30
CPC分类号： G06F9/3016 , G06F9/30036 , G06F9/3828
摘要： Result and operand forwarding is provided between differently sized operands in a superscalar processor by grouping a first set of instructions for operand forwarding, and grouping a second set of instructions for result forwarding, the first set of instructions comprising a first source instruction having a first operand and a first dependent instruction having a second operand, the first dependent instruction depending from the first source instruction; the second set of instructions comprising a second source instruction having a third operand and a second dependent instruction having a fourth operand, the second dependent instruction depending from the second source instruction, performing operand forwarding by forwarding the first operand, either whole or in part, as it is being read to the first dependent instruction prior to execution; performing result forwarding by forwarding a result of the second source instruction, either whole or in part, to the second dependent instruction, after execution; wherein the operand forwarding is performed by executing the first source instruction together with the first dependent instruction; and wherein the result forwarding is performed by executing the second source instruction together with the second dependent instruction.
摘要翻译：通过对用于操作数转发的第一组指令进行分组，以及对用于结果转发的第二组指令进行分组，在超标量处理器中的不同大小的操作数之间提供结果和操作数转发，所述第一组指令包括具有第一操作数的第一源指令以及具有第二操作数的第一依赖指令，所述第一依赖指令取决于所述第一源指令; 所述第二组指令包括具有第三操作数和第二从属指令的第二源指令，所述第三操作数和第二从属指令具有第四操作数，所述第二依赖指令取决于所述第二源指令，通过转发所述第一操作数全部或部分地执行操作数转发，因为它在执行之前被读取到第一个依赖指令; 执行结果转发，将第二源指令的结果全部或部分转发到第二依赖指令; 其中通过与第一依赖指令一起执行第一源指令来执行操作数转发; 并且其中通过与第二从属指令一起执行第二源指令来执行结果转发。

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