专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US5555261A Interface device between a network and an exchange for assembling fixed-length cell and transmitting the same 失效
标题翻译：网络和交换机之间的接口设备，用于组装固定长度的小区并传输
公开(公告)号：US5555261A
公开(公告)日：1996-09-10
申请号：US339541
申请日：1994-11-15
申请人： Mikio Nakayama , Tetsuo Tachibana , Youzou Iketani , Yuzo Okuyama , Satoshi Kakuma
发明人： Mikio Nakayama , Tetsuo Tachibana , Youzou Iketani , Yuzo Okuyama , Satoshi Kakuma
IPC分类号： H04Q3/00 , H04J3/06 , H04L12/70 , H04L12/951 , H04Q11/04 , H04L12/56
CPC分类号： H04J3/0632 , H04Q11/0478 , H04L2012/5615 , H04L2012/5616 , H04L2012/5652 , H04L2012/5654 , H04L2012/5674
摘要： An internal timing information producing portion produces internal timing information IRTS1 to IRTS4 which is the timing information on a data reception clock by using a network clock C.sub.N and the data reception clock C.sub.RU. A calculator calculates the difference between the internal timing information IRTS1 to IRTS4 and the transmission timing information RRTS1 to RRTS4 contained in a received cell, and a data reception clock producing portion adjusts the timing of the data reception clock C.sub.RU so that the difference is zero and outputs the adjusted timing. An ATM cell decomposing portion outputs the user data D.sub.RU in synchronism with the data reception clock C.sub.RU which is input from the data reception clock producing portion.
摘要翻译：内部定时信息产生部分通过使用网络时钟CN和数据接收时钟CRU，产生作为数据接收时钟的定时信息的IRTS1至IRTS4。计算器计算内部定时信息IRTS1至IRTS4与包含在接收单元中的发送定时信息RRTS1至RRTS4之间的差异，并且数据接收时钟产生部分调整数据接收时钟CRU的定时，使得该差为零，输出调整时间。 ATM信元分解部分与从数据接收时钟产生部分输入的数据接收时钟CRU同步地输出用户数据DRU。

2. 发明授权

US5778001A Interface device 失效
标题翻译：网络接口设备
公开(公告)号：US5778001A
公开(公告)日：1998-07-07
申请号：US696355
申请日：1996-08-13
申请人： Mikio Nakayama , Tetsuo Tachibana , Youzou Iketani , Yuzo Okuyama , Satoshi Makuma
发明人： Mikio Nakayama , Tetsuo Tachibana , Youzou Iketani , Yuzo Okuyama , Satoshi Makuma
IPC分类号： H04Q3/00 , H04J3/06 , H04L12/70 , H04L12/951 , H04Q11/04 , H04L12/56
CPC分类号： H04J3/0632 , H04Q11/0478 , H04L2012/5615 , H04L2012/5616 , H04L2012/5652 , H04L2012/5654 , H04L2012/5674
摘要： An internal timing information producing portion produces internal timing information IRTS1 to IRTS4 which is the timing information on a data reception clock by using a network clock C.sub.N and the data reception clock C.sub.RU. A calculator calculates the difference between the internal timing information IRTS1 to IRTS4 and the transmission timing information RRTS1 to RRTS4 contained in a received cell, and a data reception clock producing portion adjusts the timing of the data reception clock C.sub.RU so that the difference is zero and outputs the adjusted timing. An ATM cell decomposing portion outputs the user data D.sub.RU in synchronism with the data reception clock C.sub.RU which is input from the data reception clock producing portion.
摘要翻译：内部定时信息产生部分通过使用网络时钟CN和数据接收时钟CRU，产生作为数据接收时钟的定时信息的IRTS1至IRTS4。计算器计算内部定时信息IRTS1至IRTS4与包含在接收单元中的发送定时信息RRTS1至RRTS4之间的差异，并且数据接收时钟产生部分调整数据接收时钟CRU的定时，使得该差为零，输出调整时间。 ATM信元分解部分与从数据接收时钟产生部分输入的数据接收时钟CRU同步地输出用户数据DRU。

3. 发明授权

US06333932B1 Connectionless communications system, its test method, and intra-station control system 失效
标题翻译：无连接通信系统，其测试方法和站内控制系统
公开(公告)号：US06333932B1
公开(公告)日：2001-12-25
申请号：US08518110
申请日：1995-08-21
申请人： Yasusi Kobayasi , Yoshihiro Watanabe , Hiroshi Nishida , Masami Murayama , Naoyuki Izawa , Yasuhiro Aso , Yoshihiro Uchida , Hiromi Yamanaka , Jin Abe , Yoshihisa Tsuruta , Yoshiharu Kato , Satoshi Kakuma , Shiro Uriu , Noriko Samejima , Eiji Ishioka , Shigeru Sekine , Yoshiyuki Karakawa , Atsushi Kagawa , Mikio Nakayama , Miyuki Kawataka , Satoshi Esaka , Nobuyuki Tsutsui , Fumio Hirase , Atsuko Suzuki , Shouji Kohira , Kenichi Okabe , Takashi Hatano , Yasuhiro Nishikawa , Jun Itoh , Shinichi Araya
发明人： Yasusi Kobayasi , Yoshihiro Watanabe , Hiroshi Nishida , Masami Murayama , Naoyuki Izawa , Yasuhiro Aso , Yoshihiro Uchida , Hiromi Yamanaka , Jin Abe , Yoshihisa Tsuruta , Yoshiharu Kato , Satoshi Kakuma , Shiro Uriu , Noriko Samejima , Eiji Ishioka , Shigeru Sekine , Yoshiyuki Karakawa , Atsushi Kagawa , Mikio Nakayama , Miyuki Kawataka , Satoshi Esaka , Nobuyuki Tsutsui , Fumio Hirase , Atsuko Suzuki , Shouji Kohira , Kenichi Okabe , Takashi Hatano , Yasuhiro Nishikawa , Jun Itoh , Shinichi Araya
IPC分类号： H04Q1104
CPC分类号： H04L5/16 , H04L2012/5628 , H04L2012/5645 , H04L2012/5652 , H04Q11/0478
摘要： The quality and performance of the connectionless communications system are improved. When a BOM is received, the destination address DA of the L3-PDU stored in the payload of the BOM is retrieved, and the tag information is obtained from the DA (S11). The output message identifier MID is reserved (S12), and the tag information and output MID are assigned to the BOM (S13). Then, the tag information and output MID are written to the table. When a COM is received, the tag information and output MID are retrieved using the MID of the COM as a key, and the information is provided for the COM (S31 and S32). When an EOM is received, the tag information and output MID are retrieved using the MID of the EOM as a key, and the information is provided for the EOM (S41 and S42). Then, the output MID is released (S43).
摘要翻译：无连接通信系统的质量和性能得到提高。当接收到BOM时，检索存储在BOM的有效载荷中的L3-PDU的目的地地址DA，并从DA获得标签信息（S11）。输出消息标识符MID被保留（S12），标签信息和输出MID被分配给BOM（S13）。然后，将标签信息和输出MID写入表中。当接收到COM时，使用COM的MID作为密钥检索标签信息和输出MID，并为COM提供信息（S31和S32）。当接收到EOM时，使用EOM的MID作为密钥检索标签信息和输出MID，并且为EOM提供信息（S41和S42）。然后，释放输出MID（S43）。

4. 发明授权

US07551612B2 Intra-station control system for connectionless communications system 失效
标题翻译：无连接通信系统的站内控制系统
公开(公告)号：US07551612B2
公开(公告)日：2009-06-23
申请号：US09277213
申请日：1999-03-26
申请人： Yasusi Kobayashi , Yoshihiro Watanabe , Hiroshi Nishida , Masami Murayama , Naoyuki Izawa , Yasuhiro Aso , Yoshihiro Uchida , Hiromi Yamanaka , Jin Abe , Yoshihisa Tsuruta , Yoshiharu Kato , Satoshi Kakuma , Shiro Uriu , Noriko Samejima , Eiji Ishioka , Shigeru Sekine , Yoshiyuki Karakawa , Atsushi Kagawa , Mikio Nakayama , Miyuki Kawataka , Satoshi Esaka , Nobuyuki Tsutsui , Fumio Hirase , Atsuko Suzuki , Shouji Kohira , Kenichi Okabe , Takashi Hatano , Yasuhiro Nishikawa , Jun Itoh , Shinichi Araya
发明人： Yasusi Kobayashi , Yoshihiro Watanabe , Hiroshi Nishida , Masami Murayama , Naoyuki Izawa , Yasuhiro Aso , Yoshihiro Uchida , Hiromi Yamanaka , Jin Abe , Yoshihisa Tsuruta , Yoshiharu Kato , Satoshi Kakuma , Shiro Uriu , Noriko Samejima , Eiji Ishioka , Shigeru Sekine , Yoshiyuki Karakawa , Atsushi Kagawa , Mikio Nakayama , Miyuki Kawataka , Satoshi Esaka , Nobuyuki Tsutsui , Fumio Hirase , Atsuko Suzuki , Shouji Kohira , Kenichi Okabe , Takashi Hatano , Yasuhiro Nishikawa , Jun Itoh , Shinichi Araya
IPC分类号： H04L12/66
CPC分类号： H04L5/16 , H04L2012/5628 , H04L2012/5645 , H04L2012/5652 , H04Q11/0478
摘要： A switch station including an ATM switch; a memory storing control data for operations of the switch station; an intra-station device, accommodating a subscriber line, performing communication operation on subscriber ATM cell; a control processor generating control information in link access protocol (LAP) format; and an interface unit converting LAP control information into ATM cell to the intra-station device through the ATM switch, wherein the control information is communicated according to LAP, the intra-station device receives the control information and transmits a direct memory access request to obtain control data stored in the memory, the interface unit obtains and converts the data format of the control data into ATM cell to transmit to the intra-station device through the switch, and the intra-station device performs the communication operation on the subscriber ATM cell based on the control data received through the switch.
摘要翻译：包括ATM交换机的交换台; 存储用于所述开关站的操作的控制数据的存储器; 站内设备，容纳用户线路，对用户ATM信元进行通信操作; 控制处理器生成链路接入协议（LAP）格式的控制信息; 以及接口单元，其通过ATM交换机将LAP控制信息转换为ATM信元到站内设备，其中根据LAP传送控制信息，站内设备接收控制信息并发送直接存储器访问请求以获得存储在存储器中的控制数据，接口单元获取控制数据的数据格式并将其转换成ATM信元，通过交换机发送到站内设备，并且站内设备对用户ATM信元进行通信操作基于通过交换机接收的控制数据。

5. 发明授权

US06026098A Line multiplexing system 失效
标题翻译：线路复用系统
公开(公告)号：US06026098A
公开(公告)日：2000-02-15
申请号：US931638
申请日：1997-09-16
申请人： Jyoei Kamoi , Tomoyuki Yamaguchi , Mikio Nakayama , Yuzo Okuyama
发明人： Jyoei Kamoi , Tomoyuki Yamaguchi , Mikio Nakayama , Yuzo Okuyama
IPC分类号： H04J3/04 , H04J3/24 , H04Q11/04 , H04L12/56
CPC分类号： H04L49/3081 , H04J3/247 , H04Q11/0478 , H04L2012/5672
摘要： A plurality of input lines are respectively connected to separate multiplexing units that are connected in cascade by cascading lines. Select signals are transferred in parallel with fixed length packets over the cascading lines. Each separate multiplexing unit is responsive to a select signal received from the cascading line to select one of fixed length packets received over the corresponding input line and the upstream cascading line and output it over the downstream cascading line. The most downstream separate multiplexing unit provides a multiplexed output of the input lines.
摘要翻译：多个输入线分别连接到通过级联线级联连接的分离复用单元。选择信号通过级联线路与固定长度的数据包并行传输。每个单独的复用单元响应于从级联线路接收的选择信号，以选择在相应输入线路和上游级联线路上接收的固定长度分组中的一个，并在下游级联线路上输出。最下游单独复用单元提供输入线的多路复用输出。

6. 发明授权

US5777985A Apparatus and method for absorbing an arrival time delay fluctuation of a fixed length packet, and ATM switching system 失效
标题翻译：用于吸收固定长度分组的到达时间延迟波动的装置和方法，以及ATM交换系统
公开(公告)号：US5777985A
公开(公告)日：1998-07-07
申请号：US514987
申请日：1995-08-14
申请人： Mikio Nakayama
发明人： Mikio Nakayama
IPC分类号： H04L7/00 , H04J3/06 , H04L7/08 , H04L12/70 , H04L12/885 , H04L12/951 , H04Q11/04 , H04J3/14
CPC分类号： H04Q11/0478 , H04J3/0632 , H04L2012/5649 , H04L2012/568
摘要： An apparatus for absorbing an arrival time delay of a fixed length packet, equipped with a first-in, first-out type memory, a fixed length packet writing unit for reading out information stored within fixed length packet and for writing into the first-in, first-out type memory, a first-cell detection unit for detecting the fixed length packet which is first received, a read-out timing generation unit for, in the case where the first-received fixed length packet has been detected with the first cell detection unit, generating read-out timing that shows read-out initiation following a prescribed time lapse, and a read-out unit for, in the case where read-out timing has been generated with the read-out timing generation unit, initiating the read-out of information stored within the first-in, first-out type memory.
摘要翻译：一种用于吸收固定长度分组的到达时间延迟的装置，其具有先入先出式存储器，固定长度分组写入单元，用于读出存储在固定长度分组内的信息并写入到先到先首先输出型存储器，用于检测首先接收的固定长度分组的第一单元检测单元，在第一接收固定长度分组被检测到的情况下，读出定时生成单元单元检测单元，产生在规定的时间流逝之后显示读出启动的读出定时，以及读出单元，用于在读出定时产生单元产生读出定时的情况下启动读出存储在先入先出的存储器中的信息。

7. 发明授权

US5063563A Communication terminal having means for controlling power transfer 失效
标题翻译：具有控制电力传输手段的通信终端
公开(公告)号：US5063563A
公开(公告)日：1991-11-05
申请号：US578358
申请日：1990-09-06
申请人： Koji Ikeda , Mikio Nakayama
发明人： Koji Ikeda , Mikio Nakayama
IPC分类号： H04M1/00 , H04M1/253 , H04M19/08 , H04Q11/04
CPC分类号： H04Q11/0471 , H04M19/08 , H04Q2213/08
摘要： A communication terminal is coupled to a communication network via transmitting and receiving signal lines and a switching system. The communication terminal includes a power input line coupled to the transmitting and receiving signal lines, a power sink for supplying power, a switch coupled between the power input line and the power sink, a hook switch coupled between the power input line and the power sink in parallel to the switch, a detection circuit coupled to the receiving signal line for detecting a signal on the receiving signal line, a state maintaining circuit coupled to the switch and the detection circuit for closing the switch and for maintaining the switch in a closed state by carrying out a state maintaining operation when a signal is detected by the detection circuit, and a prohibit circuit coupled to the detection circuit for prohibiting a signal detection of the detection circuit.
摘要翻译：通信终端经由发送和接收信号线（100,101）和交换系统耦合到通信网络。通信终端包括耦合到发射和接收信号线的电力输入线（117,219），用于供电的功率宿（118），耦合在所述电力输入线和所述功率宿之间的开关（SW），钩开关（HS1），与所述开关并联连接在所述电力输入线和所述功率吸收器之间;检测电路（1），耦合到所述接收信号线，用于检测所述接收信号线上的信号;状态维持电路（2）所述开关和所述检测电路用于关闭所述开关并且用于通过在所述检测电路检测到信号时执行状态保持操作来将所述开关保持在闭合状态;以及禁止电路（3），其耦合到所述检测电路禁止检测电路的信号检测。

8. 发明授权

US06873621B2 System for controlling AAL1 cell bandwidth 失效
标题翻译：控制AAL1单元带宽的系统
公开(公告)号：US06873621B2
公开(公告)日：2005-03-29
申请号：US09759176
申请日：2001-01-12
申请人： Jyoei Kamoi , Yoshihiro Uchida , Naoki Aihara , Mikio Nakayama , Kazuhito Yasue , Kazuhiko Kumagai
发明人： Jyoei Kamoi , Yoshihiro Uchida , Naoki Aihara , Mikio Nakayama , Kazuhito Yasue , Kazuhiko Kumagai
IPC分类号： H04L12/853 , H04L12/953 , H04Q11/04 , H04L12/28
CPC分类号： H04Q11/0478 , H04L2012/5647 , H04L2012/5654
摘要： A system for controlling a bandwidth when receiving and reassembling a consecutive data stream transferred while segmented by AAL1 format cells which enables correct determination of non-P and P formats and reassembly of cells even when error arises in multiple bits including the CSI bit of an AAL1 cell or when adding dummy cells and thereby enabling prevention of a gap in data in a frame, comprising, in a data reassembly unit which reassembles received cells, an 8-cell buffer for storing 8 cells of a cycle of a sequence count (SC) of 0 to 7 and sending the cells out to a later stage after a check unit of a sequence number (SN) field confirms normalcy of the cells and a control unit for control so that the number of P format cells stored in the 8-cell buffer becomes 1 cell when 8 cells are stored in the 8-cell buffer.
摘要翻译：一种用于在接收和重新组合由AAL1格式单元分段传送的连续数据流时控制带宽的系统，其能够正确确定非P和P格式并且即使在包括AAL1的CSI位的多个比特中出现错误时也可重新组合或者当添加虚拟小区时，从而能够防止帧中数据的间隙，包括在重新组合接收到的小区的数据重新组合单元中存储用于存储序列计数（SC）的循环的8个单元的8个单元缓冲器， 0到7，并且在序列号（SN）字段的检查单元确认单元的正常状态和用于控制的控制单元之后将单元发送到稍后阶段，使得存储在8单元中的P格式单元的数量当8个单元格存储在8个单元缓冲区中时，缓冲区变为1个单元格。

9. 发明授权

US5914954A Buffer control system 失效
标题翻译：缓冲控制系统
公开(公告)号：US5914954A
公开(公告)日：1999-06-22
申请号：US715010
申请日：1996-08-17
申请人： Mikio Nakayama
发明人： Mikio Nakayama
IPC分类号： H04L7/00 , H04L12/70 , H04L12/801 , H04L12/885 , H04L12/911 , H04Q3/00 , H04Q11/04 , H04J3/24
CPC分类号： H04L49/108 , H04Q11/0478 , H04L2012/5647 , H04L2012/5649 , H04L2012/565
摘要： In cell transfer in which cells are sent at uniform intervals, in a case in which 18 cells have been lost between cell A (SN=2) and cell B (SN=5), every time 8 times the expectation value T of the cell arrival interval elapses after the arrival of cell A a dummy cell having the same sequence number as cell A (SN=2) is written into the cell FIFO section. Cells or dummy cells are stored in the cell FIFO section in the order SN=2, 2, 2, 5. When cells or dummy cells are read out of the cell FIFO section in order, if the sequence number SN=2 appears twice in a row, dummy data are created corresponding to the cells SN=3, 4, 5, 6, 7, 0, 1; if the sequence number SN=2 is followed by SN=5, then dummy data are created corresponding to SN=3 and 4.
摘要翻译：在细胞以均匀间隔发送的细胞转移中，在细胞A（SN = 2）和细胞B（SN = 5）之间已经丢失18个细胞的情况下，每次细胞的期望值T的8倍在小区A到达之后，到达间隔经过与小区A（SN = 2）具有相同序列号的虚拟小区被写入小区FIFO部分。单元格或虚拟单元格按SN = 2,2,2,5的顺序存储在单元格FIFO单元中。当单元格或单元格FIFO单元按顺序读出时，如果序列号SN = 2出现两次，对应于单元SN = 3,4,5,6,7,10,1而创建一行虚拟数据; 如果序列号SN = 2后跟SN = 5，则创建对应于SN = 3和4的伪数据。

10. 发明授权

US5349679A Communication control unit for selecting a control mode of data communication and selectively bypassing an interprocessor interface 失效
标题翻译：通信控制单元，用于选择数据通信的控制模式并选择性地绕过处理器间接口
公开(公告)号：US5349679A
公开(公告)日：1994-09-20
申请号：US750827
申请日：1991-08-27
申请人： Mikio Nakayama
发明人： Mikio Nakayama
IPC分类号： H04L29/06 , G06F13/38 , H04L29/10 , G06F3/00
CPC分类号： G06F13/385
摘要： A communication control unit includes a central processing unit, a peripheral circuit part for operating the central processing unit, a line interface part for carrying out a call control, a data communication part for controlling a data terminal, a line system bus which couples the central processing unit, the peripheral circuit part and the line interface part, a data system bus which is coupled to the data communication part, an interprocessor interface part which is coupled to the data communication part, and a bus selector part which is coupled to the line system bus, the data communication part and the interprocessor interface part. The bus selector part bypasses the interprocessor interface part and couples the line system bus to the data communication part in a single mode in which the central processing unit controls both the line interface part and the data communication part, and said bus selector part couples the line system bus to the data communication part via the interprocessor interface part in a multi mode in which the central processing unit controls the line interface part and another central processing unit controls the data communication part via the data system bus.
摘要翻译：通信控制单元包括中央处理单元，用于操作中央处理单元的外围电路部分，用于执行呼叫控制的线路接口部分，用于控制数据终端的数据通信部分，连接中央处理单元的线路总线处理单元，外围电路部分和线路接口部分，耦合到数据通信部分的数据系统总线，耦合到数据通信部分的处理器间接口部分和耦合到线路的总线选择器部分系统总线，数据通信部分和处理器间接口部分。总线选择器部分绕过处理器接口部分，并且以单个模式将线路系统总线耦合到数据通信部分，其中中央处理单元控制线路接口部分和数据通信部分，并且所述总线选择器部分耦合线路系统总线经由处理器接口部分以多模式传送到数据通信部分，其中中央处理单元控制线路接口部分，另一个中央处理单元经由数据系统总线控制数据通信部分。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式