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1. 发明申请

US20080145958A1 MONITORING OF ELECTROSTATIC DISCHARGE (ESD) EVENTS DURING SEMICONDUCTOR MANUFACTURE USING ESD SENSITIVE RESISTORS 审中-公开
标题翻译：使用ESD敏感电阻监测半导体制造过程中的静电放电（ESD）事件
公开(公告)号：US20080145958A1
公开(公告)日：2008-06-19
申请号：US11611258
申请日：2006-12-15
申请人： Michel J. Abou-Khalil , Robert J. Gauthier , Tom C. Lee , Junjun Li , Souvick Mitra , Christopher Stephen Putnam
发明人： Michel J. Abou-Khalil , Robert J. Gauthier , Tom C. Lee , Junjun Li , Souvick Mitra , Christopher Stephen Putnam
IPC分类号： H01L21/66 , H01L23/58
CPC分类号： H01L22/14 , H01L22/20 , H01L23/60 , H01L2924/0002 , H01L2924/00
摘要： A monitor semiconductor chip that incorporates ESD sensitive resistors is subjected to the same steps in a semiconductor manufacturing process to which functional semiconductor chips are subjected. The ESD sensitive resistors are configured to experience non-volatile changes in resistance in response to ESD events, such that the resistors retain the changes in resistance after dissipation of the ESD events have occurred. As a result, the occurrence of an ESD event, and in some instances, the magnitude of an ESD event, can be detected by monitoring the resistance of the ESD sensitive resistors after one or more steps in a semiconductor manufacturing process.
摘要翻译：在ESD功能半导体芯片受到的半导体制造工序中，具有ESD敏感电阻的监视器半导体芯片进行相同的工序。 ESD敏感电阻被配置为响应于ESD事件而经历电阻的非易失性变化，使得电阻器在ESD事件消散之后保持电阻的变化。结果，通过在半导体制造过程中的一个或多个步骤之后监视ESD敏感电阻器的电阻，可以检测到ESD事件的发生，并且在一些情况下，ESD事件的幅度。

2. 发明申请

US20080145993A1 ELECTROSTATIC DISCHARGE PROTECTION DEVICE AND METHOD OF FABRICATING SAME 审中-公开
标题翻译：静电放电保护装置及其制造方法
公开(公告)号：US20080145993A1
公开(公告)日：2008-06-19
申请号：US12036319
申请日：2008-02-25
申请人： Robert J. Gauthier , Junjun Li , Souvick Mitra , Mahmoud A. Mousa , Christopher Stephen Putnam
发明人： Robert J. Gauthier , Junjun Li , Souvick Mitra , Mahmoud A. Mousa , Christopher Stephen Putnam
IPC分类号： H01L21/8228
CPC分类号： H01L29/7436 , H01L21/84 , H01L27/0262 , H01L27/1203
摘要： A silicon control rectifier, a method of making the silicon control rectifier and the use of the silicon control rectifier as an electrostatic discharge protection device of an integrated circuit. The silicon control rectifier includes a silicon body formed in a silicon layer in direct physical contact with a buried oxide layer of a silicon-on-insulator substrate, a top surface of the silicon layer defining a horizontal plane; and an anode of the silicon control rectifier formed in a first region of the silicon body and a cathode of the silicon control rectifier formed in an opposite second region of the silicon body, wherein a path of current flow between the anode and the cathode is only in a single horizontal direction parallel to the horizontal plane.
摘要翻译：硅控制整流器，制造硅控制整流器的方法和使用硅控制整流器作为集成电路的静电放电保护器件。硅控制整流器包括形成在硅层中的硅体，其与绝缘体上硅衬底的掩埋氧化物层直接物理接触，硅层的顶表面限定水平面; 并且形成在硅体的第一区域中的硅控制整流器的阳极和形成在硅体的相对的第二区域中的硅控制整流器的阴极，其中阳极和阴极之间的电流路径仅为在平行于水平面的单个水平方向上。

3. 发明申请

US20080224172A1 ELECTROSTATIC DISCHARGE PROTECTION DEVICE AND METHOD OF FABRICATING SAME 有权
标题翻译：静电放电保护装置及其制造方法
公开(公告)号：US20080224172A1
公开(公告)日：2008-09-18
申请号：US12127946
申请日：2008-05-28
申请人： Robert J. Gauthier , Junjun Li , Souvick Mitra , Mahmoud A. Mousa , Christopher Stephen Putnam
发明人： Robert J. Gauthier , Junjun Li , Souvick Mitra , Mahmoud A. Mousa , Christopher Stephen Putnam
IPC分类号： H01L29/74
CPC分类号： H01L29/7436 , H01L21/84 , H01L27/0262 , H01L27/1203
摘要： A silicon control rectifier and an electrostatic discharge protection device of an integrated circuit including the silicon control rectifier. The silicon control rectifier includes a silicon body formed in a silicon layer in direct physical contact with a buried oxide layer of a silicon-on-insulator substrate, a top surface of the silicon layer defining a horizontal plane; and an anode of the silicon control rectifier formed in a first region of the silicon body and a cathode of the silicon control rectifier formed in an opposite second region of the silicon body, wherein a path of current flow between the anode and the cathode is only in a single horizontal direction parallel to the horizontal plane.
摘要翻译：包括硅控制整流器的集成电路的硅控制整流器和静电放电保护装置。硅控制整流器包括形成在硅层中的硅体，其与绝缘体上硅衬底的掩埋氧化物层直接物理接触，硅层的顶表面限定水平面; 并且形成在硅体的第一区域中的硅控制整流器的阳极和形成在硅体的相对的第二区域中的硅控制整流器的阴极，其中阳极和阴极之间的电流路径仅为在平行于水平面的单个水平方向上。

4. 发明申请

US20070285853A1 RC-Triggered Power Clamp Suppressing Negative Mode Electrostatic Discharge Stress 失效
标题翻译： RC触发电源钳位抑制负模式静电放电应力
公开(公告)号：US20070285853A1
公开(公告)日：2007-12-13
申请号：US11422608
申请日：2006-06-07
申请人： Robert J. Gauthier , Dimitrios K. Kontos , Junjun Li , Souvick Mitra , Christopher S. Putnam
发明人： Robert J. Gauthier , Dimitrios K. Kontos , Junjun Li , Souvick Mitra , Christopher S. Putnam
IPC分类号： H02H9/00
CPC分类号： H02H9/046
摘要： An electrostatic discharge (ESD) power clamp circuit including a RC-delay element coupled to a plurality of serialized inverter elements with a power clamp element and an ESD-triggered keeper device coupled to the plurality of inverters. During negative mode ESD events, the ESD-triggered keeper device is activated and assists the power clamp element to pull up and strongly conduct current to protect the circuit. Additionally, a method of ESD protection in a circuit is provided. The method includes coupling a RC-delay element to an input of a plurality of serialized inverter elements, coupling an output of the plurality of serialized inverters with an ESD-triggered keeper device and a power clamp element, triggering the ESD-triggered keeper device to turn on during negative ESD events and conducting current by the power clamp element with assistance of the ESD-triggered keeper device to protect the circuit as a result of negative ESD events.
摘要翻译：一种静电放电（ESD）功率钳位电路，其包括耦合到多个串联反相器元件的RC延迟元件，其具有耦合到所述多个逆变器的功率钳位元件和ESD触发的保持器装置。在负模式ESD事件期间，ESD触发的保护装置被激活，并且帮助电源钳位元件上拉并强烈地传导电流以保护电路。另外，提供了电路中ESD保护的方法。该方法包括将RC延迟元件耦合到多个串联反相器元件的输入端，将多个串联反相器的输出与ESD触发的保持器装置和功率钳位元件耦合，将ESD触发的保持器装置触发在ESD ESD事件期间接通电源，并通过ESD触发的保护装置的辅助，通过电源钳位元件传导电流，以保护电路由于负ESD事件。

5. 发明申请

US20080232012A1 METHOD FOR IMPROVED TRIGGERING AND OSCILLATION SUPRESSION OF ESD CLAMPING DEVICES 失效
标题翻译：用于改善ESD钳位装置的触发和振荡抑制的方法
公开(公告)号：US20080232012A1
公开(公告)日：2008-09-25
申请号：US12133424
申请日：2008-06-05
申请人： Albert M. Chu , Robert J. Gauthier , Junjun Li , Thomas W. Wyckoff
发明人： Albert M. Chu , Robert J. Gauthier , Junjun Li , Thomas W. Wyckoff
IPC分类号： H02H9/00
CPC分类号： H01L27/0266
摘要： An apparatus for protecting an integrated circuit from electrostatic discharge (ESD) includes an RC trigger device configured between a pair of power rails, a first control path coupled to the RC trigger device, and a second control path coupled to the RC trigger device. A power clamp is configured between the power rails for discharging current from an ESD event, the power clamp having an input coupled to outputs of the first and second control paths, the power clamp independently controllable by the first and second control paths. The first and second control paths are further configured to prevent the power clamp from reactivating following an initial deactivation of the power clamp.
摘要翻译：用于保护集成电路免受静电放电（ESD）的装置包括RC触发装置，其配置在耦合到RC触发装置的一对电源轨，第一控制路径和耦合到RC触发装置的第二控制路径之间。功率钳被配置在用于从ESD事件放电的电源轨之间，功率钳具有耦合到第一和第二控制路径的输出的输入，功率钳由第一和第二控制路径独立地控制。第一和第二控制路径还被配置为防止在电源钳的初始去激活之后电源钳位被重新激活。

6. 发明申请

US20080001620A1 METHOD AND APPARATUS FOR IMPEDANCE MATCHING IN TRANSMISSION CIRCUITS USING TANTALUM NITRIDE RESISTOR DEVICES 有权
标题翻译：使用氮化钛电阻器件在传输电路中阻抗匹配的方法和装置
公开(公告)号：US20080001620A1
公开(公告)日：2008-01-03
申请号：US11427798
申请日：2006-06-30
申请人： Fen Chen , Kai D. Feng , Robert J. Gauthier , Tom C. Lee
发明人： Fen Chen , Kai D. Feng , Robert J. Gauthier , Tom C. Lee
IPC分类号： H03K19/003
CPC分类号： H03K19/018571
摘要： A method for trimming impedance matching devices in high-speed circuits includes determining an electrical parameter associated with a first tantalum nitride (TaN) resistor used as an impedance matching device in the circuit under test, and comparing the determined electrical parameter associated with the first TaN resistor to a desired design value of the electrical parameter. The resistance value of the first TaN resistor is altered by application of a trimming voltage thereto, wherein the trimming voltage is based on a voltage-resistance characteristic curve of the first TaN resistor. It is then determined whether the altered resistance value of the first TaN resistor causes the electrical parameter to equal the desired design value thereof, and the altering of the resistance value of the first TaN resistor by application of a trimming voltage is repeated until the electrical parameter equals the desired design value thereof.
摘要翻译：一种用于微调高速电路中的阻抗匹配装置的方法包括：确定与在被测电路中用作阻抗匹配装置的第一氮化钽（TaN）电阻相关联的电参数，并将确定的与第一TaN相关的电参数进行比较电阻到所需的电参数设计值。通过施加微调电压来改变第一TaN电阻器的电阻值，其中微调电压基于第一TaN电阻器的耐电压特性曲线。然后确定第一TaN电阻器的改变的电阻值是否使电参数等于其期望的设计值，并且重复通过施加微调电压来改变第一TaN电阻器的电阻值，直到电参数等于其期望的设计值。

7. 发明授权

US08110483B2 Forming an extremely thin semiconductor-on-insulator (ETSOI) layer 有权
标题翻译：形成极薄的绝缘体上半导体（ETSOI）层
公开(公告)号：US08110483B2
公开(公告)日：2012-02-07
申请号：US12603737
申请日：2009-10-22
申请人： Wagdi W. Abadeer , Lilian Kamal, legal representative , Kiran V. Chatty , Jason E. Cummings , Toshiharu Furukawa , Robert J. Gauthier , Jed H. Rankin, Jr. , Robert R. Robison , William R. Tonti
发明人： Wagdi W. Abadeer , Kiran V. Chatty , Jason E. Cummings , Toshiharu Furukawa , Robert J. Gauthier , Jed H. Rankin, Jr. , Robert R. Robison , William R. Tonti
IPC分类号： H01L21/762
CPC分类号： H01L29/0649 , H01L21/76264 , H01L21/84 , H01L27/1203
摘要： Solutions for forming an extremely thin semiconductor-on-insulator (ETSOI) layer are disclosed. In one embodiment, a method includes providing a wafer including a plurality of semiconductor-on-insulator (SOI) layer regions separated by at least one shallow trench isolation (STI); amorphizing the plurality of SOI layer regions by implanting the plurality of SOI layer regions with an implant species; and removing a portion of the amorphized SOI layer region to form at least one recess in the amorphized SOI layer region.
摘要翻译：公开了用于形成非常薄的绝缘体上半导体（ETSOI）层的解决方案。在一个实施例中，一种方法包括提供包括通过至少一个浅沟槽隔离（STI）分离的多个绝缘体上半导体（SOI）层区域的晶片; 通过用植入物种植入多个SOI层区域来使多个SOI层区域非晶化; 以及去除所述非晶化SOI层区域的一部分以在所述非晶化SOI层区域中形成至少一个凹部。

8. 发明授权

US4976683A Peritoneal dialysis method 失效
标题翻译：腹膜透析法
公开(公告)号：US4976683A
公开(公告)日：1990-12-11
申请号：US220779
申请日：1988-07-18
申请人： Robert J. Gauthier , Robert S. Levinson
发明人： Robert J. Gauthier , Robert S. Levinson
IPC分类号： A61M1/28
CPC分类号： A61M1/28 , A61M1/287
摘要： This invention relates to an improved method for conducting peritoneal dialysis with a decreased total volume of dialysis fluid used and increased efficacy parameters such as ultrafiltration rate, urea clearance rate and dialysate volume as compared to conventional techniques. In the method of this invention, a fluid communication through the peritoneal membrane into the peritoneal cavity of a patient in need of peritoneal dialysis treatment is established. An initial volume of an aqueous peritoneal dialysis composition containing an osmotic agent is instilled into the peritoneal cavity through the fluid communication. The dialysis composition contains an amount of dissolved osmotic agent (i) that is insufficient to adequately dialyze the patient during a predetermined time period of dialysis treatment, but (ii) that is present at an osmolarity that is greater than the osmolarity of the body fluids in contact with the membrane, such that an osmolarity gradient is created across the membrane between the composition and the body fluids. A flux of water and solute enters the composition from the body fluids by means of that gradient.A further amount of dissolved osmotic agent is released into the instilled dialysis composition to form a modified dialysis composition. That further osmotic agent is released in an amount sufficient to maintain a substantially constant osmolarity gradient between the modified dialysis composition and the body fluids such that the water and solute flux continues to enter into the modified dialysis composition during the predetermined dialysis time period. The modified dialysis composition is substantially removed from the peritoneal cavity at the end of the treatment time period.
摘要翻译：本发明涉及一种改进的腹膜透析方法，与常规技术相比，使用的透析液的总体积减少，并且提高了功效参数，例如超滤速率，尿素清除率和透析液体积。在本发明的方法中，建立了通过腹膜进入需要腹膜透析治疗的患者的腹腔的液体连通。通过流体连通将含有渗透剂的含水性腹膜透析组合物的初始体积滴入腹膜腔。透析组合物含有一定量的溶解渗透剂（i），其不足以在透析治疗的预定时间段期间充分透析患者，但（ii）存在的渗透压大于体液的渗透压与膜接触，使得跨组合物和体液之间的膜产生渗透压梯度。水和溶质的通量通过该梯度从体液进入组合物。将另外量的溶解的渗透剂释放到滴入浓缩组合物中以形成改性透析组合物。该释放出的进一步的渗透剂量足以在修饰的透析组合物和体液之间保持基本恒定的渗透压梯度，使得水和溶质通量在预定的透析时间期间继续进入修饰的透析组合物。在治疗时间段结束时，改良的透析组合物基本上从腹膜腔中除去。

9. 发明授权

US07709926B2 Device structures for active devices fabricated using a semiconductor-on-insulator substrate and design structures for a radiofrequency integrated circuit 失效
标题翻译：使用绝缘体上半导体衬底制造的有源器件的器件结构和用于射频集成电路的设计结构
公开(公告)号：US07709926B2
公开(公告)日：2010-05-04
申请号：US12108924
申请日：2008-04-24
申请人： Wagdi W. Abadeer , Kiran V. Chatty , Robert J. Gauthier , Jed H. Rankin , Robert R. Robison , William R. Tonti
发明人： Wagdi W. Abadeer , Kiran V. Chatty , Robert J. Gauthier , Jed H. Rankin , Robert R. Robison , William R. Tonti
IPC分类号： H01L29/06
CPC分类号： H01L29/7436 , H01L21/76229 , H01L29/0649 , H01L29/6625 , H01L29/66265 , H01L29/7317 , H01L29/735
摘要： Device structure for active devices fabricated in a semiconductor-on-insulator (SOI) substrate and design structures for a radiofrequency integrated circuit. The device structure includes a first isolation region in the semiconductor layer that extends from a top surface of a semiconductor layer to a first depth, a second isolation region in the semiconductor layer that extends from the top surface of the semiconductor layer to a second depth greater than the first depth, and a first doped region in the semiconductor layer. The first doped region is disposed vertically between the first isolation region and an insulating layer disposed between the semiconductor layer and a handle wafer of the SOI substrate. The device structure may be included in a design structure embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit.
摘要翻译：用于在绝缘体上半导体（SOI）衬底中制造的有源器件的器件结构和用于射频集成电路的设计结构。器件结构包括半导体层中从半导体层的顶表面延伸到第一深度的第一隔离区域，半导体层中的从半导体层的顶表面延伸到第二深度更大的第二隔离区域比第一深度，以及半导体层中的第一掺杂区域。第一掺杂区域垂直地设置在第一隔离区域和设置在SOI衬底的半导体层和处理晶片之间的绝缘层之间。装置结构可以包括在体现在用于设计，制造或测试集成电路的机器可读介质中的设计结构中。

10. 发明授权

US06411480B1 Substrate pumped ESD network with trench structure 失效
标题翻译：衬底泵浦ESD网络，具有沟槽结构
公开(公告)号：US06411480B1
公开(公告)日：2002-06-25
申请号：US09259541
申请日：1999-03-01
申请人： Robert J. Gauthier , Steven H. Voldman
发明人： Robert J. Gauthier , Steven H. Voldman
IPC分类号： H02H900
CPC分类号： H01L27/0259
摘要： An ESD protection circuit which may be implemented in thin epitaxial substrate surfaces. The protection device includes a MOSFET transistor or bipolar transistor implemented in a trench isolated area of the substrate. The isolation of the MOSFET transistor permits the substrate region to be pumped with an electric charge which reduces the trigger/snapback voltage and MOSFET threshold voltage for the device. A trigger current supplies the pumping current to the isolated substrate area when a transient voltage is applied thus lowering the trigger/snapback voltage of the MOSFET transistor in the presence of a transient voltage.
摘要翻译：可以在薄的外延衬底表面中实现的ESD保护电路。保护装置包括实现在衬底的沟槽隔离区域中的MOSFET晶体管或双极晶体管。 MOSFET晶体管的隔离允许以电荷泵浦衬底区域，这减少了器件的触发/回跳电压和MOSFET阈值电压。当施加瞬态电压时，触发电流将泵浦电流提供给隔离衬底区域，从而在存在瞬态电压的情况下降低MOSFET晶体管的触发/回跳电压。

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