专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06512296B1 Semiconductor structure having heterogenous silicide regions having titanium and molybdenum 失效
标题翻译：具有异质硅化物区域的具有钛和钼的半导体结构
公开(公告)号：US06512296B1
公开(公告)日：2003-01-28
申请号：US09636325
申请日：2000-08-10
申请人： Robert J. Gauthier, Jr. , Randy W. Mann , Steven H. Voldman
发明人： Robert J. Gauthier, Jr. , Randy W. Mann , Steven H. Voldman
IPC分类号： H01L2348
CPC分类号： H01L29/4933 , H01L21/28052 , H01L21/28518 , H01L21/28568 , H01L21/823418 , H01L21/823443 , H01L29/456
摘要： A process for forming heterogeneous silicide structures on a semiconductor substrate (10) includes implanting molybdenum ions into selective areas of the semiconductor substrate (10) to form molybdenum regions (73, 74, 75, 76). Titanium is then deposited over the semiconductor substrate (10). The semiconductor substrate (10) is annealed at a temperature between approximately 600° C. and approximately 700° C. During the annealing process, the titanium deposited in areas outside the molybdenum regions (73, 74, 75, 76) interacts with silicon on the substrate to form titanium silicide in a high resistivity C49 crystal phase. The titanium deposited in areas within the molybdenum regions (73, 74, 75, 76) interacts with silicon to form titanium silicide in a low resistivity C54 crystal phase because the presence of molybdenum ions in silicon lowers the energy barrier for crystal phase transformation between the C49 phase and the C54 phase.
摘要翻译：在半导体衬底（10）上形成异质硅化物结构的方法包括将钼离子注入到半导体衬底（10）的选择区域中以形成钼区（73,74,75,76）。然后将钛沉积在半导体衬底（10）上。半导体衬底（10）在大约600℃和大约700℃之间的温度下退火。在退火过程中，沉积在钼区域（73,74,75,76）之外的区域中的钛与硅该基板在高电阻率C49晶相中形成硅化钛。在钼区域（73,74,75,76）中的区域中沉积的钛与硅相互作用以在低电阻率C54晶体相中形成硅化钛，因为硅中的钼离子的存在降低了能量势垒以进行晶体相变 C49相和C54相。

2. 发明授权

US06288426B1 Thermal conductivity enhanced semiconductor structures and fabrication processes 有权
标题翻译：热导率增强的半导体结构和制造工艺
公开(公告)号：US06288426B1
公开(公告)日：2001-09-11
申请号：US09514106
申请日：2000-02-28
申请人： Robert J. Gauthier, Jr. , Dominic J. Schepis , William R. Tonti , Steven H. Voldman
发明人： Robert J. Gauthier, Jr. , Dominic J. Schepis , William R. Tonti , Steven H. Voldman
IPC分类号： H01L2900
CPC分类号： H01L29/78648 , H01L21/76264 , H01L21/76286 , H01L21/763 , H01L23/3677 , H01L27/1203 , H01L2924/0002 , H01L2924/00
摘要： Silicon is formed at selected locations on a substrate during fabrication of selected electronic components. A dielectric separation region is formed within the top silicon layer, and filled with a thermally conductive material. A liner material may be optionally deposited prior to depositing the thermally conductive material. In a second embodiment, a horizontal layer of thermally conductive material is also deposited in an oxide layer or bulk silicon layer below the top layer of silicon.
摘要翻译：在选择的电子部件的制造期间，在基板上的选定位置处形成硅。介电分离区形成在顶层硅层内，并填充有导热材料。衬里材料可以在沉积导热材料之前任选地沉积。在第二实施例中，水平导热材料层也沉积在硅顶层之下的氧化物层或体硅层中。

3. 发明授权

US06232163B1 Method of forming a semiconductor diode with depleted polysilicon gate structure 有权
标题翻译：形成具有耗尽的多晶硅栅结构的半导体二极管的方法
公开(公告)号：US06232163B1
公开(公告)日：2001-05-15
申请号：US09362549
申请日：1999-07-28
申请人： Steven H. Voldman , Robert J. Gauthier, Jr. , Jeffrey S. Brown
发明人： Steven H. Voldman , Robert J. Gauthier, Jr. , Jeffrey S. Brown
IPC分类号： H01L218238
CPC分类号： H01L27/0811 , H01L29/7391 , H01L2924/0002 , H01L2924/00
摘要： A high voltage tolerant diode structure for mixed-voltage, and mixed signal and analog/digital applications. The preferred silicon diode includes a polysilicon gate structure on at least one dielectric film layer on a semiconductor (silicon) layer or body. A well or an implanted area is formed in a bulk semiconductor substrate or in a surface silicon layer on an SOI wafer. Voltage applied to the polysilicon gate film, electrically depletes it, reducing voltage stress across the dielectric film. An intrinsic polysilicon film may be counter-doped, implanted with a low doped implantation, implanted with a low doped source/drain implant, or with a low doped MOSFET LDD or extension implant. Alternatively, a block mask may be formed over the gate structure when defining the depleted-polysilicon gate silicon diode to form low series resistance diode implants, preventing over-doping the film. Optionally, a hybrid photoresist method may be used to form higher doped edge implants in the silicon to reduce diode series resistance without a block mask.
摘要翻译：用于混合电压，混合信号和模拟/数字应用的高耐压二极管结构。优选的硅二极管包括在半导体（硅）层或主体上的至少一个电介质膜层上的多晶硅栅极结构。阱体或植入区域形成在SOI半导体衬底或SOI晶片的表面硅层中。施加到多晶硅栅极膜的电压，电耗电，降低电介质膜两端的电压。本征多晶硅膜可以是反掺杂的，注入低掺杂注入，注入低掺杂源/漏注入，或者与低掺杂的MOSFET LDD或延伸注入。或者，当限定耗尽多晶硅栅极硅二极管以形成低串联电阻二极管植入物时，可以在栅极结构上形成块掩模，防止膜过度掺杂。可选地，可以使用混合光致抗蚀剂方法在硅中形成更高掺杂的边缘注入，以减少二极管串联电阻而不使用块掩模。

4. 发明授权

US6097069A Method and structure for increasing the threshold voltage of a corner device 失效
标题翻译：提高拐角装置阈值电压的方法和结构
公开(公告)号：US6097069A
公开(公告)日：2000-08-01
申请号：US102196
申请日：1998-06-22
申请人： Jeffrey S. Brown , Robert J. Gauthier , Steven H. Voldman
发明人： Jeffrey S. Brown , Robert J. Gauthier , Steven H. Voldman
IPC分类号： H01L29/78 , H01L21/28 , H01L21/8238 , H01L29/423 , H01L29/76 , H01L29/00
CPC分类号： H01L21/28167 , H01L21/8238 , H01L29/42368
摘要： A structure for increasing the threshold voltage of a corner device, particularly for shallow trench isolation having narrow devices. An FET comprises a substrate having a channel formed therein under a gate between spaced source and drain regions. A trench isolation region is formed in the substrate around the transistor and on opposite sides of the channel to isolate the transistor from other devices formed in the substrate, with the trench isolation region forming first and second junction corner devices with opposite sides of the channel. A first dielectric layer is formed under the gate and over the channel of the field effect transistor to form a gate insulator for the transistor. A second corner edge dielectric layer is formed under the gate structure and over the first and second corner devices, such that the corner edge dielectric layer increases the thickness of dielectric over each corner device and thus increases the threshold voltage (Vt) and edge dielectric breakdown and decreases MOSFET corner gate-induced drain leakage.
摘要翻译：一种用于增加角装置的阈值电压的结构，特别是对于具有窄装置的浅沟槽隔离。 FET包括在间隔开的源极和漏极区之间的栅极下方形成有沟道的衬底。沟槽隔离区形成在晶体管周围的衬底和通道的相对侧上，以将晶体管与形成在衬底中的其它器件隔离，其中沟槽隔离区形成具有通道相对侧的第一和第二接合角器件。在场效应晶体管的栅极和沟道之下形成第一介电层，以形成晶体管的栅极绝缘体。在栅极结构之下和第一和第二角部器件之上形成第二角边缘电介质层，使得角部边缘电介质层增加每个拐角器件上的电介质厚度，从而增加阈值电压（Vt）和边缘电介质击穿并降低MOSFET栅极引起的漏极泄漏。

5. 发明授权

US6034388A Depleted polysilicon circuit element and method for producing the same 失效
标题翻译：耗尽多晶硅电路元件及其制造方法
公开(公告)号：US6034388A
公开(公告)日：2000-03-07
申请号：US79846
申请日：1998-05-15
申请人： Jeffrey S. Brown , Robert J. Gauthier, Jr. , Steven H. Voldman
发明人： Jeffrey S. Brown , Robert J. Gauthier, Jr. , Steven H. Voldman
IPC分类号： H01L21/334 , H01L21/762 , H01L21/8238 , H01L27/06 , H01L27/12 , H01L29/94 , H01L29/76
CPC分类号： H01L29/66181 , H01L21/76237 , H01L21/76264 , H01L21/823842 , H01L21/82385 , H01L27/0629 , H01L27/1203 , H01L29/94 , H01L21/76283 , Y10S257/907
摘要： A circuit element comprising a semiconductor substrate. A well region of a first conductivity type is formed in a surface of the substrate. A dielectric film is formed on the substrate. A gate conductor of the first conductivity type is formed on the dielectric film over the well region of the substrate. The gate conductor is formed of a polycrystalline silicon film. The gate conductor has an impurity concentration substantially lower than a standard impurity concentration for the gate conductor of an MOS device. A polycrystalline silicon edge spacer is formed on each side of the gate conductor. A first pair of first conductivity type impurity diffusion regions are formed adjacent to the polycrystalline silicon edge spacers. The polycrystalline silicon film and edge spacers lie on a portion of the substrate between the first pair of first conductivity type impurity diffusion regions. The first pair of first conductivity type impurity diffusion regions have an impurity concentration substantially lower than the standard impurity concentration for the gate conductor of an MOS device. The gate conductor and the first pair of first conductivity type impurity diffusion regions may be formed by a single implantation step. Applications include ESD protection, analog applications, peripheral input/output circuitry, decoupling capacitors, and resistor ballasting.
摘要翻译：一种包括半导体衬底的电路元件。第一导电类型的阱区形成在衬底的表面中。在基板上形成电介质膜。在衬底的阱区上的电介质膜上形成第一导电类型的栅极导体。栅极导体由多晶硅膜形成。栅极导体的杂质浓度基本上低于MOS器件的栅极导体的标准杂质浓度。在栅极导体的每一侧上形成多晶硅边缘隔离物。第一对第一导电型杂质扩散区形成在与多晶硅边缘隔离物相邻的位置。多晶硅膜和边缘隔离物位于第一对第一导电型杂质扩散区之间的衬底的一部分上。第一对第一导电型杂质扩散区的杂质浓度基本上低于MOS器件的栅极导体的标准杂质浓度。可以通过单个注入步骤形成栅极导体和第一对第一导电型杂质扩散区。应用包括ESD保护，模拟应用，外围输入/输出电路，去耦电容和电阻镇流器。

6. 发明授权

US06352905B1 Method and structure of high and low K buried oxide for SOI technology 失效
标题翻译：用于SOI技术的高K和低K埋氧体的方法和结构
公开(公告)号：US06352905B1
公开(公告)日：2002-03-05
申请号：US09702787
申请日：2000-11-01
申请人： Robert J. Gauthier, Jr. , Dominic J. Schepis , Steven H. Voldman
发明人： Robert J. Gauthier, Jr. , Dominic J. Schepis , Steven H. Voldman
IPC分类号： H01L2176
CPC分类号： H01L21/7624
摘要： A method and structure for forming an integrated circuit wafer comprises forming a substrate having first and second portions, depositing a first insulator over the substrate, patterning the first insulator such that the first insulator remains only over the first portion, depositing a second insulator over substrate (the first insulator has different thermal dissipation characteristics than the second insulator), polishing the second insulator to form a planar surface, and attaching a silicon film over the first insulator and the second insulator.
摘要翻译：用于形成集成电路晶片的方法和结构包括形成具有第一和第二部分的衬底，在衬底上沉积第一绝缘体，图案化第一绝缘体，使得第一绝缘体仅保留在第一部分之上，在衬底上沉积第二绝缘体（第一绝缘体具有与第二绝缘体不同的散热特性），抛光第二绝缘体以形成平坦表面，并且在第一绝缘体和第二绝缘体上附着硅膜。

7. 发明授权

US06256184B1 Method and apparatus for providing electrostatic discharge protection 有权
标题翻译：提供静电放电保护的方法和装置
公开(公告)号：US06256184B1
公开(公告)日：2001-07-03
申请号：US09334088
申请日：1999-06-16
申请人： Robert J. Gauthier Jr. , Edward J. Nowak , Steven H. Voldman , Richard Q. Williams
发明人： Robert J. Gauthier Jr. , Edward J. Nowak , Steven H. Voldman , Richard Q. Williams
IPC分类号： H02H322
CPC分类号： H01L27/0251 , H01L27/0266
摘要： An ESD protection method and apparatus are provided for an IC chip having an I/O pad and I/O circuitry coupled to the I/O pad. A low threshold voltage FET is coupled to the I/O pad in parallel with the I/O circuitry for protecting the IC chip from an ESD event on the I/O pad. The FET also is coupled to a first voltage terminal of the I/O circuitry for providing a shunting path for the ESD event, thereby effectuating the protecting of the IC chip from the ESD event on the I/O pad. A first control circuit is coupled to a gate of the FET for maintaining the gate at a voltage level below a threshold voltage of the FET, thereby maintaining the FET in an off state during normal operation of the IC chip. Preferably a second control circuit is coupled between the FET and the first voltage terminal and operates in conjunction with the first control circuit for maintaining the FET in an off state during normal operation of the IC chip. The first control circuit preferably comprises a short circuit between the gate of the FET and the first voltage terminal, an inverter coupled between the gate of the FET and a second voltage terminal or a negative bias generator coupled to the gate of the FET. The second control circuit preferably comprises a short circuit between the FET and the first voltage terminal or a diode coupled between the FET and the first voltage terminal.
摘要翻译：为具有耦合到I / O焊盘的I / O焊盘和I / O电路的IC芯片提供ESD保护方法和装置。低阈值电压FET与I / O电路并联耦合到I / O焊盘，以保护IC芯片免受I / O焊盘上的ESD事件。 FET还耦合到I / O电路的第一电压端子，用于为ESD事件提供分流路径，从而实现IC芯片免受I / O焊盘上的ESD事件的保护。第一控制电路耦合到FET的栅极，用于将栅极保持在低于FET阈值电压的电压电平，从而在IC芯片正常工作期间保持FET处于截止状态。优选地，第二控制电路耦合在FET和第一电压端子之间，并且与第一控制电路一起操作，以在IC芯片的正常操作期间将FET保持在截止状态。第一控制电路优选地包括在FET的栅极和第一电压端子之间的短路，耦合在FET的栅极和耦合到FET的栅极的第二电压端子或负偏压发生器之间的反相器。第二控制电路优选地包括FET和第一电压端子之间的短路或耦合在FET和第一电压端子之间的二极管。

8. 发明授权

US06232639B1 Method and structure to reduce latch-up using edge implants 失效
标题翻译：使用边缘植入物减少闭锁的方法和结构
公开(公告)号：US06232639B1
公开(公告)日：2001-05-15
申请号：US09107900
申请日：1998-06-30
申请人： Faye D. Baker , Jeffrey S. Brown , Robert J. Gauthier, Jr. , Steven J. Holmes , Robert K. Leidy , Edward J. Nowak , Steven H. Voldman
发明人： Faye D. Baker , Jeffrey S. Brown , Robert J. Gauthier, Jr. , Steven J. Holmes , Robert K. Leidy , Edward J. Nowak , Steven H. Voldman
IPC分类号： H01L2976
CPC分类号： H01L21/823878 , H01L27/0921 , Y10S148/137
摘要： The preferred embodiment of the present invention overcomes the limitations of the prior art and provides a device and method to increase the latch-up immunity of CMOS devices by forming implants at the well edges. The preferred method uses hybrid resist to form these implants at the edges of the N-wells and/or P-wells. The implants reduce the lifetime of minority carriers in the parasitic transistor, and hence reduce the gain of the parasitic transistor. This reduces the propensity of the CMOS device to latch-up. The preferred embodiment method allows these implants to be formed without requiring additional masking steps over prior art methods. Furthermore, the preferred method for forming the implants results in implants that are self aligned to the edges of the wells.
摘要翻译：本发明的优选实施例克服了现有技术的限制，并且提供了一种通过在阱边缘处形成植入物来增加CMOS器件的闩锁抗扰度的装置和方法。优选的方法使用混合抗蚀剂在N阱和/或P阱的边缘形成这些植入物。植入物减少了寄生晶体管中少数载流子的寿命，从而降低了寄生晶体管的增益。这降低了CMOS器件闭锁的倾向。优选实施例方法允许形成这些植入物，而不需要比现有技术方法更多的掩蔽步骤。此外，用于形成植入物的优选方法导致与孔的边缘自对准的植入物。

9. 发明授权

US06187617B1 Semiconductor structure having heterogeneous silicide regions and method for forming same 失效
标题翻译：具有异质硅化物区域的半导体结构及其形成方法
公开(公告)号：US06187617B1
公开(公告)日：2001-02-13
申请号：US09363558
申请日：1999-07-29
申请人： Robert J. Gauthier, Jr. , Randy W. Mann , Steven H. Voldman
发明人： Robert J. Gauthier, Jr. , Randy W. Mann , Steven H. Voldman
IPC分类号： H01L21336
CPC分类号： H01L29/4933 , H01L21/28052 , H01L21/28518 , H01L21/28568 , H01L21/823418 , H01L21/823443 , H01L29/456
摘要： A process for forming heterogeneous silicide structures on a semiconductor substrate (10) includes implanting molybdenum ions into selective areas of the semiconductor substrate (10) to form molybdenum regions (73, 74, 75, 76). Titanium is then deposited over the semiconductor substrate (10). The semiconductor substrate (10) is annealed at a temperature between approximately 600° C. and approximately 700° C. During the annealing process, the titanium deposited in areas outside the molybdenum regions (73, 74, 75, 76) interacts with silicon on the substrate to form titanium silicide in a high resistivity C49 crystal phase. The titanium deposited in areas within the molybdenum regions (73, 74, 75, 76) interacts with silicon to form titanium silicide in a low resistivity C54 crystal phase because the presence of molybdenum ions in silicon lowers the energy barrier for crystal phase transformation between the C49 phase and the C54 phase.
摘要翻译：在半导体衬底（10）上形成异质硅化物结构的方法包括将钼离子注入到半导体衬底（10）的选择区域中以形成钼区（73,74,75,76）。然后将钛沉积在半导体衬底（10）上。半导体衬底（10）在大约600℃和大约700℃之间的温度下退火。在退火过程中，沉积在钼区域（73,74,75,76）之外的区域中的钛与硅该基板在高电阻率C49晶相中形成硅化钛。在钼区域（73,74,75,76）中的区域中沉积的钛与硅相互作用以在低电阻率C54晶体相中形成硅化钛，因为硅中的钼离子的存在降低了能量势垒以进行晶体相变 C49相和C54相。

10. 发明授权

US6166420A Method and structure of high and low K buried oxide for SoI technology 失效
标题翻译：用于SoI技术的高K和低K埋氧体的方法和结构
公开(公告)号：US6166420A
公开(公告)日：2000-12-26
申请号：US526369
申请日：2000-03-16
申请人： Robert J. Gauthier, Jr. , Dominic J. Schepis , Steven H. Voldman
发明人： Robert J. Gauthier, Jr. , Dominic J. Schepis , Steven H. Voldman
IPC分类号： H01L27/04 , H01L21/762 , H01L21/822 , H01L27/12 , H01L29/786 , H01L29/00 , H01L23/58
CPC分类号： H01L21/7624
摘要： A method and structure for forming an integrated circuit wafer comprises forming a substrate having first and second portions, depositing a first insulator over the substrate, patterning the first insulator such that the first insulator remains only over the first portion, depositing a second insulator over substrate (the first insulator has different thermal dissipation characteristics than the second insulator), polishing the second insulator to form a planar surface, and attaching a silicon film over the first insulator and the second insulator.
摘要翻译：用于形成集成电路晶片的方法和结构包括形成具有第一和第二部分的衬底，在衬底上沉积第一绝缘体，图案化第一绝缘体，使得第一绝缘体仅保留在第一部分之上，在衬底上沉积第二绝缘体（第一绝缘体具有与第二绝缘体不同的散热特性），抛光第二绝缘体以形成平坦表面，并且在第一绝缘体和第二绝缘体上附着硅膜。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式