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1. 发明授权

US06710379B2 Fully relaxed channel HEMT device 有权
标题翻译：完全放松通道HEMT设备
公开(公告)号：US06710379B2
公开(公告)日：2004-03-23
申请号：US10359268
申请日：2003-02-04
申请人： Michael Wojtowicz , Tsung-Pei Chin , Michael E. Barsky , Ronald W. Grundbacher
发明人： Michael Wojtowicz , Tsung-Pei Chin , Michael E. Barsky , Ronald W. Grundbacher
IPC分类号： H01L29778
CPC分类号： H01L29/7782 , H01L29/2003
摘要： A HEMT device comprises a buffer layer disposed over a substrate. A partially-relaxed channel is disposed over the buffer layer and a barrier layer is disposed over the channel. A cap layer is disposed over the barrier layer and a gate is positioned on the barrier layer. A source and a drain are positioned on the barrier layer on opposite sides of the gate.
摘要翻译： HEMT器件包括设置在衬底上的缓冲层。部分松弛的通道设置在缓冲层之上，阻挡层设置在通道上。盖层设置在阻挡层之上并且栅极位于阻挡层上。源极和漏极位于栅极的相对侧上的势垒层上。

2. 发明授权

US06515316B1 Partially relaxed channel HEMT device 有权
标题翻译：部分放松通道HEMT设备
公开(公告)号：US06515316B1
公开(公告)日：2003-02-04
申请号：US09616852
申请日：2000-07-14
申请人： Michael Wojtowicz , Tsung-Pei Chin , Michael E. Barsky , Ronald W. Grundbacher
发明人： Michael Wojtowicz , Tsung-Pei Chin , Michael E. Barsky , Ronald W. Grundbacher
IPC分类号： H01L29778
CPC分类号： H01L29/7782 , H01L29/2003
摘要： A HEMT device comprises a buffer layer disposed over a substrate. A partially-relaxed channel is disposed over the buffer layer and a barrier layer is disposed over the channel. A cap layer is disposed over the barrier layer and a gate is positioned on the barrier layer. A source and a drain are positioned on the barrier layer on opposite sides of the gate.
摘要翻译： HEMT器件包括设置在衬底上的缓冲层。部分松弛的通道设置在缓冲层之上，阻挡层设置在通道上。盖层设置在阻挡层之上并且栅极位于阻挡层上。源极和漏极位于栅极的相对侧上的势垒层上。

3. 发明授权

US06383826B1 Method for determining etch depth 失效
标题翻译：确定蚀刻深度的方法
公开(公告)号：US06383826B1
公开(公告)日：2002-05-07
申请号：US09691636
申请日：2000-10-18
申请人： Michael E. Barsky , Richard Lai , Ronald W. Grundbacher , Rosie M. Dia , Yaochung Chen
发明人： Michael E. Barsky , Richard Lai , Ronald W. Grundbacher , Rosie M. Dia , Yaochung Chen
IPC分类号： H01L2166
CPC分类号： H01L22/26 , H01L22/12
摘要： A method for determining the etch depth of a gate recess (26) in an InP based FET device (10). The source-drain, current-voltage (I-V) relationship is monitored during the etching process. As the etch depth increases, a kink is formed in the linear portion of the I-V relationship. When the kink current reaches a desired value, the etching is stopped. The kink current is a strong function of etch depth, so small differences in etch depth can be easily targeted. By controlling the etch depth, the characteristics of the transistor can be reproducibly controlled and optimized.
摘要翻译：一种用于确定基于InP的FET器件（10）中的栅极凹槽（26）的蚀刻深度的方法。在蚀刻过程中监测源极 - 漏极，电流 - 电压（I-V）关系。当蚀刻深度增加时，在I-V关系的线性部分中形成扭结。当扭结电流达到所需值时，停止蚀刻。扭结电流是蚀刻深度的强函数，因此刻蚀深度的差异很小。通过控制蚀刻深度，可以可重复地控制和优化晶体管的特性。

4. 发明授权

US06524899B1 Process for forming a large area, high gate current HEMT diode 有权
标题翻译：用于形成大面积，高栅极电流HEMT二极管的工艺
公开(公告)号：US06524899B1
公开(公告)日：2003-02-25
申请号：US09667360
申请日：2000-09-21
申请人： Ronald W. Grundbacher , Richard Lai , Mark Kintis , Michael E. Barsky , Roger S. Tsai
发明人： Ronald W. Grundbacher , Richard Lai , Mark Kintis , Michael E. Barsky , Roger S. Tsai
IPC分类号： H01L21338
CPC分类号： H01L29/66143 , H01L21/30612 , H01L29/66462
摘要： A method of manufacturing a HEMT IC using a citric acid etchant. In order that gates of different sizes may be formed with a single etching step, a citric acid etchant is used which includes potassium citrate, citric acid and hydrogen peroxide. The wafer is first spin coated with a photoresist which is then patterned by optical lithography. The wafer is dipped in the etchant to etch the exposed semiconductor material. Metal electrodes are evaporated onto the wafer and the remaining photoresist is removed with solvent.
摘要翻译：使用柠檬酸蚀刻剂制造HEMT IC的方法。为了通过单个蚀刻步骤形成不同尺寸的浇口，使用柠檬酸蚀刻剂，其包括柠檬酸钾，柠檬酸和过氧化氢。首先用光致抗蚀剂旋转晶片，然后通过光学光刻将其形成图案。将晶片浸入蚀刻剂中以蚀刻暴露的半导体材料。将金属电极蒸发到晶片上，并用溶剂除去剩余的光致抗蚀剂。

5. 发明授权

US06396679B1 Single-layer dielectric structure with rounded corners, and circuits including such structures 有权
标题翻译：具有圆角的单层电介质结构，以及包括这种结构的电路
公开(公告)号：US06396679B1
公开(公告)日：2002-05-28
申请号：US09691459
申请日：2000-10-18
申请人： Ronald W. Grundbacher , Richard Lai , Roger S. Tsai , Michael E. Barsky
发明人： Ronald W. Grundbacher , Richard Lai , Roger S. Tsai , Michael E. Barsky
IPC分类号： H01G4228
CPC分类号： H01L28/40
摘要： A single-layer, metal-insulator-metal capacitor, a monolithic microwave integrated circuit including such capacitors, and a process of fabricating such capacitors. The capacitor has a single layer of insulating material between two metallic layers. At least one of the metallic layers has rounded corners, reducing the electric field at the corners, and so lessening the likelihood of breakdown. In one preferred embodiment, each metal layer has rounded corners. The capacitors can be fabricated by an optical lithographic process.
摘要翻译：单层金属绝缘体金属电容器，包括这种电容器的单片微波集成电路以及制造这种电容器的工艺。电容器在两个金属层之间具有单层绝缘材料。金属层中的至少一个具有圆角，减小拐角处的电场，并因此减小击穿的可能性。在一个优选实施例中，每个金属层具有圆角。电容器可以通过光学光刻工艺制造。

6. 发明授权

US06452221B1 Enhancement mode device 有权
标题翻译：增强模式设备
公开(公告)号：US06452221B1
公开(公告)日：2002-09-17
申请号：US09668120
申请日：2000-09-21
申请人： Richard Lai , Ronald W. Grundbacher , Yaochung Chen , Michael E. Barsky
发明人： Richard Lai , Ronald W. Grundbacher , Yaochung Chen , Michael E. Barsky
IPC分类号： H01L31072
CPC分类号： H01L29/7787
摘要： An enhancement mode FET device (10) that employs a strained N-doped InAlAs charge shield layer (22) disposed on an intrinsic InAlAs barrier layer (20). A gate metal electrode (38) of the FET device (10) is controllably diffused through a recess (36) into the shield layer (22) to the barrier layer (20). The resulting enhancement mode device (10) provides an excellent Schottky barrier with a high barrier height that inhibits undesirable surface depletion effects through charge shielding by the shield layer (22) in the regions between the recess edge and the gate metal. Minimizing surface depletion effects makes the device more robust by making the surface less sensitive to processing conditions and long-term operation effects.
摘要翻译：一种使用设置在本征InAlAs势垒层（20）上的应变N掺杂InAlAs电荷屏蔽层（22）的增强型FET器件（10）。 FET器件（10）的栅极金属电极（38）通过凹部（36）被可控地扩散到屏蔽层（22）中至阻挡层（20）。所产生的增强模式器件（10）提供具有高势垒高度的优异的肖特基势垒，其通过在凹口边缘和栅极金属之间的区域中的屏蔽层（22）的电荷屏蔽来抑制不期望的表面消耗效应。通过使表面对加工条件和长期运行效果较不敏感，最小化表面耗尽效应使器件更加坚固。

7. 发明授权

US06245687B1 Precision wide band gap semiconductor etching 有权
标题翻译：精密宽带隙半导体蚀刻
公开(公告)号：US06245687B1
公开(公告)日：2001-06-12
申请号：US09491961
申请日：2000-01-26
申请人： Michael E. Barsky , Rajinder R. Sandhu , Michael Wojtowicz
发明人： Michael E. Barsky , Rajinder R. Sandhu , Michael Wojtowicz
IPC分类号： H01L21461
CPC分类号： H01L29/6631 , C25F3/12
摘要： A method for etching GaN material comprising configuring the GaN material as an anode in an electrochemical cell where the electrochemical cell is comprised of an anode, a cathode and an electrolyte, and applying a bias across the anode and the cathode to a level which is sufficient to induce etching of the material. The etch rate of the material is controllable by varying the bias level. The cell is additionally illuminated with a preselected level of UV light which provides for uniformity of the etching process. The present method is particularly useful for etching a GaN HBT from n-p-n GaN material.
摘要翻译：一种用于蚀刻GaN材料的方法，包括在电化学电池中将GaN材料配置为阳极，其中电化学电池由阳极，阴极和电解质组成，并且将跨越阳极和阴极的偏压施加到足够的水平以诱导材料的蚀刻。通过改变偏置电平来控制材料的蚀刻速率。另外用预定级别的UV光照射电池，这提供了蚀刻工艺的均匀性。本方法对于从n-p-n GaN材料中蚀刻GaN HBT特别有用。

8. 发明授权

US06551905B1 Wafer adhesive for semiconductor dry etch applications 有权
标题翻译：用于半导体干蚀刻应用的晶片粘合剂
公开(公告)号：US06551905B1
公开(公告)日：2003-04-22
申请号：US09693716
申请日：2000-10-20
申请人： Michael E. Barsky , Harvey N. Rogers , Vladimir Medvedev , Yaochung Chen , Richard Lai
发明人： Michael E. Barsky , Harvey N. Rogers , Vladimir Medvedev , Yaochung Chen , Richard Lai
IPC分类号： H01L2130
CPC分类号： H01L21/6835 , H01L21/76898 , H01L23/481 , H01L2221/68318 , H01L2924/0002 , H01L2924/3025 , H01L2924/00
摘要： A method is provided for backside processing a semiconductor wafer (10) including applying a polymer based protective coating (16) on the wafer, depositing a barrier layer of ceramic (18) on the protective coating, and coating the ceramic layer with a thermoplastic based adhesive (20). Thereafter, the wafer (10) is bonded to a perforated substrate (22) and then lapped and polished to a desired thickness and patterned with an etch mask. A high temperature plasma etching process is then used to etch via holes in the wafer (10). After etching and subsequent backside processing, the adhesive layer (20) is dissolved in acetone to separate the wafer (10) from the substrate (22). The protective coating (16) is then dissolved with a solvent to separate the ceramic layer (18) from the finished wafer (10).
摘要翻译：提供了一种用于背面处理半导体晶片（10）的方法，包括在晶片上施加基于聚合物的保护涂层（16），在保护涂层上沉积陶瓷（18）的阻挡层，并用基于热塑性的涂层粘合剂（20）。此后，将晶片（10）接合到多孔基材（22）上，然后研磨并抛光至所需厚度并用蚀刻掩模图案化。然后使用高温等离子体蚀刻工艺来蚀刻晶片（10）中的通孔。在蚀刻和随后的背面处理之后，将粘合剂层（20）溶解在丙酮中以将晶片（10）与基板（22）分离。然后用溶剂溶解保护涂层（16）以将陶瓷层（18）与成品晶片（10）分离。

9. 发明授权

US06764573B2 Wafer thinning techniques 有权
标题翻译：晶圆薄化技术
公开(公告)号：US06764573B2
公开(公告)日：2004-07-20
申请号：US09977158
申请日：2001-10-11
申请人： Richard Lai , Harvey N. Rogers , Yaochung Chen , Michael E. Barsky
发明人： Richard Lai , Harvey N. Rogers , Yaochung Chen , Michael E. Barsky
IPC分类号： B08B302
CPC分类号： H01L21/30612 , H01L21/302 , H01L21/67086 , H01L21/67346
摘要： Apparatuses (10, 100), and methods of using same, for the simultaneous thinning of the backside surfaces of a plurality of semiconductor wafers (W) using a non-crystallographic and uniform etching process, are described. The apparatuses (10, 100) include a fixture (12, 102) having a plurality of horizontal receptacles (14, 16, 18, 20, 104, 106, 108, 110) for receiving the semiconductor wafers (W). The loaded fixtures (12, 102) are then immersed into an etchant solution (36, 146) that is capable of isotropically removing a layer of semiconductor material from the backside surface of the semiconductor wafers (W). The etchant solution (36, 146) is preferably heated to about 40° C.-50° C. and constantly stirred with a magnetic stirring bar (48, 158). Once a sufficient period of time has elapsed, the thinned semiconductor wafers (W) are removed from the etchant solution (36, 146). The apparatuses (10, 100) are capable of simultaneously thinning several semiconductor wafers (V) down to a final thickness of about 25 &mgr;m.
摘要翻译：描述了使用非结晶和均匀蚀刻工艺的装置（10,100）及其使用方法，用于同时薄化多个半导体晶片（W）的背面。装置（10,100）包括具有用于接收半导体晶片（W）的多个水平插座（14,16,18,20,104,106,108,110）的固定装置（12,102）。然后将装载的固定装置（12,102）浸入能够从半导体晶片（W）的背面各向同性地去除半导体材料层的蚀刻剂溶液（36,146）中。蚀刻剂溶液（36,146）优选加热至约40℃-50℃，并与磁力搅拌棒（48,158）持续搅拌。一旦经过足够的时间，就从蚀刻剂溶液（36,146）中除去变薄的半导体晶片（W）。装置（10,100）能够同时使多个半导体晶片（V）变薄至约25μm的最终厚度。

10. 发明授权

US06638366B2 Automated spray cleaning apparatus for semiconductor wafers 失效
公开(公告)号：US06638366B2
公开(公告)日：2003-10-28
申请号：US09855962
申请日：2001-05-15
申请人： Michael D. Lammert , Victor J. Watson , John M. DiMond , Michael E. Barsky
发明人： Michael D. Lammert , Victor J. Watson , John M. DiMond , Michael E. Barsky
IPC分类号： B08B302
CPC分类号： H01L21/67051 , B08B3/024 , B08B5/02
摘要： Semiconductor wafer (11) are uniformly and thoroughly cleaned of particulate and organic contaminants by sweeping the wafer with a hydraulic broom that sprays cleaning solution onto the wafer. The broom contains an aspirating nozzle (3) for connection to a source of pressurized gas, such as nitrogen, and to a source of cleaning fluid, such as acetone, wherein cleaning fluid aspirated by the gas stream is expressed through the nozzle outlet to impact the surface of the wafer, dislodging particulate matter and dissolving organic contaminants. A programmed controller (9) controls movement of the hydraulic broom relative to the wafer to ensure that the entire surface is cleaned and permits a variety of sweeping patterns.

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