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1. 发明授权

US06245687B1 Precision wide band gap semiconductor etching 有权
标题翻译：精密宽带隙半导体蚀刻
公开(公告)号：US06245687B1
公开(公告)日：2001-06-12
申请号：US09491961
申请日：2000-01-26
申请人： Michael E. Barsky , Rajinder R. Sandhu , Michael Wojtowicz
发明人： Michael E. Barsky , Rajinder R. Sandhu , Michael Wojtowicz
IPC分类号： H01L21461
CPC分类号： H01L29/6631 , C25F3/12
摘要： A method for etching GaN material comprising configuring the GaN material as an anode in an electrochemical cell where the electrochemical cell is comprised of an anode, a cathode and an electrolyte, and applying a bias across the anode and the cathode to a level which is sufficient to induce etching of the material. The etch rate of the material is controllable by varying the bias level. The cell is additionally illuminated with a preselected level of UV light which provides for uniformity of the etching process. The present method is particularly useful for etching a GaN HBT from n-p-n GaN material.
摘要翻译：一种用于蚀刻GaN材料的方法，包括在电化学电池中将GaN材料配置为阳极，其中电化学电池由阳极，阴极和电解质组成，并且将跨越阳极和阴极的偏压施加到足够的水平以诱导材料的蚀刻。通过改变偏置电平来控制材料的蚀刻速率。另外用预定级别的UV光照射电池，这提供了蚀刻工艺的均匀性。本方法对于从n-p-n GaN材料中蚀刻GaN HBT特别有用。

2. 发明授权

US06515316B1 Partially relaxed channel HEMT device 有权
标题翻译：部分放松通道HEMT设备
公开(公告)号：US06515316B1
公开(公告)日：2003-02-04
申请号：US09616852
申请日：2000-07-14
申请人： Michael Wojtowicz , Tsung-Pei Chin , Michael E. Barsky , Ronald W. Grundbacher
发明人： Michael Wojtowicz , Tsung-Pei Chin , Michael E. Barsky , Ronald W. Grundbacher
IPC分类号： H01L29778
CPC分类号： H01L29/7782 , H01L29/2003
摘要： A HEMT device comprises a buffer layer disposed over a substrate. A partially-relaxed channel is disposed over the buffer layer and a barrier layer is disposed over the channel. A cap layer is disposed over the barrier layer and a gate is positioned on the barrier layer. A source and a drain are positioned on the barrier layer on opposite sides of the gate.
摘要翻译： HEMT器件包括设置在衬底上的缓冲层。部分松弛的通道设置在缓冲层之上，阻挡层设置在通道上。盖层设置在阻挡层之上并且栅极位于阻挡层上。源极和漏极位于栅极的相对侧上的势垒层上。

3. 发明授权

US06710379B2 Fully relaxed channel HEMT device 有权
标题翻译：完全放松通道HEMT设备
公开(公告)号：US06710379B2
公开(公告)日：2004-03-23
申请号：US10359268
申请日：2003-02-04
申请人： Michael Wojtowicz , Tsung-Pei Chin , Michael E. Barsky , Ronald W. Grundbacher
发明人： Michael Wojtowicz , Tsung-Pei Chin , Michael E. Barsky , Ronald W. Grundbacher
IPC分类号： H01L29778
CPC分类号： H01L29/7782 , H01L29/2003
摘要： A HEMT device comprises a buffer layer disposed over a substrate. A partially-relaxed channel is disposed over the buffer layer and a barrier layer is disposed over the channel. A cap layer is disposed over the barrier layer and a gate is positioned on the barrier layer. A source and a drain are positioned on the barrier layer on opposite sides of the gate.
摘要翻译： HEMT器件包括设置在衬底上的缓冲层。部分松弛的通道设置在缓冲层之上，阻挡层设置在通道上。盖层设置在阻挡层之上并且栅极位于阻挡层上。源极和漏极位于栅极的相对侧上的势垒层上。

4. 发明申请

US20140264448A1 METHOD OF FORMING A GATE CONTACT 有权
标题翻译：形成门盖接触的方法
公开(公告)号：US20140264448A1
公开(公告)日：2014-09-18
申请号：US13837856
申请日：2013-03-15
申请人： CAROL O. NAMBA , Po-Hsin Lin , Poust Sumiko , Ioulia Smorchkova , Michael Wojtowicz , Ronald Grundbacher
发明人： CAROL O. NAMBA , Po-Hsin Lin , Poust Sumiko , Ioulia Smorchkova , Michael Wojtowicz , Ronald Grundbacher
IPC分类号： H01L29/778 , H01L29/66
CPC分类号： H01L21/28114 , H01L21/0277 , H01L21/28123 , H01L21/28537 , H01L21/28587 , H01L29/2003 , H01L29/42312 , H01L29/66431 , H01L29/66462 , H01L29/778 , H01L29/78
摘要： A method is provided for forming a gate contact for a compound semiconductor device. The gate contact is formed from a gate contact portion and a top or wing contact portion. The method allows for the tunablity of the size of the wing contact portion, while retaining the size of the gate contact portion based on a desired operational frequency. This is accomplished by providing for one or more additional conductive material processes on the wing contact portion to increase the cross-sectional area of the wing contact portion reducing the gate resistance, while maintaing the length of the gate contact portion to maintain the operating frequency of the device.
摘要翻译：提供了一种用于形成化合物半导体器件的栅极接触的方法。栅极接触由栅极接触部分和顶部或翼部接触部分形成。该方法允许机翼接触部分的尺寸的可操作性，同时基于期望的操作频率保持门接触部分的尺寸。这是通过在翼接触部分上提供一个或多个额外的导电材料工艺来实现的，以增加翼接触部分的横截面面积来减小栅极电阻，同时保持栅极接触部分的长度以维持栅极接触部分的工作频率装置。

5. 发明授权

US06528829B1 Integrated circuit structure having a charge injection barrier 失效
标题翻译：具有电荷注入阻挡层的集成电路结构
公开(公告)号：US06528829B1
公开(公告)日：2003-03-04
申请号：US09276041
申请日：1999-03-25
申请人： Augusto L. Gutierrez-Aitken , Aaron K. Oki , Michael Wojtowicz , Dwight C. Streit , Thomas R. Block , Frank M. Yamada
发明人： Augusto L. Gutierrez-Aitken , Aaron K. Oki , Michael Wojtowicz , Dwight C. Streit , Thomas R. Block , Frank M. Yamada
IPC分类号： H01L2970
CPC分类号： H01L21/02395 , H01L21/02463 , H01L21/02505 , H01L21/0251 , H01L21/02546 , H01L29/267 , H01L29/7371
摘要： The invention relates to an integrated circuit structure that includes a substrate wafer having an active device layer disposed on a surface of the substrate wafer and having an electrically conductive element contained therein. The integrated circuit structure further comprises a barrier disposed between the substrate wafer and the active device layer, where the barrier blocks carriers injected into the substrate wafer and reduces low frequency oscillation effect.
摘要翻译：本发明涉及一种集成电路结构，其包括具有设置在衬底晶片的表面上并且其中包含导电元件的有源器件层的衬底晶片。集成电路结构还包括设置在衬底晶片和有源器件层之间的势垒，其中势垒阻挡载流子注入衬底晶片并降低低频振荡效应。

6. 发明申请

US20080153215A1 LEAKAGE BARRIER FOR GaN BASED HEMT ACTIVE DEVICE 有权
标题翻译：用于GaN基HEMT有源器件的漏电保护器
公开(公告)号：US20080153215A1
公开(公告)日：2008-06-26
申请号：US12026099
申请日：2008-02-05
申请人： Rajinder Randy Sandhu , Michael Edward Barsky , Michael Wojtowicz
发明人： Rajinder Randy Sandhu , Michael Edward Barsky , Michael Wojtowicz
IPC分类号： H01L21/338
CPC分类号： H01L29/66462 , H01L29/2003 , H01L29/7783
摘要： An improved HEMT formed from a GaN material system is disclosed which has reduced gate leakage current relative to known GaN based HEMTs and eliminates the problem of current constrictions resulting from deposition of the gate metal over the step discontinuities formed over the gate mesa. The HEMT device is formed from a GaN material system. One or more GaN based materials are layered and etched to form a gate mesa with step discontinuities defining source and drain regions. In order to reduce the leakage current, the step discontinuities are back-filled with an insulating material, such as silicon nitride (SiN), forming a flat surface relative to the source and drain regions, to enable to the gate metal to lay flat. By back-filling the source and drain regions with an insulating material, leakage currents between the gate and source and the gate and drain are greatly reduced. In addition, current constrictions resulting from the deposition of the gate metal over a step discontinuity are virtually eliminated.
摘要翻译：公开了一种由GaN材料体系形成的改进的HEMT，其相对于已知的基于GaN的HEMT具有减小的栅极漏电流，并且消除了由栅极金属沉积在栅极台面上形成的台阶不连续部分而导致的电流限制的问题。 HEMT器件由GaN材料体系形成。层叠并蚀刻一种或多种GaN基材料以形成具有限定源极和漏极区域的步骤不连续性的栅极台面。为了减少泄漏电流，步骤不连续性用诸如氮化硅（SiN）的绝缘材料反填充，形成相对于源极和漏极区域的平坦表面，以使栅极金属能够平坦化。通过用绝缘材料对源极和漏极区域进行反向填充，栅极和源极以及栅极和漏极之间的漏电流大大降低。此外，由于栅极金属在阶梯不连续处的沉积而导致的电流限制实际上被消除。

7. 发明申请

US20050090076A1 Hard substrate wafer sawing process 有权
标题翻译：硬基片晶圆锯切工艺
公开(公告)号：US20050090076A1
公开(公告)日：2005-04-28
申请号：US10692390
申请日：2003-10-22
申请人： Michael Barsky , Michael Wojtowicz , Rajinder Sandhu
发明人： Michael Barsky , Michael Wojtowicz , Rajinder Sandhu
IPC分类号： H01L21/301 , H01L21/46 , H01L21/68 , H01L21/78
CPC分类号： H01L21/78 , H01L21/6836 , H01L2221/68327
摘要： Die of high aspect ratio formed in a hard wafer substrate are sawed out without requiring tape, obtaining high die yields. Preliminary to sawing the semiconductor die (3) from a sapphire wafer (2), the wafer is joined (20) to a silicon carrier substrate (6) by a thermoplastic layer (4) forming a unitary sandwich-like assembly. Sawing the die from the wafer follows. The thermoplastic is removed, and the die may be removed individually (50) from the silicon carrier substrate. Thermoplastic produces a bond that holds the die in place against the shear force exerted by the saw and by the stream of coolant (30).
摘要翻译：在硬质晶片基板上形成的高纵横比的裸片被锯出而不需要胶带，获得高的模头产量。初步从蓝宝石晶片（2）锯切半导体管芯（3）时，晶片通过形成单一的三明治组件的热塑性层（4）连接（20）到硅载体衬底（6）。从晶圆上切割模具如下。去除热塑性塑料，并且可以从硅载体衬底单独除去模具（50）。热塑性塑料产生粘合，其将模具保持在适当位置，抵抗由锯和冷却剂流（30）施加的剪切力。

8. 发明授权

US09048184B2 Method of forming a gate contact 有权
标题翻译：形成栅极接触的方法
公开(公告)号：US09048184B2
公开(公告)日：2015-06-02
申请号：US13837856
申请日：2013-03-15
申请人： Carol O. Namba , Po-Hsin Liu , Sumiko Poust , Ioulia Smorchkova , Michael Wojtowicz , Ronald Grundbacher
发明人： Carol O. Namba , Po-Hsin Liu , Sumiko Poust , Ioulia Smorchkova , Michael Wojtowicz , Ronald Grundbacher
IPC分类号： H01L21/28 , H01L29/778 , H01L29/66 , H01L21/285 , H01L21/027 , H01L29/78 , H01L29/423 , H01L29/20
CPC分类号： H01L21/28114 , H01L21/0277 , H01L21/28123 , H01L21/28537 , H01L21/28587 , H01L29/2003 , H01L29/42312 , H01L29/66431 , H01L29/66462 , H01L29/778 , H01L29/78
摘要： A method is provided for forming a gate contact for a compound semiconductor device. The gate contact is formed from a gate contact portion and a top or wing contact portion. The method allows for the tunablity of the size of the wing contact portion, while retaining the size of the gate contact portion based on a desired operational frequency. This is accomplished by providing for one or more additional conductive material processes on the wing contact portion to increase the cross-sectional area of the wing contact portion reducing the gate resistance, while maintaing the length of the gate contact portion to maintain the operating frequency of the device.
摘要翻译：提供了一种用于形成化合物半导体器件的栅极接触的方法。栅极接触由栅极接触部分和顶部或翼部接触部分形成。该方法允许机翼接触部分的尺寸的可操作性，同时基于期望的操作频率保持门接触部分的尺寸。这是通过在翼接触部分上提供一个或多个额外的导电材料工艺来实现的，以增加翼接触部分的横截面面积来减小栅极电阻，同时保持栅极接触部分的长度以维持栅极接触部分的工作频率装置。

9. 发明授权

US08809137B2 Leakage barrier for GaN based HEMT active device 有权
标题翻译：基于GaN的HEMT有源器件的漏电屏障
公开(公告)号：US08809137B2
公开(公告)日：2014-08-19
申请号：US13227817
申请日：2011-09-08
申请人： Rajinder Randy Sandhu , Michael Edward Barsky , Michael Wojtowicz
发明人： Rajinder Randy Sandhu , Michael Edward Barsky , Michael Wojtowicz
IPC分类号： H01L21/338 , H01L29/778 , H01L29/66 , H01L29/20
CPC分类号： H01L29/66462 , H01L29/2003 , H01L29/7783
摘要： An improved HEMT formed from a GaN material system is disclosed which has reduced gate leakage current and eliminates the problem of current constrictions resulting from deposition of the gate metal over the step discontinuities formed over the gate mesa. One or more GaN based materials are layered and etched to form a gate mesa with step discontinuities defining source and drain regions. In order to reduce the leakage current, the step discontinuities are back-filled with an insulating material, such as silicon nitride (SiN), forming a flat surface relative to the source and drain regions, to enable to the gate metal to lay flat. By back-filling the source and drain regions with an insulating material, leakage currents between the gate and source and the gate and drain are greatly reduced. In addition, current constrictions resulting from the deposition of the gate metal over a step discontinuity are virtually eliminated.
摘要翻译：公开了一种由GaN材料体系形成的改进的HEMT，其具有降低的栅极漏电流，并且消除了由栅极金属沉积在栅极台面上形成的台阶不连续部上而导致的电流限制的问题。层叠并蚀刻一种或多种GaN基材料以形成具有限定源极和漏极区域的步骤不连续性的栅极台面。为了减少泄漏电流，步骤不连续性用诸如氮化硅（SiN）的绝缘材料反填充，形成相对于源极和漏极区域的平坦表面，以使栅极金属能够平坦化。通过用绝缘材料对源极和漏极区域进行反向填充，栅极和源极以及栅极和漏极之间的漏电流大大降低。此外，由于栅极金属在阶梯不连续处的沉积而导致的电流限制实际上被消除。

10. 发明授权

US08575657B2 Direct growth of diamond in backside vias for GaN HEMT devices 有权
标题翻译：用于GaN HEMT器件的背面通孔中的金刚石的直接生长
公开(公告)号：US08575657B2
公开(公告)日：2013-11-05
申请号：US13425245
申请日：2012-03-20
申请人： Vincent Gambin , Rajinder Sandhu , Benjamin Poust , Michael Wojtowicz
发明人： Vincent Gambin , Rajinder Sandhu , Benjamin Poust , Michael Wojtowicz
IPC分类号： H01L23/10 , H01L23/34 , H01L29/66
CPC分类号： H01L29/7786 , H01L23/367 , H01L23/3732 , H01L29/2003 , H01L2924/0002 , H01L2924/00
摘要： A GaN high electron mobility transistor (HEMT) device having a silicon carbide substrate including a top surface and a bottom surface, where the substrate further includes a via formed through the bottom surface and into the substrate. The device includes a plurality of epitaxial layers provided on the top surface of the substrate, a plurality of device layers provided on the epitaxial layers, and a diamond layer provided within the via.
摘要翻译：一种GaN高电子迁移率晶体管（HEMT）器件，其具有包括顶表面和底表面的碳化硅衬底，其中衬底还包括通过底表面形成并且进入衬底的通孔。该器件包括设置在衬底的顶表面上的多个外延层，设置在外延层上的多个器件层以及设置在通孔内的金刚石层。

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