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    • 3. 发明授权
    • Method and system for distributed testing of electronic devices
    • 电子设备分布式测试方法与系统
    • US06892328B2
    • 2005-05-10
    • US09966541
    • 2001-09-27
    • Joseph C. KleinJack C. LittlePaul R. HunterArcher R. Lawrence
    • Joseph C. KleinJack C. LittlePaul R. HunterArcher R. Lawrence
    • G11C29/56G06F11/00
    • G11C29/56
    • A distributed tester method and system communicates test recipes for testing electronic devices from a host computer over a network to a test site. The test site translates test recipes into test instructions for execution by a test engine that determines the status of the electronic device. For instance, in a tester for testing memory, a test recipe is defined and stored with a host computer to determine test data for storage on the memory device under test at the test site. The host computer controls execution of the test recipe over the network. The test recipe is defined and stored in an XML formatted data file transmitted over the network to a processor at the test site. The test site processor translates the XML formatted data into test instructions for execution by a test engine. The test engine determines whether the memory device under test accurately stores data and provides the results, such as erroneously stored data, to the host computer through the network. A test design host and a global data master also interface with the network to aid the design and storage of test recipes. The distributed test method and system advantageously improves flexibility of testing over a geographically disbursed area and with divergent test recipes and devices under test.
    • 分布式测试仪方法和系统通过网络向测试站点传送测试电子样本,用于测试电子设备。 测试站点将测试配方转换为测试指令,以便由确定电子设备状态的测试引擎执行。 例如,在用于测试存储器的测试器中,定义测试配方并与主机一起存储以确定测试数据,以便在测试位置的待测存储器件上进行存储。 主机通过网络控制测试配方的执行。 测试配方被定义并存储在通过网络传输到测试站点处理器的XML格式的数据文件中。 测试站点处理器将XML格式的数据转换成测试指令,以供测试引擎执行。 测试引擎确定被测试的存储器件是否准确地存储数据,并通过网络将诸如错误存储的数据的结果提供给主计算机。 测试设计主机和全局数据主机也与网络接口,以帮助设计和存储测试配方。 分布式测试方法和系统有利地提高了在地理上支付的区域上的测试的灵活性,并且具有不同的测试配方和被测设备。
    • 6. 发明授权
    • Method and system for automatic synchronous memory identification
    • 自动同步记忆识别方法与系统
    • US06182253B2
    • 2001-01-30
    • US08895550
    • 1997-07-16
    • Archer R. LawrenceJack C. Little
    • Archer R. LawrenceJack C. Little
    • G11C2900
    • G11C29/50012G06F11/006G11C11/401G11C29/50
    • A time conserving method of identifying width, depth, access time, control line configurations, and part type of any of a plurality of different synchronous memories. A nested loop process is used to develop, and apply to a synchronous memory being identified, trial control line configurations taken from ordered entries of tables representative of the plurality of synchronous memories. The width, depth, control line configurations, and part type are determined from the responses evoked from the synchronous memory being identified. The delay between a read command issued by the test system CPU and a reading of bit patterns from the synchronous memory is incremented in finite steps in successive write/read iterations until the bit pattern read is identified to the bit pattern written into the synchronous memory, thereby identifying the access time of the synchronous memory.
    • 识别多个不同同步存储器中的任何一个的宽度,深度,访问时间,控制线配置和部件类型的时间保存方法。 使用嵌套循环过程来开发并​​应用于正在识别的同步存储器,从表示多个同步存储器的表的有序条目获取的试验控制线配置。 宽度,深度,控制线配置和部件类型根据被识别的同步存储器引发的响应来确定。 测试系统CPU发出的读取命令和来自同步存储器的位模式的读取之间的延迟在连续写入/读取迭代中以有限的步长递增,直到将位模式读取识别为写入同步存储器的位模式, 从而识别同步存储器的访问时间。