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1. 发明授权

US6064948A Tester systems 失效
标题翻译：测试仪系统
公开(公告)号：US6064948A
公开(公告)日：2000-05-16
申请号：US33364
申请日：1998-03-02
申请人： Michael S. West , Archer R. Lawrence , Paul R. Hunter , Jack C. Little
发明人： Michael S. West , Archer R. Lawrence , Paul R. Hunter , Jack C. Little
IPC分类号： G01R31/3183 , G01R31/319 , G01R31/26
CPC分类号： G01R31/318307 , G01R31/3191
摘要： A tester for use with a device under test includes a processor, a signal timing editor to create representations of signal waveforms and associated times, and a test program executable on the processor that schedules events based on information from the signal timing editor. The test program schedules different delays for the events to compensate for variations in time delays between different signals coupled to the device under test.
摘要翻译：与被测设备一起使用的测试器包括处理器，用于创建信号波形和相关时间表示的信号定时编辑器，以及可在处理器上执行的测试程序，其基于来自信号定时编辑器的信息调度事件。测试程序为事件调度不同的延迟，以补偿耦合到被测器件的不同信号之间的时间延迟的变化。

2. 发明授权

US6067648A Programmable pulse generator 失效
标题翻译：可编程脉冲发生器
公开(公告)号：US6067648A
公开(公告)日：2000-05-23
申请号：US32968
申请日：1998-03-02
申请人： Paul R. Hunter , Archer R. Lawrence , Jack C. Little
发明人： Paul R. Hunter , Archer R. Lawrence , Jack C. Little
IPC分类号： G01R31/319 , G11C29/56 , H03K5/15 , G11C29/00 , H03K5/04 , H03K7/08
CPC分类号： H03K5/1502 , G11C29/56 , G01R31/31921
摘要： A digital programmable delay which provides a series of pulses that are programmed in both pulse latency and trigger latency to control the operation of a memory module test system.
摘要翻译：数字可编程延迟，提供一系列以脉冲延迟和触发延迟编程的脉冲，以控制存储器模块测试系统的操作。

3. 发明授权

US06892328B2 Method and system for distributed testing of electronic devices 有权
标题翻译：电子设备分布式测试方法与系统
公开(公告)号：US06892328B2
公开(公告)日：2005-05-10
申请号：US09966541
申请日：2001-09-27
申请人： Joseph C. Klein , Jack C. Little , Paul R. Hunter , Archer R. Lawrence
发明人： Joseph C. Klein , Jack C. Little , Paul R. Hunter , Archer R. Lawrence
IPC分类号： G11C29/56 , G06F11/00
CPC分类号： G11C29/56
摘要： A distributed tester method and system communicates test recipes for testing electronic devices from a host computer over a network to a test site. The test site translates test recipes into test instructions for execution by a test engine that determines the status of the electronic device. For instance, in a tester for testing memory, a test recipe is defined and stored with a host computer to determine test data for storage on the memory device under test at the test site. The host computer controls execution of the test recipe over the network. The test recipe is defined and stored in an XML formatted data file transmitted over the network to a processor at the test site. The test site processor translates the XML formatted data into test instructions for execution by a test engine. The test engine determines whether the memory device under test accurately stores data and provides the results, such as erroneously stored data, to the host computer through the network. A test design host and a global data master also interface with the network to aid the design and storage of test recipes. The distributed test method and system advantageously improves flexibility of testing over a geographically disbursed area and with divergent test recipes and devices under test.
摘要翻译：分布式测试仪方法和系统通过网络向测试站点传送测试电子样本，用于测试电子设备。测试站点将测试配方转换为测试指令，以便由确定电子设备状态的测试引擎执行。例如，在用于测试存储器的测试器中，定义测试配方并与主机一起存储以确定测试数据，以便在测试位置的待测存储器件上进行存储。主机通过网络控制测试配方的执行。测试配方被定义并存储在通过网络传输到测试站点处理器的XML格式的数据文件中。测试站点处理器将XML格式的数据转换成测试指令，以供测试引擎执行。测试引擎确定被测试的存储器件是否准确地存储数据，并通过网络将诸如错误存储的数据的结果提供给主计算机。测试设计主机和全局数据主机也与网络接口，以帮助设计和存储测试配方。分布式测试方法和系统有利地提高了在地理上支付的区域上的测试的灵活性，并且具有不同的测试配方和被测设备。

4. 发明授权

US06285962B1 Method and system for testing rambus memory modules 失效
标题翻译：测试Rambus内存模块的方法和系统
公开(公告)号：US06285962B1
公开(公告)日：2001-09-04
申请号：US09267731
申请日：1999-03-15
申请人： Paul R. Hunter
发明人： Paul R. Hunter
IPC分类号： G01R3127
CPC分类号： G11C29/56 , G01R31/31905 , G01R31/3191 , G01R31/31937
摘要： A system and method for testing a RIMM loaded with RDRAM integrated circuits generates and reads test transaction data with a test transaction engine, such as a microprocessor-based memory tester. A RIMM adapter interfaces with the test transaction engine and the RIMM under test to communicate test data, including test write, address, control and read data. A comparison of test read data returned to the test transaction engine from the RIMM against predetermined values allows a determination of the operational status of the RIMM. The RIMM adapter is embodied as an ASIC with plural FIFO circuits interfaced between the test transaction engine and a channel controller and RAC. The FIFOs reconcile differences in timing between generation and return of test data and demands by the RAC and channel controller. Separate read and write data paths between the test transaction engine and ASIC support improved rates of data transfer. The test transaction engine provides full speed test transactions by using instruction data to generate test data with FPGAs.
摘要翻译：用于测试装载有RDRAM集成电路的RIMM的系统和方法使用诸如基于微处理器的存储器测试器之类的测试事务引擎生成并读取测试交易数据。 RIMM适配器与测试事务引擎和正在测试的RIMM进行接口，以通信测试数据，包括测试写入，地址，控制和读取数据。从RIMM返回到测试事务引擎的测试读取数据与预定值的比较允许确定RIMM的操作状态。 RIMM适配器实现为具有接口在测试事务引擎和通道控制器与RAC之间的多个FIFO电路的ASIC。 FIFO调和RAC和通道控制器产生和返回测试数据和要求之间的时间差异。在测试事务引擎和ASIC之间分离读写数据路径可以提高数据传输速率。测试事务引擎通过使用指令数据来生成测试数据，提供全速测试事务。

5. 发明授权

US4684801A Signal preconditioning for touch entry device 失效
标题翻译：触摸输入设备的信号预处理
公开(公告)号：US4684801A
公开(公告)日：1987-08-04
申请号：US835015
申请日：1986-02-28
申请人： Arthur B. Carroll , Stewart E. Hough , Paul R. Hunter , John K. Carstedt , Sam R. Shaw , James E. Garrett
发明人： Arthur B. Carroll , Stewart E. Hough , Paul R. Hunter , John K. Carstedt , Sam R. Shaw , James E. Garrett
IPC分类号： G01B11/00 , G01V8/20 , G06F3/033 , G06F3/041 , G06F3/042 , H03K17/94 , G09G1/28
CPC分类号： G06F3/0421 , G01V8/20 , H03K17/941
摘要： A touch entry system employing arrays of emitter and detector opto devices located around the periphery of an irradiated field detects intrusion of an opaque element such as a stylus within the field. The detector analog output is converted to a digital signal for input into a microprocessor. Digital signals input into the microprocessor can vary due to inconsistencies in conventional opto devices. A programmable amplifier responsive to the microprocessors preconditions the analog signals prior to analog to digital conversion to bring all digital signals corresponding to the unblocked emitter beam condition within a normalized range before input into the microprocessor.

6. 发明授权

US06480799B2 Method and system for testing RAMBUS memory modules 有权
标题翻译：用于测试RAMBUS内存模块的方法和系统
公开(公告)号：US06480799B2
公开(公告)日：2002-11-12
申请号：US09943721
申请日：2001-08-31
申请人： Paul R. Hunter
发明人： Paul R. Hunter
IPC分类号： G01R3127
CPC分类号： G11C29/56 , G01R31/31905 , G01R31/3191 , G01R31/31937
摘要： A system and method for testing a RIMM loaded with RDRAM integrated circuits generates and reads test transaction data with a test transaction engine, such as a microprocessor-based memory tester. A RIMM adapter interfaces with the test transaction engine and the RIMM under test to communicate test data, including test write, address, control and read data. A comparison of test read data returned to the test transaction engine from the RIMM against predetermined values allows a determination of the operational status of the RIMM. The RIMM adapter is embodied as an ASIC with plural FIFO circuits interfaced between the test transaction engine and a channel controller and RAC. The FIFOs reconcile differences in timing between generation and return of test data and demands by the RAC and channel controller. Separate read and write data paths between the test transaction engine and ASIC support improved rates of data transfer. The test transaction engine provides full speed test transactions by using instruction data to generate test data with FPGAs.
摘要翻译：用于测试装载有RDRAM集成电路的RIMM的系统和方法使用诸如基于微处理器的存储器测试器之类的测试事务引擎生成并读取测试交易数据。 RIMM适配器与测试事务引擎和正在测试的RIMM进行接口，以通信测试数据，包括测试写入，地址，控制和读取数据。从RIMM返回到测试事务引擎的测试读取数据与预定值的比较允许确定RIMM的操作状态。 RIMM适配器实现为具有接口在测试事务引擎和通道控制器与RAC之间的多个FIFO电路的ASIC。 FIFO调和RAC和通道控制器产生和返回测试数据和要求之间的时间差异。在测试事务引擎和ASIC之间分离读写数据路径可以提高数据传输速率。测试事务引擎通过使用指令数据来生成测试数据，提供全速测试事务。

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