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1. 发明授权

US07081393B2 Reduced dielectric constant spacer materials integration for high speed logic gates 失效
标题翻译：降低介电常数间隔材料集成用于高速逻辑门
公开(公告)号：US07081393B2
公开(公告)日：2006-07-25
申请号：US10709652
申请日：2004-05-20
申请人： Michael P. Belyansky , Joyce C. Liu , Hsing Jen Wann , Richard Stephen Wise , Hongwen Yan
发明人： Michael P. Belyansky , Joyce C. Liu , Hsing Jen Wann , Richard Stephen Wise , Hongwen Yan
IPC分类号： H01L21/336
CPC分类号： H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： An FET transistor has a gate disposed between a source and a drain; a gate dielectric layer disposed underneath the gate; and a spacer on a side of the gate. The gate dielectric layer is conventional oxide and the spacer has a reduced dielectric constant (k). The reduced dielectric constant (k) may be less than 3.85, or it may be less than 7.0 (˜nitride), but greater than 3.85 (˜oxide). Preferably, the spacer comprises a material which can be etched selectively to the gate dielectric layer. The spacer may be porous, and a thin layer is deposited on the porous spacer to prevent moisture absorption. The spacer may comprise a material selected from the group consisting of Black Diamond, Coral, TERA and Blok type materials. Pores may be formed in the spacer material by exposing the spacers to an oxygen plasma.
摘要翻译： FET晶体管具有设置在源极和漏极之间的栅极; 设置在栅极下方的栅介质层; 和在门侧的间隔物。栅极电介质层是常规的氧化物，间隔物具有降低的介电常数（k）。降低的介电常数（k）可以小于3.85，或者可以小于7.0（〜氮化物），但大于3.85（〜氧化物）。优选地，间隔物包括可以选择性地蚀刻到栅极介电层的材料。间隔物可以是多孔的，并且在多孔间隔物上沉积薄层以防止吸湿。间隔物可以包括选自黑钻石，珊瑚，TERA和Blok型材料的材料。可以通过将间隔物暴露于氧等离子体来在间隔物材料中形成孔。

2. 发明申请

US20050260819A1 REDUCED DIELECTRIC CONSTANT SPACER MATERIALS INTEGRATION FOR HIGH SPEED LOGIC GATES 失效
标题翻译：减少电介质间隔材料高速逻辑门集成
公开(公告)号：US20050260819A1
公开(公告)日：2005-11-24
申请号：US10709652
申请日：2004-05-20
申请人： Michael Belyansky , Joyce Liu , Hsing Jen Wann , Richard Wise , Hongwen Yan
发明人： Michael Belyansky , Joyce Liu , Hsing Jen Wann , Richard Wise , Hongwen Yan
IPC分类号： H01L21/316 , H01L21/336 , H01L21/4763 , H01L27/088 , H01L29/78 , H01L29/786
CPC分类号： H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： An FET transistor has a gate disposed between a source and a drain; a gate dielectric layer disposed underneath the gate; and a spacer on a side of the gate. The gate dielectric layer is conventional oxide and the spacer has a reduced dielectric constant (k). The reduced dielectric constant (k) may be less than 3.85, or it may be less than 7.0 (˜nitride), but greater than 3.85 (˜oxide). Preferably, the spacer comprises a material which can be etched selectively to the gate dielectric layer. The spacer may be porous, and a thin layer is deposited on the porous spacer to prevent moisture absorption. The spacer may comprise a material selected from the group consisting of Black Diamond, Coral, TERA and Blok type materials. Pores may be formed in the spacer material by exposing the spacers to an oxygen plasma.
摘要翻译： FET晶体管具有设置在源极和漏极之间的栅极; 设置在栅极下方的栅介质层; 和在门侧的间隔物。栅极电介质层是常规的氧化物，间隔物具有降低的介电常数（k）。降低的介电常数（k）可以小于3.85，或者可以小于7.0（〜氮化物），但大于3.85（〜氧化物）。优选地，间隔物包括可以选择性地蚀刻到栅极介电层的材料。间隔物可以是多孔的，并且在多孔间隔物上沉积薄层以防止吸湿。间隔物可以包括选自黑钻石，珊瑚，TERA和Blok型材料的材料。可以通过将间隔物暴露于氧等离子体来在间隔物材料中形成孔。

3. 发明授权

US07691701B1 Method of forming gate stack and structure thereof 失效
标题翻译：形成栅极叠层的方法及其结构
公开(公告)号：US07691701B1
公开(公告)日：2010-04-06
申请号：US12348332
申请日：2009-01-05
申请人： Michael P. Belyansky , Siddarth A. Krishnan , Unoh Kwon , Naim Moumen , Ravikumar Ramachandran , James Kenyon Schaeffer , Richard Wise , Keith Kwong Hon Wong , Hongwen Yan
发明人： Michael P. Belyansky , Siddarth A. Krishnan , Unoh Kwon , Naim Moumen , Ravikumar Ramachandran , James Kenyon Schaeffer , Richard Wise , Keith Kwong Hon Wong , Hongwen Yan
IPC分类号： H01L21/00
CPC分类号： H01L21/823842 , H01L21/823857
摘要： Embodiments of the present invention provide a method of forming gate stacks for field-effect-transistors. The method includes forming a metal-containing layer directly on a first titanium-nitride (TiN) layer, the first TiN layer covering areas of a semiconductor substrate designated for first and second types of field-effect-transistors; forming a capping layer of a second TiN layer on top of the metal-containing layer; patterning the second TiN layer and the metal-containing layer to cover only a first portion of the first TiN layer, the first portion of the first TiN layer covering an area designated for the first type of field-effect-transistors; etching away a second portion of the first TiN layer exposed by the patterning while protecting the first portion of the first TiN layer, from the etching, through covering with at least a portion of thickness of the patterned metal-containing layer; and forming a third TiN layer covering an areas of the semiconductor substrate designated for the second type of field-effect-transistors.
摘要翻译：本发明的实施例提供了一种形成场效应晶体管的栅叠层的方法。该方法包括直接在第一氮化钛（TiN）层上形成含金属层，第一TiN层覆盖用于第一和第二类场效应晶体管的半导体衬底的区域; 在所述含金属层的顶部上形成第二TiN层的覆盖层; 图案化第二TiN层和含金属层以仅覆盖第一TiN层的第一部分，第一TiN层的第一部分覆盖指定用于第一类型的场效应晶体管的区域; 蚀刻通过图案化暴露的第一TiN层的第二部分，同时通过覆盖图案化的含金属层的厚度的至少一部分来保护第一TiN层的第一部分免受蚀刻; 以及形成覆盖指定用于第二类场效应晶体管的半导体衬底的区域的第三TiN层。

4. 发明授权

US07749830B2 CMOS (complementary metal oxide semiconductor) devices having metal gate NFETS and poly-silicon gate PFETS 失效
标题翻译：具有金属栅极NFETS和多晶硅栅极PFETS的CMOS（互补金属氧化物半导体）器件
公开(公告)号：US07749830B2
公开(公告)日：2010-07-06
申请号：US12026793
申请日：2008-02-06
申请人： Bruce Bennett Doris , William K. Henson , Richard Stephen Wise , Hongwen Yan
发明人： Bruce Bennett Doris , William K. Henson , Richard Stephen Wise , Hongwen Yan
IPC分类号： H01L21/8238
CPC分类号： H01L21/823842
摘要： A semiconductor structure fabrication method. The method includes providing a structure which includes (a) first and second semiconductor regions, (b) first and second gate dielectric regions on the first and second semiconductor regions, respectively, (c) a high-K dielectric region on the first gate dielectric region, K being greater than 4, (d) an electrically conductive layer on the high-K dielectric region, (e) a poly-silicon layer on the electrically conductive layer and the second gate dielectric region, and (f) a hard mask layer on the poly-silicon layer. The hard mask layer is patterned resulting in first and second hard mask regions. The poly-silicon layer is etched with the first and second hard mask regions as blocking masks resulting in first and second poly-silicon regions. The first and second poly-silicon regions are exposed to a surrounding ambient.
摘要翻译：半导体结构制造方法。该方法包括提供一种结构，该结构包括（a）分别在第一和第二半导体区域上的第一和第二半导体区域，（b）第一和第二栅极电介质区域，（c）第一栅极电介质上的高K电介质区域区域，K大于4，（d）高K电介质区域上的导电层，（e）导电层和第二栅极电介质区域上的多晶硅层，以及（f）硬掩模层在多晶硅层上。对硬掩模层进行图案化，形成第一和第二硬掩模区域。用第一和第二硬掩模区域蚀刻多晶硅层作为阻挡掩模，产生第一和第二多晶硅区域。第一和第二多晶硅区域暴露于周围环境。

5. 发明申请

US20100258875A1 CMOS (COMPLEMENTARY METAL OXIDE SEMICONDUCTOR) DEVICES HAVING METAL GATE NFETS AND POLY-SILICON GATE PFETS 失效
标题翻译：具有金属栅极NFET和聚硅栅极的CMOS（补充金属氧化物半导体）器件
公开(公告)号：US20100258875A1
公开(公告)日：2010-10-14
申请号：US12823225
申请日：2010-06-25
申请人： Bruce Bennett Doris , William K. Henson , Richard Stephen Wise , Hongwen Yan
发明人： Bruce Bennett Doris , William K. Henson , Richard Stephen Wise , Hongwen Yan
IPC分类号： H01L27/088
CPC分类号： H01L21/823842
摘要： A semiconductor structure. The semiconductor structure includes: a first semiconductor region and a second semiconductor region; a first gate dielectric region on the first semiconductor region; a second gate dielectric region on the second semiconductor region, wherein the second semiconductor region includes a first top surface shared by the second semiconductor region and the second gate dielectric region, and wherein the first top surface defines a reference direction perpendicular to the first top surface and pointing from inside to outside of the second semiconductor region; an electrically conductive layer on the first gate dielectric region; a first poly-silicon region on the electrically conductive layer; a second poly-silicon region on the second gate dielectric region; a first hard mask region on the first poly-silicon region; and a second hard mask region on the second poly-silicon region.
摘要翻译：半导体结构。半导体结构包括：第一半导体区域和第二半导体区域; 在所述第一半导体区域上的第一栅极电介质区域; 在所述第二半导体区域上的第二栅极电介质区域，其中所述第二半导体区域包括由所述第二半导体区域和所述第二栅极电介质区域共享的第一顶表面，并且其中所述第一顶表面限定垂直于所述第一顶表面的参考方向并从第二半导体区域的内部指向外部; 在所述第一栅极电介质区域上的导电层; 导电层上的第一多晶硅区; 在所述第二栅极电介质区域上的第二多晶硅区域; 第一多晶硅区域上的第一硬掩模区域; 以及第二多晶硅区域上的第二硬掩模区域。

6. 发明申请

US20080194112A1 METHOD AND SYSTEM FOR PLASMA ETCHING HAVING IMPROVED ACROSS-WAFER ETCH UNIFORMITY 审中-公开
标题翻译：等离子体蚀刻的方法和系统具有改进的跨越蚀刻均匀性
公开(公告)号：US20080194112A1
公开(公告)日：2008-08-14
申请号：US11673128
申请日：2007-02-09
申请人： Qingyun Yang , Joyce C. Liu , Hongwen Yan , Ying Zhang
发明人： Qingyun Yang , Joyce C. Liu , Hongwen Yan , Ying Zhang
IPC分类号： H01L21/3065
CPC分类号： H01L21/32136 , H01L21/32137 , H01L21/6708
摘要： A method for improving across-wafer etch uniformity of semiconductor devices in an etching chamber, wherein the method includes: introducing a first flow of gas mixtures from a central gas distribution plate manifold; introducing a second flow of gas mixtures from an auxiliary gas feed; and controlling process parameters including one or more of: duration, power, pressure, and gas flow rates for the first and second flow of gas mixtures; wherein the central gas distribution plate manifold is positioned above the semiconductor wafer; wherein the auxiliary gas feed is positioned around the perimeter of the semiconductor wafer; and wherein the controlling of the process parameters of the central gas distribution plate manifold and the auxiliary gas feed is facilitated by independent controls.
摘要翻译：一种用于改善蚀刻室中的半导体器件的跨晶片蚀刻均匀性的方法，其中所述方法包括：从中央气体分配板歧管引入第一气体混合物流; 从辅助气体进料引入第二气体混合物流; 以及控制过程参数，包括以下一个或多个：气体混合物的第一和第二流动的持续时间，功率，压力和气体流速; 其中所述中央气体分配板歧管位于所述半导体晶片的上方; 其中所述辅助气体进料围绕所述半导体晶片的周边定位; 并且其中通过独立控制来促进对中央气体分配板歧管和辅助气体进料的工艺参数的控制。

7. 发明授权

US06838347B1 Method for reducing line edge roughness of oxide material using chemical oxide removal 失效
标题翻译：使用化学氧化物去除减少氧化物材料的线边缘粗糙度的方法
公开(公告)号：US06838347B1
公开(公告)日：2005-01-04
申请号：US10605331
申请日：2003-09-23
申请人： Joyce C. Liu , Wesley C. Natzle , Richard S. Wise , Hongwen Yan , Bidan Zhang
发明人： Joyce C. Liu , Wesley C. Natzle , Richard S. Wise , Hongwen Yan , Bidan Zhang
IPC分类号： H01L21/311 , H01L21/3205 , H01L21/3213 , H01L21/336 , H01L21/4763
CPC分类号： H01L21/32139 , H01L21/31116
摘要： A method for reducing line edge roughness (LER) of a semiconductor gate structure includes patterning a photoresist layer formed over an oxide hardmask layer. The photoresist layer is etched so as to transfer a photoresist pattern to the oxide hardmask layer, the photoresist pattern having an initial LER. The exposed surfaces of the oxide hardmask are etched with a chemical oxide removal (COR) so as to form a reaction product on the exposed surfaces, wherein concave portions of the exposed surfaces are etched at a reduced rate with respect to convex portions of the exposed surfaces.

8. 发明申请

US20080182372A1 METHOD OF FORMING DISPOSABLE SPACERS FOR IMPROVED STRESSED NITRIDE FILM EFFECTIVENESS 审中-公开
标题翻译：形成改善间隔物的方法，用于改善耐压氮化膜的有效性
公开(公告)号：US20080182372A1
公开(公告)日：2008-07-31
申请号：US11669645
申请日：2007-01-31
申请人： Joyce C. Liu , Hongwen Yan , Qingyun Yang , Ying Zhang
发明人： Joyce C. Liu , Hongwen Yan , Qingyun Yang , Ying Zhang
IPC分类号： H01L21/8238
CPC分类号： H01L29/6653 , H01L21/3146 , H01L21/823864 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/7843
摘要： A method of forming a complementary metal oxide semiconductor (CMOS) device includes forming an oxide layer on sidewalls and a top surface of a patterned gate conductor, and on sidewalls of a gate insulating layer formed on a semiconductor substrate; forming a first carbon-based layer over the gate conductor, gate insulating layer, and substrate; etching the first carbon-based layer so as to create a first set of carbon spacers; forming a second carbon-based layer over the gate conductor, gate insulating layer, substrate, and first set of carbon spacers; etching the second carbon-based layer so as to create a second set of carbon spacers; forming silicide contacts on the gate conductor, and on source and drain regions formed in the substrate; removing the first and second sets of carbon spacers; and forming a stress-inducing nitride layer over the substrate, silicide contacts, gate conductor, and gate insulating layer.
摘要翻译：形成互补金属氧化物半导体（CMOS）器件的方法包括在图案化栅极导体的侧壁和顶表面上以及形成在半导体衬底上的栅极绝缘层的侧壁上形成氧化物层; 在栅极导体，栅极绝缘层和衬底上形成第一碳基层; 蚀刻第一碳基层以产生第一组碳间隔物; 在栅极导体，栅极绝缘层，衬底和第一组碳隔离物上形成第二碳基层; 蚀刻第二碳基层以产生第二组碳间隔物; 在栅极导体上形成硅化物触点，以及在衬底中形成的源极和漏极区上; 去除第一和第二组碳间隔物; 以及在衬底上形成应力诱导氮化物层，硅化物接触，栅极导体和栅极绝缘层。

9. 发明申请

US20090194820A1 CMOS (COMPLEMENTARY METAL OXIDE SEMICONDUCTOR) DEVICES HAVING METAL GATE NFETS AND POLY-SILICON GATE PFETS 失效
标题翻译：具有金属栅极NFET和聚硅栅极的CMOS（补充金属氧化物半导体）器件
公开(公告)号：US20090194820A1
公开(公告)日：2009-08-06
申请号：US12026793
申请日：2008-02-06
申请人： Bruce Bennett Doris , William K. Henson , Richard Stephen Wise , Hongwen Yan
发明人： Bruce Bennett Doris , William K. Henson , Richard Stephen Wise , Hongwen Yan
IPC分类号： H01L27/00 , H01L21/8238
CPC分类号： H01L21/823842
摘要： A semiconductor structure fabrication method. The method includes providing a structure which includes (a) first and second semiconductor regions, (b) first and second gate dielectric regions on the first and second semiconductor regions, respectively, (c) a high-K dielectric region on the first gate dielectric region, K being greater than 4, (d) an electrically conductive layer on the high-K dielectric region, (e) a poly-silicon layer on the electrically conductive layer and the second gate dielectric region, and (f) a hard mask layer on the poly-silicon layer. The hard mask layer is patterned resulting in first and second hard mask regions. The poly-silicon layer is etched with the first and second hard mask regions as blocking masks resulting in first and second poly-silicon regions. The first and second poly-silicon regions are exposed to a surrounding ambient.
摘要翻译：半导体结构制造方法。该方法包括提供一种结构，该结构包括（a）分别在第一和第二半导体区域上的第一和第二半导体区域，（b）第一和第二栅极电介质区域，（c）第一栅极电介质上的高K电介质区域区域，K大于4，（d）高K电介质区域上的导电层，（e）导电层和第二栅极电介质区域上的多晶硅层，以及（f）硬掩模层在多晶硅层上。对硬掩模层进行图案化，形成第一和第二硬掩模区域。用第一和第二硬掩模区域蚀刻多晶硅层作为阻挡掩模，产生第一和第二多晶硅区域。第一和第二多晶硅区域暴露于周围环境。

10. 发明授权

US08018005B2 CMOS (complementary metal oxide semiconductor) devices having metal gate NFETs and poly-silicon gate PFETs 失效
标题翻译：具有金属栅极NFET和多晶硅栅极PFET的CMOS（互补金属氧化物半导体）器件
公开(公告)号：US08018005B2
公开(公告)日：2011-09-13
申请号：US12823225
申请日：2010-06-25
申请人： Bruce Bennett Doris , William K. Henson , Richard Stephen Wise , Hongwen Yan
发明人： Bruce Bennett Doris , William K. Henson , Richard Stephen Wise , Hongwen Yan
IPC分类号： H01L21/70
CPC分类号： H01L21/823842
摘要： A semiconductor structure. The semiconductor structure includes: a first semiconductor region and a second semiconductor region; a first gate dielectric region on the first semiconductor region; a second gate dielectric region on the second semiconductor region, wherein the second semiconductor region includes a first top surface shared by the second semiconductor region and the second gate dielectric region, and wherein the first top surface defines a reference direction perpendicular to the first top surface and pointing from inside to outside of the second semiconductor region; an electrically conductive layer on the first gate dielectric region; a first poly-silicon region on the electrically conductive layer; a second poly-silicon region on the second gate dielectric region; a first hard mask region on the first poly-silicon region; and a second hard mask region on the second poly-silicon region.
摘要翻译：半导体结构。半导体结构包括：第一半导体区域和第二半导体区域; 在所述第一半导体区域上的第一栅极电介质区域; 在所述第二半导体区域上的第二栅极电介质区域，其中所述第二半导体区域包括由所述第二半导体区域和所述第二栅极电介质区域共享的第一顶表面，并且其中所述第一顶表面限定垂直于所述第一顶表面的参考方向并从第二半导体区域的内部指向外部; 在所述第一栅极电介质区域上的导电层; 导电层上的第一多晶硅区; 在所述第二栅极电介质区域上的第二多晶硅区域; 第一多晶硅区域上的第一硬掩模区域; 以及第二多晶硅区域上的第二硬掩模区域。

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