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1. 发明授权

US06838347B1 Method for reducing line edge roughness of oxide material using chemical oxide removal 失效
标题翻译：使用化学氧化物去除减少氧化物材料的线边缘粗糙度的方法
公开(公告)号：US06838347B1
公开(公告)日：2005-01-04
申请号：US10605331
申请日：2003-09-23
申请人： Joyce C. Liu , Wesley C. Natzle , Richard S. Wise , Hongwen Yan , Bidan Zhang
发明人： Joyce C. Liu , Wesley C. Natzle , Richard S. Wise , Hongwen Yan , Bidan Zhang
IPC分类号： H01L21/311 , H01L21/3205 , H01L21/3213 , H01L21/336 , H01L21/4763
CPC分类号： H01L21/32139 , H01L21/31116
摘要： A method for reducing line edge roughness (LER) of a semiconductor gate structure includes patterning a photoresist layer formed over an oxide hardmask layer. The photoresist layer is etched so as to transfer a photoresist pattern to the oxide hardmask layer, the photoresist pattern having an initial LER. The exposed surfaces of the oxide hardmask are etched with a chemical oxide removal (COR) so as to form a reaction product on the exposed surfaces, wherein concave portions of the exposed surfaces are etched at a reduced rate with respect to convex portions of the exposed surfaces.

2. 发明申请

US20080286972A1 ADDITION OF BALLAST HYDROCARBON GAS TO DOPED POLYSILICON ETCH MASKED BY RESIST 有权
标题翻译：添加沉积物中的多氯硅烷蚀刻阻垢剂
公开(公告)号：US20080286972A1
公开(公告)日：2008-11-20
申请号：US12170634
申请日：2008-07-10
申请人： Timothy J. Dalton , Wesley C. Natzle , Paul W. Pastel , Richard S. Wise , Hongwen Yan , Ying Zhang
发明人： Timothy J. Dalton , Wesley C. Natzle , Paul W. Pastel , Richard S. Wise , Hongwen Yan , Ying Zhang
IPC分类号： H01L21/308
CPC分类号： H01L21/32139 , H01L21/32137 , Y10S438/909
摘要： A chemical composition and method for providing uniform and consistent etching of gate stacks on a semiconductor wafer, whereby the composition includes an etchant and an added ballast gas added. The gate stacks are formed using this combined etchant and ballast gas composition. The ballast gas may either be similar to, or the equivalent of, a gaseous byproduct generated within the processing chamber. The ballast gas is added in either an overload amount, or in an amount sufficient to compensate for varying pattern factor changes across the water. This etchant and added ballast gas form a substantially homogeneous etchant across the entire wafer, thereby accommodating for or compensating for these pattern factor differences. When etching the wafer using this homogeneous etchant, a passivation layer is formed on exposed wafer surfaces. The passivation layer protects the lateral sidewalls of the gate stacks during etch to result in straighter gate stacks.
摘要翻译：一种用于在半导体晶片上提供均匀且一致的栅叠层蚀刻的化学组成和方法，由此所述组合物包括添加的蚀刻剂和添加的压载气体。使用这种组合的蚀刻剂和压载气组合物形成栅堆叠。压载气体可以类似于或等同于在处理室内产生的气态副产物。压载气体以过载量或足以补偿横跨水的变化因子变化的量加入。这种蚀刻剂和添加的压载气体在整个晶片上形成基本均匀的蚀刻剂，从而适应或补偿这些图案因子差异。当使用这种均匀的蚀刻剂蚀刻晶片时，在暴露的晶片表面上形成钝化层。钝化层在蚀刻期间保护栅极堆叠的侧壁以产生更直的栅叠层。

3. 发明授权

US08198103B2 Addition of ballast hydrocarbon gas to doped polysilicon etch masked by resist 有权
标题翻译：添加压敏烃气体到由抗蚀剂掩蔽的掺杂多晶硅蚀刻
公开(公告)号：US08198103B2
公开(公告)日：2012-06-12
申请号：US12170634
申请日：2008-07-10
申请人： Timothy J. Dalton , Wesley C. Natzle , Paul W. Pastel , Richard S. Wise , Hongwen Yan , Ying Zhang
发明人： Timothy J. Dalton , Wesley C. Natzle , Paul W. Pastel , Richard S. Wise , Hongwen Yan , Ying Zhang
IPC分类号： H01L21/302
CPC分类号： H01L21/32139 , H01L21/32137 , Y10S438/909
摘要： A chemical composition and method for providing uniform and consistent etching of gate stacks on a semiconductor wafer, whereby the composition includes an etchant and an added ballast gas added. The gate stacks are formed using this combined etchant and ballast gas composition. The ballast gas may either be similar to, or the equivalent of, a gaseous byproduct generated within the processing chamber. The ballast gas is added in either an overload amount, or in an amount sufficient to compensate for varying pattern factor changes across the water. This etchant and added ballast gas form a substantially homogeneous etchant across the entire wafer, thereby accommodating for or compensating for these pattern factor differences. When etching the wafer using this homogeneous etchant, a passivation layer is formed on exposed wafer surfaces. The passivation layer protects the lateral sidewalls of the gate stacks during etch to result in straighter gate stacks.
摘要翻译：一种用于在半导体晶片上提供均匀且一致的栅叠层蚀刻的化学组成和方法，由此所述组合物包括添加的蚀刻剂和添加的压载气体。使用这种组合的蚀刻剂和压载气组合物形成栅堆叠。压载气体可以类似于或等同于在处理室内产生的气态副产物。压载气体以过载量或足以补偿横跨水的变化因子变化的量加入。这种蚀刻剂和添加的压载气体在整个晶片上形成基本均匀的蚀刻剂，从而适应或补偿这些图案因子差异。当使用这种均匀的蚀刻剂蚀刻晶片时，在暴露的晶片表面上形成钝化层。钝化层在蚀刻期间保护栅极堆叠的侧壁以产生更直的栅叠层。

4. 发明申请

US20090104776A1 METHODS FOR FORMING NESTED AND ISOLATED LINES IN SEMICONDUCTOR DEVICES 审中-公开
标题翻译：在半导体器件中形成嵌套和隔离线的方法
公开(公告)号：US20090104776A1
公开(公告)日：2009-04-23
申请号：US11874392
申请日：2007-10-18
申请人： David M. Dobuzinsky , Johnathan E. Faltermeier , Naoyoshi Kusaba , Joyce C. Liu , Munir D. Naeem , Siddhartha Panda , Richard S. Wise , Hongwen Yan
发明人： David M. Dobuzinsky , Johnathan E. Faltermeier , Naoyoshi Kusaba , Joyce C. Liu , Munir D. Naeem , Siddhartha Panda , Richard S. Wise , Hongwen Yan
IPC分类号： H01L21/4763
CPC分类号： H01L21/76838 , H01L21/0337 , H01L21/0338 , H01L21/32137 , H01L21/32139
摘要： A method for forming lines for semiconductor devices including, depositing a shallow trench isolation (STI) film stack on a silicon substrate, depositing a layer of polysilicon on the STI film stack, depositing a layer of antireflective coating on the layer of polysilicon, developing a phototoresist on the antireflective coating, wherein the photoresist defines a line, etching the layer of antireflective coating and the layer of polysilicon using RIE with a low bias power, removing the photoresist, removing the layer of antireflective coating, etching the STI film stack to form the line, wherein the layer of polysilicon further defines the line.
摘要翻译：一种用于形成用于半导体器件的线的方法，包括：在硅衬底上沉积浅沟槽隔离（STI）膜堆叠，在所述STI膜堆叠上沉积多晶硅层，在所述多晶硅层上沉积一层抗反射涂层，在抗反射涂层上光致抗蚀剂，其中光致抗蚀剂限定线，使用具有低偏压功率的RIE蚀刻抗反射涂层和多晶硅层，去除光致抗蚀剂，去除抗反射涂层，蚀刻STI膜叠层以形成所述线，其中所述多晶硅层进一步限定所述线。

5. 发明授权

US07077903B2 Etch selectivity enhancement for tunable etch resistant anti-reflective layer 失效
标题翻译：可蚀刻耐腐蚀抗反射层的蚀刻选择性增强
公开(公告)号：US07077903B2
公开(公告)日：2006-07-18
申请号：US10705577
申请日：2003-11-10
申请人： Katherina E. Babich , Scott D. Halle , David V. Horak , Arpan P. Mahorowala , Wesley C. Natzle , Dirk Pfeiffer , Hongwen Yan
发明人： Katherina E. Babich , Scott D. Halle , David V. Horak , Arpan P. Mahorowala , Wesley C. Natzle , Dirk Pfeiffer , Hongwen Yan
IPC分类号： C30B25/02
CPC分类号： H01L21/0275 , H01L21/31144 , H01L21/32139 , Y10T428/24843
摘要： Methods for generating a nanostructure and for enhancing etch selectivity, and a nanostructure are disclosed. The invention implements a tunable etch-resistant anti-reflective (TERA) material integration scheme which gives high etch selectivity for both etching pattern transfer through the TERA layer (used as an ARC and/or hardmask) with etch selectivity to the patterned photoresist, and etching to pattern transfer through a dielectric layer of nitride. This is accomplished by oxidizing a TERA layer after etching pattern transfer through the TERA layer to form an oxidized TERA layer having chemical properties similar to oxide. The methods provide all of the advantages of the TERA material and allows for high etch selectivity (approximately 5–10:1) for etching to pattern transfer through nitride. In addition, the methodology reduces LER and allows for trimming despite reduced photoresist thickness.
摘要翻译：公开了产生纳米结构和提高蚀刻选择性的方法，以及纳米结构。本发明实现了可调谐抗蚀抗反射（TERA）材料集成方案，其对蚀刻图案转移通过TERA层（用作ARC和/或硬掩模）提供了高蚀刻选择性，具有对图案化光致抗蚀剂的蚀刻选择性，以及蚀刻到通过氮化物的介电层的图案转移。这是通过在通过TERA层蚀刻图案转移之后氧化TERA层来实现的，以形成具有与氧化物相似的化学性质的氧化TERA层。这些方法提供了TERA材料的所有优点，并且允许高蚀刻选择性（约5-10:1）蚀刻到通过氮化物的图案转移。此外，该方法减少LER，并允许尽管减少光致抗蚀剂厚度的修剪。

6. 发明申请

US20080194112A1 METHOD AND SYSTEM FOR PLASMA ETCHING HAVING IMPROVED ACROSS-WAFER ETCH UNIFORMITY 审中-公开
标题翻译：等离子体蚀刻的方法和系统具有改进的跨越蚀刻均匀性
公开(公告)号：US20080194112A1
公开(公告)日：2008-08-14
申请号：US11673128
申请日：2007-02-09
申请人： Qingyun Yang , Joyce C. Liu , Hongwen Yan , Ying Zhang
发明人： Qingyun Yang , Joyce C. Liu , Hongwen Yan , Ying Zhang
IPC分类号： H01L21/3065
CPC分类号： H01L21/32136 , H01L21/32137 , H01L21/6708
摘要： A method for improving across-wafer etch uniformity of semiconductor devices in an etching chamber, wherein the method includes: introducing a first flow of gas mixtures from a central gas distribution plate manifold; introducing a second flow of gas mixtures from an auxiliary gas feed; and controlling process parameters including one or more of: duration, power, pressure, and gas flow rates for the first and second flow of gas mixtures; wherein the central gas distribution plate manifold is positioned above the semiconductor wafer; wherein the auxiliary gas feed is positioned around the perimeter of the semiconductor wafer; and wherein the controlling of the process parameters of the central gas distribution plate manifold and the auxiliary gas feed is facilitated by independent controls.
摘要翻译：一种用于改善蚀刻室中的半导体器件的跨晶片蚀刻均匀性的方法，其中所述方法包括：从中央气体分配板歧管引入第一气体混合物流; 从辅助气体进料引入第二气体混合物流; 以及控制过程参数，包括以下一个或多个：气体混合物的第一和第二流动的持续时间，功率，压力和气体流速; 其中所述中央气体分配板歧管位于所述半导体晶片的上方; 其中所述辅助气体进料围绕所述半导体晶片的周边定位; 并且其中通过独立控制来促进对中央气体分配板歧管和辅助气体进料的工艺参数的控制。

7. 发明授权

US07081393B2 Reduced dielectric constant spacer materials integration for high speed logic gates 失效
标题翻译：降低介电常数间隔材料集成用于高速逻辑门
公开(公告)号：US07081393B2
公开(公告)日：2006-07-25
申请号：US10709652
申请日：2004-05-20
申请人： Michael P. Belyansky , Joyce C. Liu , Hsing Jen Wann , Richard Stephen Wise , Hongwen Yan
发明人： Michael P. Belyansky , Joyce C. Liu , Hsing Jen Wann , Richard Stephen Wise , Hongwen Yan
IPC分类号： H01L21/336
CPC分类号： H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： An FET transistor has a gate disposed between a source and a drain; a gate dielectric layer disposed underneath the gate; and a spacer on a side of the gate. The gate dielectric layer is conventional oxide and the spacer has a reduced dielectric constant (k). The reduced dielectric constant (k) may be less than 3.85, or it may be less than 7.0 (˜nitride), but greater than 3.85 (˜oxide). Preferably, the spacer comprises a material which can be etched selectively to the gate dielectric layer. The spacer may be porous, and a thin layer is deposited on the porous spacer to prevent moisture absorption. The spacer may comprise a material selected from the group consisting of Black Diamond, Coral, TERA and Blok type materials. Pores may be formed in the spacer material by exposing the spacers to an oxygen plasma.
摘要翻译： FET晶体管具有设置在源极和漏极之间的栅极; 设置在栅极下方的栅介质层; 和在门侧的间隔物。栅极电介质层是常规的氧化物，间隔物具有降低的介电常数（k）。降低的介电常数（k）可以小于3.85，或者可以小于7.0（〜氮化物），但大于3.85（〜氧化物）。优选地，间隔物包括可以选择性地蚀刻到栅极介电层的材料。间隔物可以是多孔的，并且在多孔间隔物上沉积薄层以防止吸湿。间隔物可以包括选自黑钻石，珊瑚，TERA和Blok型材料的材料。可以通过将间隔物暴露于氧等离子体来在间隔物材料中形成孔。

8. 发明申请

US20080182372A1 METHOD OF FORMING DISPOSABLE SPACERS FOR IMPROVED STRESSED NITRIDE FILM EFFECTIVENESS 审中-公开
标题翻译：形成改善间隔物的方法，用于改善耐压氮化膜的有效性
公开(公告)号：US20080182372A1
公开(公告)日：2008-07-31
申请号：US11669645
申请日：2007-01-31
申请人： Joyce C. Liu , Hongwen Yan , Qingyun Yang , Ying Zhang
发明人： Joyce C. Liu , Hongwen Yan , Qingyun Yang , Ying Zhang
IPC分类号： H01L21/8238
CPC分类号： H01L29/6653 , H01L21/3146 , H01L21/823864 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/7843
摘要： A method of forming a complementary metal oxide semiconductor (CMOS) device includes forming an oxide layer on sidewalls and a top surface of a patterned gate conductor, and on sidewalls of a gate insulating layer formed on a semiconductor substrate; forming a first carbon-based layer over the gate conductor, gate insulating layer, and substrate; etching the first carbon-based layer so as to create a first set of carbon spacers; forming a second carbon-based layer over the gate conductor, gate insulating layer, substrate, and first set of carbon spacers; etching the second carbon-based layer so as to create a second set of carbon spacers; forming silicide contacts on the gate conductor, and on source and drain regions formed in the substrate; removing the first and second sets of carbon spacers; and forming a stress-inducing nitride layer over the substrate, silicide contacts, gate conductor, and gate insulating layer.
摘要翻译：形成互补金属氧化物半导体（CMOS）器件的方法包括在图案化栅极导体的侧壁和顶表面上以及形成在半导体衬底上的栅极绝缘层的侧壁上形成氧化物层; 在栅极导体，栅极绝缘层和衬底上形成第一碳基层; 蚀刻第一碳基层以产生第一组碳间隔物; 在栅极导体，栅极绝缘层，衬底和第一组碳隔离物上形成第二碳基层; 蚀刻第二碳基层以产生第二组碳间隔物; 在栅极导体上形成硅化物触点，以及在衬底中形成的源极和漏极区上; 去除第一和第二组碳间隔物; 以及在衬底上形成应力诱导氮化物层，硅化物接触，栅极导体和栅极绝缘层。

9. 发明授权

US07329602B2 Wiring structure for integrated circuit with reduced intralevel capacitance 有权
标题翻译：具有降低的体积电容的集成电路的接线结构
公开(公告)号：US07329602B2
公开(公告)日：2008-02-12
申请号：US11203944
申请日：2005-08-15
申请人： Richard S. Wise , Bomy A. Chen , Mark C. Hakey , Hongwen Yan
发明人： Richard S. Wise , Bomy A. Chen , Mark C. Hakey , Hongwen Yan
IPC分类号： H01L21/4763
CPC分类号： H01L23/5222 , H01L21/7682 , H01L23/53295 , H01L2221/1057 , H01L2924/0002 , H01L2924/00
摘要： A method of forming a wiring structure for an integrated circuit includes the steps of forming a plurality of features in a layer of dielectric material, and forming spacers on sidewalls of the features. Conductors are then formed in the features, being separated from the sidewalls by the spacers. The spacers are then removed, forming air gaps at the sidewalls so that the conductors are separated from the sidewalls by the air gaps. Dielectric layers above and below the conductors may be low-k dielectrics having a dielectric constant less than that of the dielectric between the conductors. A cross-section of each of the conductors has a bottom in contact with the a low-k dielectric layer, a top in contact with another low-k dielectric, and sides in contact only with the air gaps. The air gaps serve to reduce the intralevel capacitance.
摘要翻译：形成用于集成电路的布线结构的方法包括以下步骤：在介电材料层中形成多个特征，以及在特征的侧壁上形成间隔物。然后在特征中形成导体，通过间隔件与侧壁分离。然后去除间隔物，在侧壁处形成气隙，使得导体通过气隙与侧壁分离。导体之上和之下的介电层可以是具有比导体之间的电介质的介电常数小的介电常数的低k电介质。每个导体的横截面具有与低k电介质层接触的底部，与另一低k电介质接触的顶部和仅与气隙接触的侧面。气隙用于降低电容值。

10. 发明授权

US08193099B1 Protecting exposed metal gate structures from etching processes in integrated circuit manufacturing 有权
标题翻译：保护暴露的金属栅极结构免受集成电路制造中的蚀刻工艺
公开(公告)号：US08193099B1
公开(公告)日：2012-06-05
申请号：US13049933
申请日：2011-03-17
申请人： Mukesh V. Khare , Renee T. Mo , Ravikumar Ramachandran , Richard S. Wise , Hongwen Yan
发明人： Mukesh V. Khare , Renee T. Mo , Ravikumar Ramachandran , Richard S. Wise , Hongwen Yan
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： H01L21/32136 , H01L21/823437 , H01L21/823481 , H01L21/823828 , H01L21/823878
摘要： A method of forming a semiconductor device includes forming a transistor gate stack over a substrate having an active area and a shallow trench isolation (STI) region. First sidewall spacers are formed on the transistor gate stack, and an isotropic etch process is applied to isotropically remove an excess portion of a metal layer included within the transistor gate stack, the excess portion left unprotected by the first sidewall spacers. Second sidewall spacers are formed on the transistor gate stack, the second sidewall spacers completely encapsulating the metal layer of the transistor gate stack.
摘要翻译：形成半导体器件的方法包括在具有有源区和浅沟槽隔离（STI）区的衬底上形成晶体管栅叠。第一侧壁间隔物形成在晶体管栅极堆叠上，并且各向同性蚀刻工艺被应用于各向同性地去除包括在晶体管栅极叠层内的金属层的过剩部分，剩余部分未被第一侧壁间隔物保护。第二侧壁间隔物形成在晶体管栅极叠层上，第二侧壁间隔物完全封装晶体管栅极叠层的金属层。

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