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1. 发明申请

US20080182372A1 METHOD OF FORMING DISPOSABLE SPACERS FOR IMPROVED STRESSED NITRIDE FILM EFFECTIVENESS 审中-公开
标题翻译：形成改善间隔物的方法，用于改善耐压氮化膜的有效性
公开(公告)号：US20080182372A1
公开(公告)日：2008-07-31
申请号：US11669645
申请日：2007-01-31
申请人： Joyce C. Liu , Hongwen Yan , Qingyun Yang , Ying Zhang
发明人： Joyce C. Liu , Hongwen Yan , Qingyun Yang , Ying Zhang
IPC分类号： H01L21/8238
CPC分类号： H01L29/6653 , H01L21/3146 , H01L21/823864 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/7843
摘要： A method of forming a complementary metal oxide semiconductor (CMOS) device includes forming an oxide layer on sidewalls and a top surface of a patterned gate conductor, and on sidewalls of a gate insulating layer formed on a semiconductor substrate; forming a first carbon-based layer over the gate conductor, gate insulating layer, and substrate; etching the first carbon-based layer so as to create a first set of carbon spacers; forming a second carbon-based layer over the gate conductor, gate insulating layer, substrate, and first set of carbon spacers; etching the second carbon-based layer so as to create a second set of carbon spacers; forming silicide contacts on the gate conductor, and on source and drain regions formed in the substrate; removing the first and second sets of carbon spacers; and forming a stress-inducing nitride layer over the substrate, silicide contacts, gate conductor, and gate insulating layer.
摘要翻译：形成互补金属氧化物半导体（CMOS）器件的方法包括在图案化栅极导体的侧壁和顶表面上以及形成在半导体衬底上的栅极绝缘层的侧壁上形成氧化物层; 在栅极导体，栅极绝缘层和衬底上形成第一碳基层; 蚀刻第一碳基层以产生第一组碳间隔物; 在栅极导体，栅极绝缘层，衬底和第一组碳隔离物上形成第二碳基层; 蚀刻第二碳基层以产生第二组碳间隔物; 在栅极导体上形成硅化物触点，以及在衬底中形成的源极和漏极区上; 去除第一和第二组碳间隔物; 以及在衬底上形成应力诱导氮化物层，硅化物接触，栅极导体和栅极绝缘层。

2. 发明申请

US20080194112A1 METHOD AND SYSTEM FOR PLASMA ETCHING HAVING IMPROVED ACROSS-WAFER ETCH UNIFORMITY 审中-公开
标题翻译：等离子体蚀刻的方法和系统具有改进的跨越蚀刻均匀性
公开(公告)号：US20080194112A1
公开(公告)日：2008-08-14
申请号：US11673128
申请日：2007-02-09
申请人： Qingyun Yang , Joyce C. Liu , Hongwen Yan , Ying Zhang
发明人： Qingyun Yang , Joyce C. Liu , Hongwen Yan , Ying Zhang
IPC分类号： H01L21/3065
CPC分类号： H01L21/32136 , H01L21/32137 , H01L21/6708
摘要： A method for improving across-wafer etch uniformity of semiconductor devices in an etching chamber, wherein the method includes: introducing a first flow of gas mixtures from a central gas distribution plate manifold; introducing a second flow of gas mixtures from an auxiliary gas feed; and controlling process parameters including one or more of: duration, power, pressure, and gas flow rates for the first and second flow of gas mixtures; wherein the central gas distribution plate manifold is positioned above the semiconductor wafer; wherein the auxiliary gas feed is positioned around the perimeter of the semiconductor wafer; and wherein the controlling of the process parameters of the central gas distribution plate manifold and the auxiliary gas feed is facilitated by independent controls.
摘要翻译：一种用于改善蚀刻室中的半导体器件的跨晶片蚀刻均匀性的方法，其中所述方法包括：从中央气体分配板歧管引入第一气体混合物流; 从辅助气体进料引入第二气体混合物流; 以及控制过程参数，包括以下一个或多个：气体混合物的第一和第二流动的持续时间，功率，压力和气体流速; 其中所述中央气体分配板歧管位于所述半导体晶片的上方; 其中所述辅助气体进料围绕所述半导体晶片的周边定位; 并且其中通过独立控制来促进对中央气体分配板歧管和辅助气体进料的工艺参数的控制。

3. 发明授权

US08481389B2 Method of removing high-K dielectric layer on sidewalls of gate structure 有权
标题翻译：去除栅极结构侧壁上的高K电介质层的方法
公开(公告)号：US08481389B2
公开(公告)日：2013-07-09
申请号：US13080084
申请日：2011-04-05
申请人： Ying Zhang , Qingyun Yang , Hongwen Yan
发明人： Ying Zhang , Qingyun Yang , Hongwen Yan
IPC分类号： H01L21/336
CPC分类号： H01L29/7833 , H01L21/26586 , H01L21/823462 , H01L21/823857 , H01L29/4966 , H01L29/517 , H01L29/66545 , H01L29/6659
摘要： A semiconductor structure, and method of forming a semiconductor structure, that includes a gate structure on a semiconductor substrate, in which the gate structure includes a gate conductor and a high-k gate dielectric layer. The high-k gate dielectric layer is in contact with the base of the gate conductor and is present on the sidewalls of the gate conductor for a dimension that is less than ¼ the gate structure's height. The semiconductor structure also includes source regions and drain regions present in the semiconductor substrate on opposing sides of the gate structure.
摘要翻译：一种半导体结构，以及形成半导体结构的方法，其包括半导体衬底上的栅极结构，其中栅极结构包括栅极导体和高k栅极电介质层。高k栅极电介质层与栅极导体的基极接触并且存在于栅极导体的侧壁上，尺寸小于栅极结构的高度的1/4。半导体结构还包括在栅极结构的相对侧上存在于半导体衬底中的源极区和漏极区。

4. 发明授权

US07435652B1 Integration schemes for fabricating polysilicon gate MOSFET and high-K dielectric metal gate MOSFET 有权
标题翻译：用于制造多晶硅栅极MOSFET和高K介质金属栅极MOSFET的集成方案
公开(公告)号：US07435652B1
公开(公告)日：2008-10-14
申请号：US11694104
申请日：2007-03-30
申请人： Tze-chiang Chen , Bruce B. Doris , Rangarajan Jagannathan , Hongwen Yan , Qingyun Yang , Ying Zhang
发明人： Tze-chiang Chen , Bruce B. Doris , Rangarajan Jagannathan , Hongwen Yan , Qingyun Yang , Ying Zhang
IPC分类号： H01L21/336
CPC分类号： H01L29/4966 , H01L21/28194 , H01L21/82345 , H01L21/823462 , H01L21/823842 , H01L21/823857 , H01L29/517
摘要： Multiple integration schemes for manufacturing dual gate semiconductor structures are disclosed. By employing the novel integration schemes, polysilicon gate MOSFETs and high-k dielectric metal gate MOSFETs are formed on the same semiconductor substrate despite differences in the composition of the gate stack and resulting differences in the etch rates. A thin polysilicon layer is used for one type of gate electrodes and a silicon-containing layer are used for the other type of gate electrodes in these integration schemes to balance the different etch rates and to enable etching of the two different gate stacks.
摘要翻译：公开了用于制造双栅极半导体结构的多重集成方案。通过采用新颖的集成方案，尽管栅极堆叠的组成差异以及蚀刻速率的差异，但是在同一半导体衬底上形成多晶硅栅极MOSFET和高k介质金属栅极MOSFET。对于一种类型的栅电极使用薄多晶硅层，并且在这些集成方案中使用含硅层用于其他类型的栅电极，以平衡不同的蚀刻速率并且能够蚀刻两个不同的栅极堆叠。

5. 发明申请

US20080242070A1 INTEGRATION SCHEMES FOR FABRICATING POLYSILICON GATE MOSFET AND HIGH-K DIELECTRIC METAL GATE MOSFET 有权
标题翻译：用于制造多晶硅栅极MOSFET和高K介电金属栅极MOSFET的集成方案
公开(公告)号：US20080242070A1
公开(公告)日：2008-10-02
申请号：US11694104
申请日：2007-03-30
申请人： Tze-chiang Chen , Bruce B. Doris , Rangarajan Jagannathan , Hongwen Yan , Qingyun Yang , Ying Zhang
发明人： Tze-chiang Chen , Bruce B. Doris , Rangarajan Jagannathan , Hongwen Yan , Qingyun Yang , Ying Zhang
IPC分类号： H01L21/3205
CPC分类号： H01L29/4966 , H01L21/28194 , H01L21/82345 , H01L21/823462 , H01L21/823842 , H01L21/823857 , H01L29/517
摘要： Multiple integration schemes for manufacturing dual gate semiconductor structures are disclosed. By employing the novel integration schemes, polysilicon gate MOSFETs and high-k dielectric metal gate MOSFETs are formed on the same semiconductor substrate despite differences in the composition of the gate stack and resulting differences in the etch rates. A thin polysilicon layer is used for one type of gate electrodes and a silicon-containing layer are used for the other type of gate electrodes in these integration schemes to balance the different etch rates and to enable etching of the two different gate stacks.
摘要翻译：公开了用于制造双栅极半导体结构的多重集成方案。通过采用新颖的集成方案，尽管栅极堆叠的组成差异以及蚀刻速率的差异，但是在同一半导体衬底上形成多晶硅栅极MOSFET和高k介质金属栅极MOSFET。对于一种类型的栅电极使用薄多晶硅层，并且在这些集成方案中使用含硅层用于其他类型的栅电极，以平衡不同的蚀刻速率并且能够蚀刻两个不同的栅极堆叠。

6. 发明申请

US20120256278A1 Method of Removing High-K Dielectric Layer on Sidewalls of Gate Structure 有权
标题翻译：去除栅极结构侧壁上高K电介质层的方法
公开(公告)号：US20120256278A1
公开(公告)日：2012-10-11
申请号：US13080084
申请日：2011-04-05
申请人： Ying Zhang , Qingyun Yang , Hongwen Yan
发明人： Ying Zhang , Qingyun Yang , Hongwen Yan
IPC分类号： H01L29/772 , H01L21/28
CPC分类号： H01L29/7833 , H01L21/26586 , H01L21/823462 , H01L21/823857 , H01L29/4966 , H01L29/517 , H01L29/66545 , H01L29/6659
摘要： A semiconductor structure, and method of forming a semiconductor structure, that includes a gate structure on a semiconductor substrate, in which the gate structure includes a gate conductor and a high-k gate dielectric layer. The high-k gate dielectric layer is in contact with the base of the gate conductor and is present on the sidewalls of the gate conductor for a dimension that is less than ¼ the gate structure's height. The semiconductor structure also includes source regions and drain regions present in the semiconductor substrate on opposing sides of the gate structure.
摘要翻译：一种半导体结构，以及形成半导体结构的方法，其包括半导体衬底上的栅极结构，其中栅极结构包括栅极导体和高k栅极电介质层。高k栅极电介质层与栅极导体的基极接触并且存在于栅极导体的侧壁上，尺寸小于栅极结构的高度的1/4。半导体结构还包括在栅极结构的相对侧上存在于半导体衬底中的源极区和漏极区。

7. 发明申请

US20080280404A1 RESIDUE FREE PATTERNED LAYER FORMATION METHOD APPLICABLE TO CMOS STRUCTURES 有权
标题翻译：适用于CMOS结构的残留层形成方法
公开(公告)号：US20080280404A1
公开(公告)日：2008-11-13
申请号：US11746759
申请日：2007-05-10
申请人： Michael Chudzik , Bruce B. Doris , William K. Henson , Hongwen Yan , Ying Zhang
发明人： Michael Chudzik , Bruce B. Doris , William K. Henson , Hongwen Yan , Ying Zhang
IPC分类号： H01L21/28 , H01L21/02 , H01L21/311
CPC分类号： H01L29/045 , H01L21/28079 , H01L21/28088 , H01L21/28097 , H01L21/31138 , H01L21/32137 , H01L21/32139 , H01L21/823842 , H01L21/823857 , H01L21/84
摘要： A method for forming a microelectronic structure uses a mask layer located over a target layer. The target layer may be etched while using the mask layer as an etch mask to form an end tapered target layer from the target layer. An additional target layer may be formed over the end tapered target layer and masked with an additional mask layer. The additional target layer may be etched to form a patterned additional target layer separated from the end tapered target layer and absent an additional target layer residue adjacent the end tapered target layer. The method is useful for fabricating CMOS structures including nFET and pFET gate electrodes comprising different NFET and pFET gate electrode materials.
摘要翻译：形成微电子结构的方法使用位于目标层上的掩模层。可以使用掩模层作为蚀刻掩模来蚀刻目标层，以从目标层形成端部锥形目标层。可以在端部锥形目标层上形成另外的目标层，并用附加掩模层掩模。可以蚀刻附加目标层以形成与端部锥形目标层分离的图案化附加目标层，并且不存在与端部锥形目标层相邻的附加靶层残余物。该方法对于制造包括nFET和pFET栅电极的CMOS结构是有用的，其包括不同的NFET和pFET栅电极材料。

8. 发明申请

US20120142181A1 CMOS STRUCTURE AND METHOD FOR FABRICATION THEREOF USING MULTIPLE CRYSTALLOGRAPHIC ORIENTATIONS AND GATE MATERIALS 失效
标题翻译： CMOS结构及其使用多种晶体取向和栅极材料制造的方法
公开(公告)号：US20120142181A1
公开(公告)日：2012-06-07
申请号：US13369707
申请日：2012-02-09
申请人： Tze-Chiang Chen , Meikei Ieong , Rajarao Jammy , Mukesh V. Khare , Chun-yung Sung , Richard Wise , Hongwen Yan , Ying Zhang
发明人： Tze-Chiang Chen , Meikei Ieong , Rajarao Jammy , Mukesh V. Khare , Chun-yung Sung , Richard Wise , Hongwen Yan , Ying Zhang
IPC分类号： H01L21/28
CPC分类号： H01L21/28079 , H01L21/823807 , H01L21/823842 , H01L21/823878 , H01L21/84 , H01L27/1203 , H01L29/045 , H01L29/6659
摘要： Methods for fabricating a CMOS structure use a first gate stack located over a first orientation region of a semiconductor substrate. A second gate material layer is located over the first gate stack and a laterally adjacent second orientation region of the semiconductor substrate. A planarizing layer is located upon the second gate material layer. The planarizing layer and the second gate material layer are non-selectively etched to form a second gate stack that approximates the height of the first gate stack. An etch stop layer may also be formed upon the first gate stack. The resulting CMOS structure may comprise different gate dielectrics, metal gates and silicon gates.
摘要翻译：制造CMOS结构的方法使用位于半导体衬底的第一取向区域上方的第一栅极堆叠。第二栅极材料层位于第一栅极叠层上方和半导体衬底的横向相邻的第二取向区域上。平坦化层位于第二栅极材料层上。平面化层和第二栅极材料层被非选择性蚀刻以形成近似第一栅极堆叠的高度的第二栅极堆叠。也可以在第一栅极叠层上形成蚀刻停止层。所得到的CMOS结构可以包括不同的栅极电介质，金属栅极和硅栅极。

9. 发明授权

US08158481B2 CMOS structure and method for fabrication thereof using multiple crystallographic orientations and gate materials 有权
标题翻译： CMOS结构及其制造方法，使用多个晶体取向和栅极材料
公开(公告)号：US08158481B2
公开(公告)日：2012-04-17
申请号：US12683535
申请日：2010-01-07
申请人： Tze-Chiang Chen , Meikei Ieong , Rajarao Jammy , Mukesh V. Khare , Chun-yung Sung , Richard Wise , Hongwen Yan , Ying Zhang
发明人： Tze-Chiang Chen , Meikei Ieong , Rajarao Jammy , Mukesh V. Khare , Chun-yung Sung , Richard Wise , Hongwen Yan , Ying Zhang
IPC分类号： H01L21/8234
CPC分类号： H01L21/28079 , H01L21/823807 , H01L21/823842 , H01L21/823878 , H01L21/84 , H01L27/1203 , H01L29/045 , H01L29/6659
摘要： Methods for fabricating a CMOS structure use a first gate stack located over a first orientation region of a semiconductor substrate. A second gate material layer is located over the first gate stack and a laterally adjacent second orientation region of the semiconductor substrate. A planarizing layer is located upon the second gate material layer. The planarizing layer and the second gate material layer are non-selectively etched to form a second gate stack that approximates the height of the first gate stack. An etch stop layer may also be formed upon the first gate stack. The resulting CMOS structure may comprise different gate dielectrics, metal gates and silicon gates.
摘要翻译：制造CMOS结构的方法使用位于半导体衬底的第一取向区域上方的第一栅极堆叠。第二栅极材料层位于第一栅极叠层上方和半导体衬底的横向相邻的第二取向区域上。平坦化层位于第二栅极材料层上。平面化层和第二栅极材料层被非选择性蚀刻以形成近似第一栅极堆叠的高度的第二栅极堆叠。也可以在第一栅极叠层上形成蚀刻停止层。所得到的CMOS结构可以包括不同的栅极电介质，金属栅极和硅栅极。

10. 发明申请

US20080224238A1 ADVANCED HIGH-k GATE STACK PATTERNING AND STRUCTURE CONTAINING A PATTERNED HIGH-k GATE STACK 有权
标题翻译：先进的高k栅格堆叠图案和结构包含一个图案高k门板堆叠
公开(公告)号：US20080224238A1
公开(公告)日：2008-09-18
申请号：US11685558
申请日：2007-03-13
申请人： Siva Kanakasabapathy , Ying Zhang , Edmund M. Sikorski , Hongwen Yan , Vijay Narayanan , Vamsi K. Paruchuri , Bruce B. Doris
发明人： Siva Kanakasabapathy , Ying Zhang , Edmund M. Sikorski , Hongwen Yan , Vijay Narayanan , Vamsi K. Paruchuri , Bruce B. Doris
IPC分类号： H01L29/76 , H01L21/302
CPC分类号： H01L21/31111 , H01L21/28088 , H01L21/31144 , H01L21/31645 , H01L21/823807 , H01L21/823828 , H01L29/045 , H01L29/4966 , H01L29/513 , H01L29/517
摘要： An advanced method of patterning a gate stack including a high-k gate dielectric that is capped with a high-k gate dielectric capping layer such as, for example, a rare earth metal (or rare earth like)-containing layer is provided. In particular, the present invention provides a method in which a combination of wet and dry etching is used in patterning such gate stacks which substantially reduces the amount of remnant high-k gate dielectric capping material remaining on the surface of a semiconductor substrate to a value that is less than 1010 atoms/cm2, preferably less than about 109 atoms/cm2.
摘要翻译：提供了一种构图栅极堆叠的先进方法，该栅极堆叠包括用例如含有稀土金属（或稀土类））层的高k栅介质覆盖层封盖的高k栅极电介质。特别地，本发明提供了一种方法，其中使用湿蚀刻和干蚀刻的组合来构图这样的栅极堆叠，其将残留在半导体衬底的表面上的剩余的高k栅极电介质封盖材料的量基本上减小到值小于10 10原子/ cm 2，优选小于约10 9原子/ cm 2。

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