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1. 发明授权

US5381148A Method and apparatus for calibrating a gain control circuit 失效
标题翻译：用于校准增益控制电路的方法和装置
公开(公告)号：US5381148A
公开(公告)日：1995-01-10
申请号：US90799
申请日：1993-07-12
申请人： Michael Mueck , Paul F. Ferguson, Jr.
发明人： Michael Mueck , Paul F. Ferguson, Jr.
IPC分类号： H03M1/70 , H03F3/34 , H03G1/04 , H03G3/02 , H03M1/10 , H03M1/66 , H03M3/02
CPC分类号： H03G1/04 , H03M1/1019 , H03M3/38 , H03M1/66 , H03M3/51
摘要： A system includes a digital-to-analog converter circuit and a calibration circuit. The digital-to-analog converter circuit includes a gain control circuit providing volume adjustment. The system includes a calibration mode and a normal mode of operation. During calibration, a correction value associated with the gain control circuit is measured by the calibration circuit and stored. During normal operation, the stored correction value is combined with the input before provision of the same to the DAC circuit such that, for a predetermined input of midscale code, the desired system output remains constant despite any change in the volume setting of the gain control circuit.
摘要翻译：系统包括数模转换器电路和校准电路。数模转换器电路包括提供音量调节的增益控制电路。该系统包括校准模式和正常操作模式。在校准期间，与增益控制电路相关联的校正值由校准电路测量并存储。在正常操作期间，将存储的校正值与其提供给DAC电路之前的输入组合，使得对于预定的中间码的输入，期望的系统输出保持恒定，尽管增益控制的音量设置有任何改变电路。

2. 发明授权

US5789974A Calibrating the DC-offset of amplifiers 失效
标题翻译：校准放大器的直流偏移
公开(公告)号：US5789974A
公开(公告)日：1998-08-04
申请号：US682102
申请日：1996-07-17
申请人： Paul F. Ferguson, Jr. , Gangadhar Burra , Michael Mueck
发明人： Paul F. Ferguson, Jr. , Gangadhar Burra , Michael Mueck
IPC分类号： H03F1/30 , H03F3/45 , H03F1/02
CPC分类号： H03F3/45475 , H03F1/304 , H03F3/45968 , H03F2200/375 , H03F2203/45048
摘要： The dc-offset voltage of an amplifier is calibrated by: (1) configuring the amplifier as a comparator, (2) using the output of the comparator to drive the up/down select input of an up/down counter, and (3) using the output count of the up/down counter to control: (a) a dc-offset correction voltage being: (i) applied across the inputs of the amplifier, or (ii) being used to adjust a voltage which controls an operating parameter of a device in the amplifier, or (b) switches which selectively adjust the effective size or operating conditions of a transistor or other device such that the dc-offset voltage of the amplifier is adjusted corresponding to the value of the output count. At the end of a calibration cycle, the output count of the up/down counter is maintained and is used to: (a) control a voltage which is applied permanently in series with one of the inputs of the amplifier or to an operating parameter control lead of a device in the amplifier, or (b) maintain the position of switches used to adjust the effective size or operating conditions of the transistor or other device in the amplifier to compensate for the offset voltage thereof.
摘要翻译：放大器的直流偏移电压通过以下方式进行校准：（1）将放大器配置为比较器，（2）使用比较器的输出驱动升/降计数器的上/下选择输入，（3）使用上/下计数器的输出计数来控制：（a）直流偏移校正电压：（i）施加在放大器的输入端，或（ii）用于调节控制工作参数的电压的放大器中的器件，或（b）选择性地调节晶体管或其他器件的有效尺寸或工作条件的开关，使得根据输出计数值调节放大器的直流偏移电压。在校准周期结束时，保持升/减计数器的输出计数，并用于：（a）控制与放大器的输入之一永久地施加的电压或者操作参数控制放大器中的器件的引线，或（b）保持用于调整放大器中的晶体管或其他器件的有效尺寸或工作条件的开关的位置，以补偿其偏移电压。

3. 发明授权

US08570200B2 Continuous-time oversampled converter having enhanced immunity to noise 有权
标题翻译：连续时间过采样转换器具有增强的抗噪声能力
公开(公告)号：US08570200B2
公开(公告)日：2013-10-29
申请号：US13337143
申请日：2011-12-25
申请人： Michael A. Ashburn, Jr. , Jeffrey Carl Gealow , Paul F. Ferguson, Jr.
发明人： Michael A. Ashburn, Jr. , Jeffrey Carl Gealow , Paul F. Ferguson, Jr.
IPC分类号： H03M3/00
CPC分类号： H03M3/344 , H03M3/50 , H03M7/304
摘要： An apparatus includes a clock source and an oversampled continuous-time digital-to-analog converter. Noise signal is added to the clock signal as the clock signal is generated and/or routed. The oversampled continuous-time digital-to-analog converter includes a sigma-delta modulator to perform noise shaping on input data samples and provide intermediate data samples; a filter to filter the intermediate data samples and generate filtered samples, the filter having a transfer function that has a stop band at a frequency range that includes the frequency of the noise signal or a component of the noise signal; and a continuous-time digital-to-analog converter to convert the filtered samples to an output analog signal.
摘要翻译：一种装置包括时钟源和过采样连续时间数模转换器。随着时钟信号的产生和/或路由，噪声信号被添加到时钟信号。过采样连续时间数模转换器包括一个Σ-Δ调制器，用于对输入数据采样进行噪声整形，并提供中间数据采样; 滤波器，用于对中间数据样本进行滤波并生成滤波后的样本，该滤波器具有在包括噪声信号的频率或噪声信号的分量的频率范围内具有阻带的传递函数; 以及连续数字模拟转换器，用于将滤波后的样本转换为输出模拟信号。

4. 发明授权

US07199740B1 Method and apparatus for use in switched capacitor systems 有权
标题翻译：用于开关电容器系统的方法和装置
公开(公告)号：US07199740B1
公开(公告)日：2007-04-03
申请号：US09575560
申请日：2000-05-21
申请人： Paul F. Ferguson, Jr. , Xavier S. Haurie
发明人： Paul F. Ferguson, Jr. , Xavier S. Haurie
IPC分类号： H03M1/66
CPC分类号： H03M1/806
摘要： A system and method including a DAC that receives a multi-bit digital signal and outputs at least two analog signals including a first analog signal and a second analog signal, the first analog signal being indicative of a sum of values of bits in the multi-bit digital signal, the second analog signal also being indicative of said sum of values of said bits in the multi-bit digital signal. The first and second analog signals may be substantially equal or they may be different from each other.
摘要翻译：一种包括DAC的系统和方法，所述DAC接收多位数字信号并输出包括第一模拟信号和第二模拟信号的至少两个模拟信号，所述第一模拟信号指示所述多位数字信号中的位的值之和，所述第二模拟信号还指示所述多位数字信号中的所述位的值的所述和。第一模拟信号和第二模拟信号可以基本相等或它们可以彼此不同。

5. 发明授权

US5621345A In-phase and quadrature sampling circuit 失效
标题翻译：同相和正交采样电路
公开(公告)号：US5621345A
公开(公告)日：1997-04-15
申请号：US418546
申请日：1995-04-07
申请人： Wai L. Lee , Norman D. Grant , Paul F. Ferguson, Jr.
发明人： Wai L. Lee , Norman D. Grant , Paul F. Ferguson, Jr.
IPC分类号： H03D7/16 , H03C3/00 , H03H11/16
CPC分类号： H03D7/165
摘要： A circuit that provides samples of in-phase and quadrature components of an input waveform includes an oversampling ADC that receives the input waveform and converts the input waveform to digital samples at an oversampling rate. A first digital filter, coupled to the ADC, receives the digital samples from the ADC and provides the in-phase component samples of the input waveform. A second digital filter, coupled to the ADC, receives the digital samples from the ADC and provides the quadrature component samples of the input waveform.
摘要翻译：提供输入波形的同相和正交分量的样本的电路包括过采样ADC，其接收输入波形，并以过采样率将输入波形转换为数字采样。耦合到ADC的第一个数字滤波器从ADC接收数字采样，并提供输入波形的同相分量采样。耦合到ADC的第二个数字滤波器从ADC接收数字采样，并提供输入波形的正交分量采样。

6. 发明授权

US5517149A Gain linearity correction circuit for MOS circuits 失效
标题翻译：用于MOS电路的增益线性校正电路
公开(公告)号：US5517149A
公开(公告)日：1996-05-14
申请号：US259858
申请日：1994-06-15
申请人： Apparajan Ganesan , Paul F. Ferguson, Jr. , David H. Robertson
发明人： Apparajan Ganesan , Paul F. Ferguson, Jr. , David H. Robertson
IPC分类号： H03F1/22 , H03F1/32 , H03F3/45 , H03G3/00 , G06G7/12 , H03K17/14
CPC分类号： H03F1/3211 , H03F1/223 , H03F3/45076
摘要： Gain linearity problems caused by impact ionization in a active MOS device are avoided by connecting an MOS shield device in series with the active MOS device so that the overall supply voltage is split across two devices, keeping both devices in a region of operation well below where impact ionization becomes a significant problem. The gate of the MOS shield device is maintained at a voltage proportional to its drain voltage, thereby keeping the device in the saturation mode and avoiding an abrupt mode change associated with prior art shield circuits.
摘要翻译：通过将MOS屏蔽器件与有源MOS器件串联连接来避免由于在有源MOS器件中产生的冲击电离引起的增益线性问题，使得整个电源电压在两个器件之间分离，从而将两个器件保持在低于冲击电离成为一个重大问题。 MOS屏蔽器件的栅极保持与其漏极电压成比例的电压，从而保持器件处于饱和模式，并避免与现有技术的屏蔽电路相关的突然模式变化。

7. 发明授权

US5412387A Error reduction in switched capacitor digital-to-analog converter systems by balanced sampling 失效
标题翻译：开关电容数模转换器系统通过平衡采样降低误差
公开(公告)号：US5412387A
公开(公告)日：1995-05-02
申请号：US44370
申请日：1993-04-06
申请人： Scott Vincelette , Paul F. Ferguson, Jr. , Robert W. Adams
发明人： Scott Vincelette , Paul F. Ferguson, Jr. , Robert W. Adams
IPC分类号： H03M3/02 , H03M1/66
CPC分类号： H03M3/324 , H03M3/458 , H03M3/50
摘要： A switched-capacitor DAC system includes two switched-capacitor DACs and a load circuit. The switched-capacitor filter of the first DAC samples a reference voltage source, which produces a reference voltage, at a first rate and the switched-capacitor filter of the second DAC samples the reference voltage source at a second rate, greater than the first rate. The load circuit samples the reference voltage source at a rate such that the level of the reference voltage is the same each time a sample is taken. The load circuit effectively equates the sampling of the two filters and substantially eliminates problems related to gain errors and low frequency quantization noise.
摘要翻译：开关电容DAC系统包括两个开关电容DAC和负载电路。第一DAC的开关电容滤波器以第一速率对产生参考电压的参考电压源进行采样，并且第二DAC的开关电容滤波器以比第一速率的第二速率对第二速率采样第二速率。负载电路以参考电压的电平在每次采样时相同的速率对参考电压源进行采样。负载电路有效地等同于两个滤波器的采样，并且基本上消除了与增益误差和低频量化噪声有关的问题。

8. 发明授权

US5363102A Offset-insensitive switched-capacitor gain stage 失效
标题翻译：偏移不敏感的开关电容器增益级
公开(公告)号：US5363102A
公开(公告)日：1994-11-08
申请号：US37300
申请日：1993-03-26
申请人： Paul F. Ferguson, Jr.
发明人： Paul F. Ferguson, Jr.
IPC分类号： H03M3/02
CPC分类号： H03M3/356 , H03M3/486
摘要： An IC chip formed with an analog-to-digital converter having a switched-capacitor programmable gain stage and employing a switched-capacitor sigma-delta modulator. The chip includes pins to receive a number of different audio input signals which are selectively connectible to buffer amplifiers the outputs of which are directed to a switch to select one output for further processing. The selected buffer amplifier output is d-c coupled to an input signal terminal of a switched-capacitor programmable gain stage. The output of this gain stage is coupled to an output stage including an op-amp and associated switched-capacitor circuitry. The programmable gain stage has a reference input terminal which is connected through an IC chip pin to an external capacitor the other electrode of which is returned to signal common. This capacitor develops a d-c voltage corresponding to the offset voltages of the operative buffer amplifier and the op-amp, and including a component corresponding to charge-injection from MOS switches. Absorption of such d-c voltages by this capacitor prevents those voltages from being significantly gained by the amplifier circuitry, and thereby prevents those voltages from using up an excessive portion of the dynamic range of the circuitry.
摘要翻译：一种由具有开关电容可编程增益级并采用开关电容Σ-Δ调制器的模数转换器形成的IC芯片。芯片包括用于接收多个不同音频输入信号的引脚，其可选择性地连接到缓冲放大器，其输出被引导到开关以选择一个输出用于进一步处理。选择的缓冲放大器输出d-c耦合到开关电容可编程增益级的输入信号端。该增益级的输出耦合到包括运算放大器和相关的开关电容器电路的输出级。可编程增益级具有参考输入端，其通过IC芯片引脚连接到外部电容器，其另一个电极返回到信号共同。该电容器产生对应于操作缓冲放大器和运算放大器的偏移电压的d-c电压，并且包括对应于MOS开关的电荷注入的分量。通过该电容器吸收这种d-c电压可以防止放大器电路显着地获得这些电压，从而防止这些电压使电路的动态范围的过多部分使用。

9. 发明授权

US5311181A Sigma delta modulator 失效
标题翻译： Sigma delta调制器
公开(公告)号：US5311181A
公开(公告)日：1994-05-10
申请号：US60890
申请日：1993-05-12
申请人： Paul F. Ferguson, Jr. , Apparajan Ganesan , Robert W. Adams
发明人： Paul F. Ferguson, Jr. , Apparajan Ganesan , Robert W. Adams
IPC分类号： H03G3/02 , H03M3/02 , H03M7/32
CPC分类号： H03G3/02 , H03M3/454 , H03M7/3035 , H03M3/43 , H03M3/446 , H03M3/45 , H03M7/3028 , H03M7/304
摘要： A separate filter circuit is inserted between the D/A converter and the summing junction in the feedback path of a conventional sigma delta modulator. This additional filter allows control of the quantization noise transfer function profile independently of the forward signal transfer function. By proper tailoring of the transfer functions a third or higher order modulator can be constructed without instability developing. The modulator can also be constructed as a completely digital circuit and used as a noise shaping circuit in a digital digital-to-analog converter.
摘要翻译：在常规Σ-Δ调制器的反馈路径中的D / A转换器和求和结点之间插入单独的滤波电路。该附加滤波器允许独立于正向信号传递函数来控制量化噪声传递函数谱。通过适当调整传递函数，可以构建第三个或更高阶的调制器，而不会产生不稳定的发展。调制器也可以构造为完全数字电路，并用作数字数/模转换器中的噪声整形电路。

10. 发明授权

US06271784B1 Capacitor-based digital-to-analog converter with continuous time output 失效
标题翻译：具有连续时间输出的基于电容器的数/模转换器
公开(公告)号：US06271784B1
公开(公告)日：2001-08-07
申请号：US08909650
申请日：1997-08-12
申请人： Lapoe E. Lynn , Paul F. Ferguson, Jr. , Hae-Seung Lee
发明人： Lapoe E. Lynn , Paul F. Ferguson, Jr. , Hae-Seung Lee
IPC分类号： H03M166
CPC分类号： H03M1/0872 , H03M1/804
摘要： A digital-to-analog converter (DAC) including an array of switched input capacitors which store samples of charge proportional to a digital input signal, and an analog output circuit which integrates the samples of charge to generate an output analog signal that is proportional to said digital input signal. The capacitors store a binary representation of the digital input signal. The output circuit includes a zeroth order sample-and-hold circuit having first and second stages with respective first and second operational amplifiers. The first and second stages are cascaded together during a sample phase so that the analog output signal is stored in a capacitor in a feedback path between the output of the second stage and the input of the first stage, and are disconnected from one another during a hold phase so that the first stage is auto-zeroed and the second stage holds the analog output signal as a continuous time output.
摘要翻译：包括存储与数字输入信号成比例的电荷样本的开关式输入电容阵列的数模转换器（DAC），以及模拟输出电路，其对电荷采样进行积分，以产生与所述数字输入信号。电容器存储数字输入信号的二进制表示。输出电路包括具有第一和第二级的第零级采样和保持电路，其具有相应的第一和第二运算放大器。第一级和第二级在采样阶段级联在一起，使得模拟输出信号被存储在第二级的输出和第一级的输入之间的反馈路径中的电容器中，并且在一个保持相位使得第一级自动归零，第二级将模拟输出信号保持为连续时间输出。

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