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1. 发明申请

US20220271842A1 LINEARIZED OPTICAL DIGITAL-TO-ANALOG MODULATOR 有权
公开(公告)号：US20220271842A1
公开(公告)日：2022-08-25
申请号：US17736876
申请日：2022-05-04
申请人： Ramot at Tel Aviv University Ltd.
发明人： Yossef EHRLICHMAN , Ofer AMRANI , Shlomo RUSCHIN
IPC分类号： H04B10/516 , G02F1/01 , G02F7/00 , G02F1/225 , H04B10/50 , H04B10/25 , H04B10/2575 , H04B10/556 , H03M1/70 , H04B10/54 , H03M1/00
摘要： In a system for converting digital data into a modulated optical signal, an electrically controllable device, including a modulator having one or more actuating electrodes, provides an analog-modulated optical signal that is modulated in response to output data bits of a digital-to-digital mapping. A digital-to-digital conversion provides the mapping of input data words to the output data bits. The mapping enables adjustments to correct for non-linearities and other undesirable characteristics, thereby improving signal quality.

2. 发明申请

US20200091927A1 DAC AND OSCILLATION CIRCUIT 审中-公开
公开(公告)号：US20200091927A1
公开(公告)日：2020-03-19
申请号：US16470037
申请日：2017-12-14
申请人： SONY SEMICONDUCTOR SOLUTIONS CORPORATION
发明人： YOSHINOBU KAWASAKI , KENTARO YASUNAKA , TAKASHI MASUDA
IPC分类号： H03M1/70 , H03B5/12
摘要： The present technology relates to a DAC (Digital to Analog Converter) and an oscillation circuit that allow widening of a range of a voltage to be output from the DAC. A plurality of first switches is connected to a voltage-dividing resistor and each configured to output, as a first voltage, a voltage at a corresponding one of connection points between the voltage-dividing resistor and the plurality of first switches. A plurality of second switches is connected to the voltage-dividing resistor and each configured to output, as a second voltage, a voltage at a corresponding one of connection points between the voltage-dividing resistor and the plurality of second switches. The present technology can be applied to, for example, a VCO (Voltage-Controlled Oscillator) and the like that oscillates a signal with a frequency according to a voltage to be output from a DAC.

3. 发明授权

US10090854B1 Digital-to-analog converter and method for correcting gain mismatch between a first segment and a second segment of a digital-to-analog converter 有权
公开(公告)号：US10090854B1
公开(公告)日：2018-10-02
申请号：US15704152
申请日：2017-09-14
申请人： Intel Corporation
发明人： Martin Clara
IPC分类号： H03M1/66 , H03M1/68 , H03M1/08 , H03M1/10 , H03M1/70
摘要： A method for correcting gain mismatch between a first segment and a second segment of a digital-to-analog converter is provided. The first segment generates a first contribution to an analog output signal of the digital-to-analog converter based on a first number of bits of a digital input word for the digital-to-analog converter, wherein the second segment generates a second contribution to the analog output signal based on a second number of bits of the digital input word. The method includes extending a numeric range of a second control word for the second segment by a predefined number of bits, wherein the second control word is indicative of the second number of bits. Further, the method includes multiplying the second control word by a correction value that is based on information about a gain error of the first segment. The method additionally includes digitally filtering the multiplied first control word. After the digital filtering, the method further includes reducing the numeric range of the multiplied second control word by the predefined number of bits to generate a modified second control word for the second segment. Additionally, the method includes supplying the modified second control word as input to the second segment.

4. 发明授权

US10063249B2 Audio circuit for suppressing DC shock noise 有权
公开(公告)号：US10063249B2
公开(公告)日：2018-08-28
申请号：US15133817
申请日：2016-04-20
申请人： ROHM CO., LTD.
发明人： Mitsuteru Sakai
IPC分类号： H03G3/00 , H03M1/66 , H03F3/20 , H03M1/70 , H03F3/187 , H03F3/213 , H03F3/68 , H03M1/74 , H03G3/30
CPC分类号： H03M1/66 , H03F3/187 , H03F3/20 , H03F3/213 , H03F3/68 , H03F2200/03 , H03F2200/375 , H03G3/3005 , H03M1/70 , H03M1/742
摘要： A D/A converter converts digital audio data DIN into analog differential audio signals VP and VN. A differential to single-ended conversion circuit converts the differential audio signals VP and VN into a single-ended audio signal VSE. A volume circuit receives the single-ended audio signal VSE, and amplifies the single-ended audio signal VSE with a gain that corresponds to a volume value. A reference voltage source generates a reference voltage VREF commonly referred by the differential to single-ended conversion circuit and the volume circuit. In a calibration operation, a calibration circuit controls the D/A converter so as to shift at least one from among the differential audio signals VP and VN such that the difference between the output voltage VSE of the differential to single-ended conversion circuit and the reference voltage VREF approaches zero.

5. 发明授权

US09515626B2 Digital/analogue conversion 有权
标题翻译：数字/模拟转换
公开(公告)号：US09515626B2
公开(公告)日：2016-12-06
申请号：US14436648
申请日：2013-10-10
申请人： Cirrus Logic International Semiconductor Limited
发明人： John Paul Lesso
IPC分类号： H03M1/00 , H03G3/00 , H03M1/06 , H03M1/66 , H03M1/08 , H03M1/70
CPC分类号： H03G3/001 , H03M1/0624 , H03M1/0626 , H03M1/0863 , H03M1/66 , H03M1/70
摘要： The application relates to digital to analogue conversion circuits having dynamic gain control. A digital variable gain element (102) may apply gain to an input digital signal (DIN) upstream of a DAC (101) to make better use of the input range of the DAC and an analogue variable gain element (103) applies a compensating analogue gain. Again controller (201) has a gain allocation module (204) for controlling the allocation of gain between said digital and analogue variable gain elements in response to changes in a signal level of the input digital audio signal. In the present invention the gain allocation module is operable in first and second modes of operation where the response to reductions in signal level is slower in the first mode than in the second mode of operation. A low-level detector (202) monitors the input digital audio signal so as to detect a low-level part of the signal and the gain controller changes from the first mode to the second mode following detection of a low-level part of the input digital audio signal. The response of the gain allocation module in the second mode is preferably fast enough such that the digital gain can be changed to a target setting suitable for the low-level part of the signal before it is received at the digital gain element.
摘要翻译：该应用涉及具有动态增益控制的数模转换电路。数字可变增益元件（102）可以对DAC（101）上游的输入数字信号（DIN）施加增益，以更好地利用DAC的输入范围，并且模拟可变增益元件（103）应用补偿模拟获得。再次，控制器（201）具有增益分配模块（204），用于响应于输入数字音频信号的信号电平的变化来控制所述数字和模拟可变增益元件之间的增益分配。在本发明中，增益分配模块可在第一和第二操作模式中操作，其中对第一模式的信号电平降低的响应比在第二操作模式中更慢。低电平检测器（202）监视输入数字音频信号，以便在检测到输入的低电平部分之后检测信号的低电平部分，并且增益控制器从第一模式改变到第二模式数字音频信号。增益分配模块在第二模式中的响应优选地足够快，使得数字增益可以在其在数字增益元件被接收之前被改变为适合于信号的低电平部分的目标设置。

6. 发明授权

US09484947B1 Variable length dynamic element matching in digital-to-analog converters 有权
标题翻译：数模转换器中的可变长度动态元件匹配
公开(公告)号：US09484947B1
公开(公告)日：2016-11-01
申请号：US14869154
申请日：2015-09-29
申请人： ANALOG DEVICES, INC.
发明人： Khiem Quang Nguyen
IPC分类号： H03M1/06 , H03M1/70 , H03M1/08 , H03M1/74 , H03M1/00
CPC分类号： H03M1/70 , H03M1/00 , H03M1/002 , H03M1/066 , H03M1/747 , H03M3/338 , H03M3/50
摘要： Embodiments of the disclosure provide improved mechanisms for applying DEM techniques to a DAC comprising a plurality of cells. Disclosed mechanisms include keeping track of the amplitude of input digital signal over a certain time period to determine a range of amplitudes of a portion of the input signal, and, when converting the digital values of that portion to analog values and applying a particular DEM technique, limiting the number of DAC cells on which a DEM technique is applied only to a number that is necessary for generating the analog output corresponding to the tracked portion, which number is determined based on the tracked amplitudes and could be smaller than the total number of DAC cells. In this manner, mismatch error may be reduced for smaller input signal amplitudes. Whenever possible, unused DAC cells may be put into a power saving mode, providing the advantage of reduced power consumption.
摘要翻译：本公开的实施例提供了用于将DEM技术应用于包括多个单元的DAC的改进机制。公开的机制包括在一定时间段内跟踪输入数字信号的幅度以确定输入信号的一部分的幅度范围，并且当将该部分的数字值转换为模拟值并应用特定的DEM技术限制将DEM技术应用于其上的DAC单元的数量仅限于产生与被跟踪部分相对应的模拟输出所需的数量，该数目是基于跟踪幅度确定的，并且可以小于 DAC单元。以这种方式，对于较小的输入信号幅度，可能会降低失配误差。只要有可能，未使用的DAC单元可以进入省电模式，提供降低功耗的优点。

7. 发明授权

US09379727B1 Transmit digital to analog converter (DAC) spur attenuation 有权
标题翻译：发送数模转换器（DAC）杂散衰减
公开(公告)号：US09379727B1
公开(公告)日：2016-06-28
申请号：US14628996
申请日：2015-02-23
申请人： QUALCOMM Incorporated
发明人： Dongwon Seo , Yang You , Honghao Ji , Tongyu Song , Ganesh Saripalli , Shahin Mehdizad Taleie
IPC分类号： H03M1/06 , H03M1/70 , H04B1/04 , G05F3/18 , G05F1/56 , H03M1/00 , H03M1/74 , G05F1/575 , H02M3/156
CPC分类号： H03M1/0604 , G05F1/56 , G05F1/575 , G05F3/18 , H02M3/156 , H03F3/24 , H03M1/00 , H03M1/70 , H03M1/747 , H04B1/0475 , H04B2001/0408
摘要： A method and apparatus for attenuating transmit digital to analog converter (DAC) spurs is provided. The method begins when a reference voltage is injected into an amplifier. Next, an output of the ground low drop-out regulator is measured and is them compared with the reference voltage. The output of the amplifier is then adjusted based on the results of the comparison. If the reference voltage is higher then the output of the ground low drop-out regulator the output of the amplifier is adjusted to ground. If the reference voltage is lower than the output of the ground low drop-out regulator then the output of the amplifier is adjusted to match the reference voltage.
摘要翻译：提供了用于衰减发射数模转换器（DAC）杂散的方法和装置。当将参考电压注入放大器时，该方法开始。接下来，测量接地低压降稳压器的输出，并将其与参考电压进行比较。然后根据比较结果调整放大器的输出。如果参考电压较高，则接地低压降稳压器的输出将放大器的输出调整到地。如果参考电压低于接地低压降稳压器的输出，则调节放大器的输出以匹配参考电压。

8. 发明授权

US09306543B2 Temperature-compensated high accuracy clock 有权
标题翻译：温度补偿高精度时钟
公开(公告)号：US09306543B2
公开(公告)日：2016-04-05
申请号：US14149219
申请日：2014-01-07
申请人： FREESCALE SEMICONDUCTOR, INC.
发明人： Dale J. McQuirk , Michael T. Berens
IPC分类号： H03K3/011 , H03M1/70 , H03K5/00
CPC分类号： H03K3/011 , H03K5/00006 , H03M1/785 , H03M1/808
摘要： A tunable clock circuit has a dual overlapping digital to analog converter (DAC) and an oscillator. The dual overlapping DAC provides a first output selectable with a first resolution and a second output selectable with a second resolution. The first resolution is different from the second resolution. The oscillator has a first input coupled to the first output of the dual overlapping DAC, a second input coupled to the second output of the dual overlapping DAC, and an output providing a clock output signal.
摘要翻译：可调谐时钟电路具有双重重叠的数模转换器（DAC）和振荡器。双重重叠DAC提供可选择的第一输出，具有第一分辨率，第二输出可选择具有第二分辨率。第一项决议与第二项决议有所不同。振荡器具有耦合到双重重叠DAC的第一输出的第一输入，耦合到双重叠DAC的第二输出的第二输入和提供时钟输出信号的输出。

9. 发明授权

US09178526B2 Multi-zone data converters 有权
公开(公告)号：US09178526B2
公开(公告)日：2015-11-03
申请号：US14623743
申请日：2015-02-17
申请人： MaxLinear, Inc.
发明人： Curtis Ling
IPC分类号： H03M1/66 , H03M1/18 , H03M1/00 , H03M1/36 , H03M1/70 , H03M1/74
CPC分类号： H03M1/002 , H03M1/12 , H03M1/188 , H03M1/36 , H03M1/66 , H03M1/70 , H03M1/74 , H04B1/40
摘要： Aspects of a method and system for data converters having a transfer function with multiple operating zones. In some embodiments, an operating zone of the multiple operating zones is characterized by more stringent performance criteria than the other operating zones. Thus, such data converters may receive an input signal and generate an output signal from the input signal per the transfer function and the more stringent performance criteria in the appropriate operating zone.

10. 发明授权

US09143157B1 Dynamic gain switching digital to analog converter 有权
标题翻译：动态增益切换数模转换器
公开(公告)号：US09143157B1
公开(公告)日：2015-09-22
申请号：US14630817
申请日：2015-02-25
申请人： DSP Group LTD.
发明人： Ori Elyada
IPC分类号： H03M1/66 , H03M1/70 , H03M1/00 , H03M1/08
CPC分类号： H03M1/70 , H03M1/662
摘要： A digital to analog converter that may include a digital gain block; an analog gain block; a digital to analog conversion (DAC) block and a controller that is configured to: determine a digital gain factor, selected out of multiple digital gain factors, of the digital gain block and an analog gain factor, selected out of multiple analog gain factors of the analog gain block; wherein the DAC block is preceded by the digital gain block and is followed by the analog gain block; wherein the digital gain block is configured to multiply a digital input signal by the digital gain factor to provide an intermediate digital signal; wherein the DAC block is configured to convert the intermediate digital signal to a converted analog signal; and wherein the analog gain block is configured to multiply the converted analog signal by the analog gain factor to provide an output signal; wherein an increment of the analog gain factor results in a decrement of the digital gain factor.
摘要翻译：可以包括数字增益块的数模转换器; 模拟增益块数模转换（DAC）块和控制器，其被配置为：确定数字增益块的多个数字增益因子中选择的数字增益因子和从多个模拟增益因子中选择的模拟增益因子模拟增益块; 其中DAC块前面是数字增益块，后面是模拟增益块; 其中所述数字增益块被配置为将数字输入信号乘以所述数字增益因子以提供中间数字信号; 其中所述DAC块被配置为将所述中间数字信号转换为转换的模拟信号; 并且其中所述模拟增益块被配置为将所述转换的模拟信号乘以所述模拟增益因子以提供输出信号; 其中模拟增益因子的增量导致数字增益因子的减小。

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