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1. 发明授权

US4370405A Multilayer photoresist process utilizing an absorbant dye 失效
标题翻译：利用吸收剂染料的多层光刻胶工艺
公开(公告)号：US4370405A
公开(公告)日：1983-01-25
申请号：US248927
申请日：1981-03-30
申请人： Michael M. O'Toole , En-Den D. Liu , Mark S. Chang
发明人： Michael M. O'Toole , En-Den D. Liu , Mark S. Chang
IPC分类号： H01L21/302 , G03F7/09 , H01L21/027 , H01L21/30 , H01L21/3065 , G03C5/00
CPC分类号： G03F7/094 , H01L21/30
摘要： An improved photoetch technique is presented of the multilayer resist type wherein a thin top layer of resist and a thick planarizing layer are deposited on a substrate and the thin layer is exposed and developed to produce a patterned resist layer. The improvement involves dissolving a suitable dye in a layer between the thin top layer and the substrate. The dye is preferably selected to absorb light of the wavelengths used to expose the top layer but does not interfere with processing of the other layers.
摘要翻译：提出了一种改进的光刻技术，其中抗蚀剂的薄顶层和厚的平坦化层沉积在衬底上，并且薄层被曝光和显影以产生图案化的抗蚀剂层。该改进涉及将合适的染料溶解在薄顶层和基底之间的层中。优选选择染料以吸收用于暴露顶层的波长的光，但不影响其它层的处理。

2. 发明授权

US08329530B1 Method and system for providing contact to a first polysilicon layer in a flash memory device 有权
标题翻译：用于提供与闪存器件中的第一多晶硅层的接触的方法和系统
公开(公告)号：US08329530B1
公开(公告)日：2012-12-11
申请号：US13566741
申请日：2012-08-03
申请人： Mark S. Chang , Hao Fang , King Wai Kelwin Ko
发明人： Mark S. Chang , Hao Fang , King Wai Kelwin Ko
IPC分类号： H01L31/0328 , H01L31/0336 , H01L31/072 , H01L31/109
CPC分类号： H01L27/11521 , H01L21/76816 , H01L27/115
摘要： A method and system for providing at least one contact in a flash memory device is disclosed. The flash memory device includes a plurality of gate stacks and at lease one component including a polysilicon layer as a top surface. The method and system further include forming a silicide on the top surface of the polysilicon layer and providing an insulating layer covering the plurality of gate stacks, the at least one component and the silicide. The method and system also include etching the insulating layer to provide at least one contact hole. The insulating layer etching step uses the silicide as an etch stop layer to ensure that the insulating etching step does not etch through the polysilicon layer. The method and system also include filling the at least one contact hole with a conductor.
摘要翻译：公开了一种用于在闪速存储器件中提供至少一个触点的方法和系统。闪速存储器件包括多个栅极堆叠，并且至少包括一个包括多晶硅层作为顶表面的部件。该方法和系统还包括在多晶硅层的顶表面上形成硅化物，并提供覆盖多个栅叠层，至少一个元件和硅化物的绝缘层。该方法和系统还包括蚀刻绝缘层以提供至少一个接触孔。绝缘层蚀刻步骤使用硅化物作为蚀刻停止层，以确保绝缘蚀刻步骤不会蚀刻通过多晶硅层。该方法和系统还包括用导体填充至少一个接触孔。

3. 发明授权

US07439141B2 Shallow trench isolation approach for improved STI corner rounding 有权
标题翻译：浅沟隔离方法可改善STI拐角四舍五入
公开(公告)号：US07439141B2
公开(公告)日：2008-10-21
申请号：US10277395
申请日：2002-10-22
申请人： Unsoon Kim , Yu Sun , Hiroyuki Kinoshita , Kuo-Tung Chang , Harpreet K. Sachar , Mark S. Chang
发明人： Unsoon Kim , Yu Sun , Hiroyuki Kinoshita , Kuo-Tung Chang , Harpreet K. Sachar , Mark S. Chang
IPC分类号： H01L21/00
CPC分类号： H01L21/76235
摘要： A method for performing shallow trench isolation during semiconductor fabrication that improves trench corner rounding is disclosed. The method includes etching trenches into a silicon substrate between active regions, and performing a double liner oxidation process on the trenches. The method further includes performing a double sacrificial oxidation process on the active regions, wherein corners of the trenches are substantially rounded by the four oxidation processes.
摘要翻译：公开了一种用于在半导体制造期间进行浅沟槽隔离的方法，其改善沟槽角圆化。该方法包括将沟槽蚀刻到有源区域之间的硅衬底中，并在沟槽上执行双衬层氧化工艺。该方法还包括对活性区域进行双重牺牲氧化处理，其中沟槽的角通过四个氧化过程基本上被圆化。

4. 发明授权

US07015504B2 Sidewall formation for high density polymer memory element array 有权
标题翻译：用于高密度聚合物存储元件阵列的侧壁形成
公开(公告)号：US07015504B2
公开(公告)日：2006-03-21
申请号：US10699903
申请日：2003-11-03
申请人： Christopher F. Lyons , Mark S. Chang , Sergey D. Lopatin , Ramkumar Subramanian , Patrick K. Cheung , Minh V. Ngo , Jane V. Oglesby
发明人： Christopher F. Lyons , Mark S. Chang , Sergey D. Lopatin , Ramkumar Subramanian , Patrick K. Cheung , Minh V. Ngo , Jane V. Oglesby
IPC分类号： H01L47/00 , H01L29/06 , H01L35/24 , H01L51/00
CPC分类号： G11C11/5664 , B82Y10/00 , G11C13/0014 , G11C13/0016 , H01L27/285 , H01L51/0595
摘要： Systems and methodologies are disclosed for increasing the number of memory cells associated with a lithographic feature. The systems comprise memory elements that are formed on the sidewalls of the lithographic feature by employing various depositing and etching processes. The side wall memory cells can have a bit line of the wafer as the first electrode and operate with a second formed electrode to activate a portion of an organic matter that is formed there between.
摘要翻译：公开了用于增加与光刻特征相关联的存储单元的数量的系统和方法。这些系统包括通过采用各种沉积和蚀刻工艺在光刻特征的侧壁上形成的记忆元件。侧壁存储单元可以具有作为第一电极的晶片的位线，并且与第二形成的电极一起操作以激活在其间形成的有机物的一部分。

5. 发明授权

US06825060B1 Photosensitive polymeric memory elements 有权
标题翻译：光敏聚合物记忆元件
公开(公告)号：US06825060B1
公开(公告)日：2004-11-30
申请号：US10405272
申请日：2003-04-02
申请人： Christopher F. Lyons , Ramkumar Subramanian , Mark S. Chang
发明人： Christopher F. Lyons , Ramkumar Subramanian , Mark S. Chang
IPC分类号： H01L2100
CPC分类号： H01L27/285 , B82Y10/00 , G11C11/5664 , G11C13/0014 , G11C13/0016 , G11C13/025 , G11C13/04 , Y10S977/943
摘要： A method of making organic memory cells made of two electrodes with a controllably conductive media between the two electrodes is disclosed. The controllably conductive media contains an organic semiconductor layer that contains a photosensitive compound. The organic semiconductor layer is formed into memory cells using patterning techniques.
摘要翻译：公开了一种由在两个电极之间具有可控导电介质的两个电极制成的有机存储单元的方法。可控导电介质包含含有光敏化合物的有机半导体层。使用图案化技术将有机半导体层形成为存储单元。

6. 发明授权

US06727195B2 Method and system for decreasing the spaces between wordlines 有权
标题翻译：减少字线间空格的方法和系统
公开(公告)号：US06727195B2
公开(公告)日：2004-04-27
申请号：US09777457
申请日：2001-02-06
申请人： Michael K. Templeton , Mark S. Chang
发明人： Michael K. Templeton , Mark S. Chang
IPC分类号： H01L21336
CPC分类号： H01L27/11521 , H01L21/76802 , H01L23/528 , H01L27/115 , H01L2924/0002 , Y10S438/945 , Y10S438/946 , Y10S438/947 , H01L2924/00
摘要： A method and system for providing a semiconductor device is disclosed. The method and system include providing a semiconductor substrate and providing a plurality of lines separated by a plurality of spaces. Each of the plurality of spaces preferably has a first width that is less than a minimum feature size. In one aspect, the method and system include providing a reverse mask having a plurality of apertures on an insulating layer. In this aspect, the method and system also include trimming the reverse mask to increase a size of each of the plurality of apertures, removing a portion of the insulating layer exposed by the plurality of trimmed apertures to provide a plurality of trenches and providing a plurality of lines in the plurality of trenches. In a second aspect, the method and system include providing a reverse mask on the insulating layer and removing a first portion of the insulating layer exposed by the plurality of apertures to provide a plurality of trenches. The reverse mask includes a plurality of apertures having a first width. Each of the plurality of trenches has a width. In this aspect, the method and system also include trimming a second portion of the insulating layers to increase the width of each of the plurality of trenches and providing a plurality of lines in the plurality of trenches.
摘要翻译：公开了一种用于提供半导体器件的方法和系统。该方法和系统包括提供半导体衬底并提供由多个空间隔开的多条线。多个空间中的每一个优选地具有小于最小特征尺寸的第一宽度。在一个方面，该方法和系统包括在绝缘层上提供具有多个孔的反向掩模。在这方面，该方法和系统还包括修整反向掩模以增加多个孔中的每一个的尺寸，去除由多个修剪的孔暴露的绝缘层的一部分以提供多个沟槽并提供多个的多个沟槽中的线。在第二方面，所述方法和系统包括在绝缘层上提供反向掩模，并且去除由多个孔暴露的绝缘层的第一部分以提供多个沟槽。反向掩模包括具有第一宽度的多个孔。多个沟槽中的每一个具有宽度。在这方面，该方法和系统还包括修整绝缘层的第二部分以增加多个沟槽中的每一个的宽度并且在多个沟槽中提供多条线。

7. 发明授权

US06509232B1 Formation of STI (shallow trench isolation) structures within core and periphery areas of flash memory device 有权
标题翻译：闪存器件的核心和周边区域内的STI（浅沟槽隔离）结构的形成
公开(公告)号：US06509232B1
公开(公告)日：2003-01-21
申请号：US09969573
申请日：2001-10-01
申请人： Unsoon Kim , Mark S. Chang , Yider Wu , Chi Chang , Angela Hui , Yu Sun
发明人： Unsoon Kim , Mark S. Chang , Yider Wu , Chi Chang , Angela Hui , Yu Sun
IPC分类号： H01L21336
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/11536
摘要： STI (shallow trench isolation) structures are formed for a flash memory device fabricated within an semiconductor substrate comprised of a core area having an array of core flash memory cells fabricated therein and comprised of a periphery area having logic circuitry fabricated therein. A first set of STI (shallow trench isolation) openings within the core area are etched through the semiconductor substrate, and a second set of STI (shallow trench isolation) openings within the periphery area are etched through the semiconductor substrate. A core active device area of the semiconductor substrate within the core area is surrounded by the first set of STI openings, and a periphery active device area of the semiconductor substrate within the periphery area is surrounded by the second set of STI openings. Dielectric liners are formed at sidewalls of the first and second sets of STI openings with reaction of the semiconductor substrate at the sidewalls of the STI openings such that top corners of the semiconductor substrate of the core and periphery active device areas adjacent the STI openings are rounded. A trench dielectric material is deposited to fill the STI openings. In addition, the top corners of the periphery active device area are exposed by etching portions of the sidewalls of the second set of STI structures in a dip-off etch. The exposed top corners of the periphery active device area are further rounded after additional thermal oxidation of the exposed top corners of the periphery active device area. The rounded corners of the core and periphery active device areas result in minimized leakage current through a flash memory cell fabricated within the core active device area and through a MOSFET fabricated within the periphery active device area.
摘要翻译：形成STI（浅沟槽隔离）结构，用于制造在半导体衬底内的闪存器件，该半导体衬底由具有在其中制造的核心闪存单元阵列的核心区域组成，并由其中制造的逻辑电路的外围区域组成。核心区域内的第一组STI（浅沟槽隔离）开口被蚀刻穿过半导体衬底，并且外围区域内的第二组STI（浅沟槽隔离）开口被蚀刻穿过半导体衬底。核心区域内的半导体衬底的核心有源器件区域由第一组STI开口包围，并且周边区域内的半导体衬底的外围有源器件区域被第二组STI开口包围。电介质衬垫通过半导体衬底在STI开口的侧壁处的反应而形成在第一和第二组STI开口的侧壁处，使得芯部的半导体衬底和邻近STI开口的周边有源器件区域的顶角是圆形的。沉积沟槽电介质材料以填充STI开口。此外，通过在浸渍蚀刻中蚀刻第二组STI结构的侧壁的部分来暴露外围有源器件区域的顶角。外围有源器件区域的暴露的顶角在外围有源器件区域的暴露顶角的额外的热氧化之后被进一步倒圆。核心和外围有源器件区域的圆角导致通过在核心有源器件区域内制造的闪存单元和通过在外围有源器件区域内制造的MOSFET的最小化的漏电流。

8. 发明授权

US06472327B2 Method and system for etching tunnel oxide to reduce undercutting during memory array fabrication 有权
标题翻译：用于在存储器阵列制造期间蚀刻隧道氧化物以减少底切的方法和系统
公开(公告)号：US06472327B2
公开(公告)日：2002-10-29
申请号：US09925205
申请日：2001-08-08
申请人： King Wai Kelwin Ko , Mark S. Chang , Hao Fang
发明人： King Wai Kelwin Ko , Mark S. Chang , Hao Fang
IPC分类号： H01L21304
CPC分类号： H01L27/11526 , H01L21/28273 , H01L27/11534
摘要： A method and system for etching gate oxide during transistor fabrication is disclosed. The method and system begin by depositing a gate oxide on a substrate, followed by a deposition of a tunnel oxide mask over a portion of the gate oxide. The method and system further include performing a combination dry/wet-etch to remove the gate oxide uncovered by the tunnel oxide mask, which minimizes tunnel oxide undercut.
摘要翻译：公开了在晶体管制造期间蚀刻栅极氧化物的方法和系统。该方法和系统首先通过在衬底上沉积栅极氧化物，然后在栅极氧化物的一部分上沉积隧道氧化物掩模。该方法和系统还包括执行干/湿蚀刻组合以去除未被隧道氧化物掩模覆盖的栅极氧化物，其使隧道氧化物底切最小化。

9. 发明授权

US06420224B2 Stepper alignment mark formation with dual field oxide process 有权
标题翻译：步进对准标记形成与双场氧化法
公开(公告)号：US06420224B2
公开(公告)日：2002-07-16
申请号：US09836064
申请日：2001-04-16
申请人： Tatsuya Kajita , Mark S. Chang
发明人： Tatsuya Kajita , Mark S. Chang
IPC分类号： H01L218238
CPC分类号： G03F7/0035 , H01L23/544 , H01L27/1052 , H01L2223/5442 , H01L2223/54453 , H01L2223/5446 , H01L2223/5448 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor photomask set for producing wafer alignment accuracy in a semiconductor fabrication process. The photomask set produces an alignment mark that is accurate for subsequent fabrication after undergoing a dual field oxide (FOX) fabrication process. Prior arts methods have traditionally covered the alignment marks with layers of oxide material. The method includes the steps of: (a) providing a first photomask member having mask portions for forming a plurality of first field oxide regions on a first region of a semiconductor substrate and also having a mask portion for forming an alignment marker; (b) providing a second photomask member having mask portions for forming a plurality of second field oxide regions on a second region of the semiconductor substrate and also having mask portions delineated for covering any first field oxide regions and alignment marker formed by using the first photomask member; (c) forming the first field oxide regions and the alignment marker utilizing the first photomask member; (d) covering the formed first field oxide regions and the alignment marker with a photoresist material by utilizing the second photomask member; (e) forming the second field oxide regions after utilizing the second photomask member; (f) facilitating wafer alignment accuracy by removing the photoresist material and exposing the alignment marker; and (g) aligning a semiconductor wafer by utilizing the exposed alignment marker. The mask set can be used in conjunction with stepper wafer alignment tools and is especially useful in forming a memory semiconductor product capable of performing block data erasure operations. The exposed alignment marker facilitates checking and testing mask misalignment during the fabrication process.
摘要翻译：一种用于在半导体制造工艺中产生晶片对准精度的半导体光掩模组。光掩模组产生对准标记，其在进行双场氧化物（FOX）制造工艺之后的后续制造中是准确的。现有技术的方法传统上用氧化物材料层覆盖对准标记。该方法包括以下步骤：（a）提供具有用于在半导体衬底的第一区域上形成多个第一场氧化物区域的掩模部分并且还具有用于形成对准标记的掩模部分的第一光掩模构件; （b）提供具有掩模部分的第二光掩模部件，用于在半导体衬底的第二区域上形成多个第二场氧化物区域，并且还具有描绘用于覆盖任何第一场氧化物区域的掩模部分和使用第一光掩模形成的对准标记会员; （c）利用第一光掩模构件形成第一场氧化物区域和对准标记; （d）利用第二光掩模件覆盖所形成的第一场氧化物区域和对准标记物与光致抗蚀剂材料; （e）在利用第二光掩模构件之后形成第二场氧化物区域; （f）通过去除光致抗蚀剂材料并暴露对准标记物来促进晶片对准精度; 和（g）通过利用曝光的对准标记对准半导体晶片。掩模组可与步进晶片对准工具结合使用，并且特别适用于形成能够执行块数据擦除操作的存储器半导体产品。暴露的对准标记有助于在制造过程中检查和测试掩模未对准。

10. 发明授权

US07361588B2 Etch process for CD reduction of arc material 有权
标题翻译：电弧材料的CD还原蚀刻工艺
公开(公告)号：US07361588B2
公开(公告)日：2008-04-22
申请号：US11098049
申请日：2005-04-04
申请人： Phillip L. Jones , Mark S. Chang , Scott A. Bell
发明人： Phillip L. Jones , Mark S. Chang , Scott A. Bell
IPC分类号： H01L21/4763
CPC分类号： H01L21/32139 , H01L21/3088 , H01L21/31144
摘要： A method of reducing critical dimensions of a feature in a anti-reflective coating layer structure can utilize a polymerizing agent. The anti-reflective coating structure can be utilized to form various integrated circuit structures. The anti-reflective coating can be utilized to form gate stacks comprised of polysilicon and a dielectric layer, conductive lines, or other IC structure. The polymerizing agent can include carbon, hydrogen and fluorine.
摘要翻译：降低抗反射涂层结构中的特征的关键尺寸的方法可以利用聚合剂。抗反射涂层结构可用于形成各种集成电路结构。抗反射涂层可用于形成由多晶硅和电介质层，导电线或其它IC结构组成的栅叠层。聚合剂可以包括碳，氢和氟。

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