专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07015504B2 Sidewall formation for high density polymer memory element array 有权
标题翻译：用于高密度聚合物存储元件阵列的侧壁形成
公开(公告)号：US07015504B2
公开(公告)日：2006-03-21
申请号：US10699903
申请日：2003-11-03
申请人： Christopher F. Lyons , Mark S. Chang , Sergey D. Lopatin , Ramkumar Subramanian , Patrick K. Cheung , Minh V. Ngo , Jane V. Oglesby
发明人： Christopher F. Lyons , Mark S. Chang , Sergey D. Lopatin , Ramkumar Subramanian , Patrick K. Cheung , Minh V. Ngo , Jane V. Oglesby
IPC分类号： H01L47/00 , H01L29/06 , H01L35/24 , H01L51/00
CPC分类号： G11C11/5664 , B82Y10/00 , G11C13/0014 , G11C13/0016 , H01L27/285 , H01L51/0595
摘要： Systems and methodologies are disclosed for increasing the number of memory cells associated with a lithographic feature. The systems comprise memory elements that are formed on the sidewalls of the lithographic feature by employing various depositing and etching processes. The side wall memory cells can have a bit line of the wafer as the first electrode and operate with a second formed electrode to activate a portion of an organic matter that is formed there between.
摘要翻译：公开了用于增加与光刻特征相关联的存储单元的数量的系统和方法。这些系统包括通过采用各种沉积和蚀刻工艺在光刻特征的侧壁上形成的记忆元件。侧壁存储单元可以具有作为第一电极的晶片的位线，并且与第二形成的电极一起操作以激活在其间形成的有机物的一部分。

2. 发明授权

US06787458B1 Polymer memory device formed in via opening 失效
标题翻译：聚合物存储器件形成在通孔中
公开(公告)号：US06787458B1
公开(公告)日：2004-09-07
申请号：US10614397
申请日：2003-07-07
申请人： Nicholas H. Tripsas , Matthew S. Buynoski , Suzette K. Pangrle , Uzodinma Okoroanyanwu , Angela T. Hui , Christopher F. Lyons , Ramkumar Subramanian , Sergey D. Lopatin , Minh Van Ngo , Ashok M. Khathuria , Mark S. Chang , Patrick K. Cheung , Jane V. Oglesby
发明人： Nicholas H. Tripsas , Matthew S. Buynoski , Suzette K. Pangrle , Uzodinma Okoroanyanwu , Angela T. Hui , Christopher F. Lyons , Ramkumar Subramanian , Sergey D. Lopatin , Minh Van Ngo , Ashok M. Khathuria , Mark S. Chang , Patrick K. Cheung , Jane V. Oglesby
IPC分类号： H01L2144
CPC分类号： H01L27/285 , H01L2924/0002 , H01L2924/00
摘要： One aspect of the present invention relates to a method of fabricating a polymer memory device in a via. The method involves providing a semiconductor substrate having at least one metal-containing layer thereon, forming at least one copper contact in the metal-containing layer, forming at least one dielectric layer over the copper contact, forming at least one via in the dielectric layer to expose at least a portion of the copper contact, forming a polymer material in a lower portion of the via, and forming a top electrode material layer in an upper portion of the via.
摘要翻译：本发明的一个方面涉及在通孔中制造聚合物存储器件的方法。该方法包括提供其上具有至少一个含金属层的半导体衬底，在含金属层中形成至少一个铜触点，在铜触点上形成至少一个电介质层，在电介质层中形成至少一个通孔露出铜触点的至少一部分，在通孔的下部形成聚合物材料，并在通孔的上部形成顶部电极材料层。

3. 发明授权

US06836398B1 System and method of forming a passive layer by a CMP process 有权
标题翻译：通过CMP工艺形成钝化层的系统和方法
公开(公告)号：US06836398B1
公开(公告)日：2004-12-28
申请号：US10284769
申请日：2002-10-31
申请人： Ramkumar Subramanian , Jane V. Oglesby , Minh Van Ngo , Mark S. Chang , Sergey D. Lopatin , Angela T. Hui , Christopher F. Lyons , Patrick K. Cheung , Ashok M. Khathuria
发明人： Ramkumar Subramanian , Jane V. Oglesby , Minh Van Ngo , Mark S. Chang , Sergey D. Lopatin , Angela T. Hui , Christopher F. Lyons , Patrick K. Cheung , Ashok M. Khathuria
IPC分类号： H01G435
CPC分类号： G11C13/0014 , B82Y10/00 , G11C13/0016 , H01L21/3212 , H01L27/285 , H01L28/75
摘要： The present invention provides systems and methods that facilitate formation of semiconductor devices via planarization processes. The present invention utilizes dishing effects that typically occur during a chemical mechanical planarization (CMP) process. A reducing CMP process is performed on a semiconductor device in order to form a passive layer instead of performing a first CMP, followed by a deposition and a second CMP to form a passive layer. The reducing CMP process utilizes a slurry that includes a reducing chemistry that forms the passive layer in a dish region of an electrode. Thus, the passive layer is formed in conjunction with the reducing CMP process utilized for forming the electrode.
摘要翻译：本发明提供了通过平坦化工艺有助于形成半导体器件的系统和方法。本发明利用通常在化学机械平面化（CMP）工艺中发生的凹陷效应。在半导体器件上进行还原CMP工艺以形成无源层，而不是执行第一CMP，随后进行沉积和第二CMP以形成钝化层。还原CMP方法利用包含在电极的盘区域中形成钝化层的还原化学物质的浆料。因此，钝化层与用于形成电极的还原CMP工艺结合形成。

4. 发明授权

US06803267B1 Silicon containing material for patterning polymeric memory element 有权
标题翻译：含硅材料用于图案化聚合物记忆元件
公开(公告)号：US06803267B1
公开(公告)日：2004-10-12
申请号：US10614484
申请日：2003-07-07
申请人： Ramkumar Subramanian , Christopher F. Lyons , Matthew S. Buynoski , Patrick K. Cheung , Angela T. Hui , Ashok M. Khathuria , Sergey D. Lopatin , Minh Van Ngo , Jane V. Oglesby , Terence C. Tong , James J. Xie
发明人： Ramkumar Subramanian , Christopher F. Lyons , Matthew S. Buynoski , Patrick K. Cheung , Angela T. Hui , Ashok M. Khathuria , Sergey D. Lopatin , Minh Van Ngo , Jane V. Oglesby , Terence C. Tong , James J. Xie
IPC分类号： H01L21336
CPC分类号： H01L27/28 , B82Y10/00 , G11C13/0014 , G11C13/0016 , H01L51/0018
摘要： The present invention provides a method to fabricate an organic memory device, wherein the fabrication method includes forming a lower electrode, depositing a passive material over the surface of the lower electrode, applying an organic semiconductor material over the passive material, and operatively coupling the an upper electrode to the lower electrode through the organic semiconductor material and the passive material. Patterning of the organic semiconductor material is achieved by depositing a silicon-based resist over the organic semiconductor, irradiating portions of the silicon-based resist and patterning the silicon-based resist to remove the irradiated portions of the silicon-based resist. Thereafter, the exposed organic semiconductor can be patterned, and the non-irradiated silicon-based resist can be stripped to expose the organic semiconductor material that can be employed as a memory cell for single and multi-cell memory devices. A partitioning component can be integrated with the memory device to facilitate stacking memory devices and programming, reading, writing and erasing memory elements.
摘要翻译：本发明提供一种制造有机存储器件的方法，其中所述制造方法包括形成下电极，在所述下电极的表面上沉积无源材料，在所述被动材料上施加有机半导体材料，以及将所述有源半导体材料上电极通过有机半导体材料和被动材料到下电极。有机半导体材料的图案化是通过在有机半导体上沉积硅基抗蚀剂，照射硅基抗蚀剂的部分并图案化硅基抗蚀剂以除去硅基抗蚀剂的照射部分来实现的。此后，可以对暴露的有机半导体进行构图，并且可以剥离未照射的硅基抗蚀剂以暴露可用作单电池和多电池存储器件的存储器单元的有机半导体材料。分区组件可以与存储器件集成，以便于堆叠存储器件和编程，读取，写入和擦除存储器元件。

5. 发明授权

US06773954B1 Methods of forming passive layers in organic memory cells 失效
标题翻译：在有机记忆细胞中形成钝化层的方法
公开(公告)号：US06773954B1
公开(公告)日：2004-08-10
申请号：US10313494
申请日：2002-12-05
申请人： Ramkumar Subramanian , Jane V. Oglesby , Sergey D. Lopatin , Mark S. Chang , Christopher F. Lyons , James J. Xie , Minh Van Ngo
发明人： Ramkumar Subramanian , Jane V. Oglesby , Sergey D. Lopatin , Mark S. Chang , Christopher F. Lyons , James J. Xie , Minh Van Ngo
IPC分类号： H01L5140
CPC分类号： G11C13/0014 , B82Y10/00 , G11C13/0016 , H01L27/28 , H01L51/0034 , H01L51/0035 , H01L51/0036 , H01L51/0037 , H01L51/0043 , H01L51/0053 , H01L51/0059 , H01L51/0062 , H01L51/0077 , H01L51/0078 , H01L51/0081 , H01L51/0085
摘要： Methods of making an organic memory cell made of two electrodes with a controllably conductive media between the two electrodes are disclosed. The controllably conductive Media contains an organic semiconductor layer and passive layer. In particular, novel methods of forming a electrode and adjacent passive layer are described.
摘要翻译：公开了在两个电极之间制造由具有可控导电介质的两个电极制成的有机存储单元的方法。可控导电介质包含有机半导体层和无源层。特别地，描述了形成电极和相邻钝化层的新颖方法。

6. 发明授权

US06656763B1 Spin on polymers for organic memory devices 失效
标题翻译：旋转有机存储器件的聚合物
公开(公告)号：US06656763B1
公开(公告)日：2003-12-02
申请号：US10385375
申请日：2003-03-10
申请人： Jane V. Oglesby , Christopher F. Lyons , Ramkumar Subramanian , Angela T. Hui , Minh Van Ngo , Suzette K. Pangrle
发明人： Jane V. Oglesby , Christopher F. Lyons , Ramkumar Subramanian , Angela T. Hui , Minh Van Ngo , Suzette K. Pangrle
IPC分类号： H01L5140
CPC分类号： G11C13/025 , B82Y10/00 , G11C11/5664 , G11C13/0014 , G11C13/0016 , G11C2213/16 , G11C2213/71 , H01L27/285 , H01L51/0003 , H01L51/0004 , H01L51/0034 , H01L51/0035 , H01L51/0036 , H01L51/0037 , H01L51/0038 , H01L51/0041 , H01L51/005 , H01L51/0053 , H01L51/0059 , H01L51/0062 , H01L51/0077 , H01L51/0078 , H01L51/0081 , H01L51/0084 , H01L51/0085 , Y10S977/843 , Y10S977/944
摘要： A method of making organic memory cells made of two electrodes with a controllably conductivce media between the two electrodes is disclosed. The controllably conductive media contains an organic semiconductor layer and passive layer. The organic semiconductor layer is formed using spin-on techniques with the assistance of certain solvents.
摘要翻译：公开了一种在两个电极之间制造具有可控导电介质的两个电极制成的有机存储单元的方法。可控导电介质包含有机半导体层和无源层。在某些溶剂的帮助下，使用旋转技术形成有机半导体层。

7. 发明授权

US07115440B1 SO2 treatment of oxidized CuO for copper sulfide formation of memory element growth 有权
标题翻译： SO2处理氧化CuO对硫化铜形成记忆元素生长
公开(公告)号：US07115440B1
公开(公告)日：2006-10-03
申请号：US10957247
申请日：2004-10-01
申请人： Christopher F. Lyons , Ramkumar Subramanian , Sergey D. Lopatin , James J. Xie , Angela T. Hui
发明人： Christopher F. Lyons , Ramkumar Subramanian , Sergey D. Lopatin , James J. Xie , Angela T. Hui
IPC分类号： H01L21/00
CPC分类号： H01L51/0575 , B82Y10/00 , G11C13/0014 , G11C13/0016 , G11C2213/77 , H01L27/285 , H01L51/105
摘要： Disclosed are methods of making memory cells and semiconductor devices containing the memory cells. The methods involve oxidizing a portion of a copper containing electrode to form a copper oxide layer; contacting the copper oxide layer with at least one of a sulfur containing gas or plasma to form a CuS layer; forming an organic semiconductor over the CuS layer; and forming an electrode over the organic semiconductor. Such devices containing the memory cells are characterized by light weight and robust reliability.
摘要翻译：公开了制造存储单元和包含存储单元的半导体器件的方法。所述方法包括氧化一部分含铜电极以形成氧化铜层; 使所述氧化铜层与含硫气体或等离子体中的至少一种接触以形成CuS层; 在CuS层上形成有机半导体; 并在有机半导体上形成电极。包含存储器单元的这种器件的特征在于重量轻和鲁棒的可靠性。

8. 发明授权

US06825060B1 Photosensitive polymeric memory elements 有权
标题翻译：光敏聚合物记忆元件
公开(公告)号：US06825060B1
公开(公告)日：2004-11-30
申请号：US10405272
申请日：2003-04-02
申请人： Christopher F. Lyons , Ramkumar Subramanian , Mark S. Chang
发明人： Christopher F. Lyons , Ramkumar Subramanian , Mark S. Chang
IPC分类号： H01L2100
CPC分类号： H01L27/285 , B82Y10/00 , G11C11/5664 , G11C13/0014 , G11C13/0016 , G11C13/025 , G11C13/04 , Y10S977/943
摘要： A method of making organic memory cells made of two electrodes with a controllably conductive media between the two electrodes is disclosed. The controllably conductive media contains an organic semiconductor layer that contains a photosensitive compound. The organic semiconductor layer is formed into memory cells using patterning techniques.
摘要翻译：公开了一种由在两个电极之间具有可控导电介质的两个电极制成的有机存储单元的方法。可控导电介质包含含有光敏化合物的有机半导体层。使用图案化技术将有机半导体层形成为存储单元。

9. 发明授权

US06878961B2 Photosensitive polymeric memory elements 有权
标题翻译：光敏聚合物记忆元件
公开(公告)号：US06878961B2
公开(公告)日：2005-04-12
申请号：US10951370
申请日：2004-09-28
申请人： Christopher F. Lyons , Ramkumar Subramanian , Mark S. Chang
发明人： Christopher F. Lyons , Ramkumar Subramanian , Mark S. Chang
IPC分类号： G11C11/56 , G11C13/02 , H01L27/28 , H01L35/24
CPC分类号： H01L27/285 , B82Y10/00 , G11C11/5664 , G11C13/0014 , G11C13/0016 , G11C13/025 , G11C13/04 , Y10S977/943
摘要： A method of making organic memory cells made of two electrodes with a controllably conductive media between the two electrodes is disclosed. The controllably conductive media contains an organic semiconductor layer that contains a photosensitive compound. The organic semiconductor layer is formed into memory cells using patterning techniques.
摘要翻译：公开了一种由在两个电极之间具有可控导电介质的两个电极制成的有机存储单元的方法。可控导电介质包含含有光敏化合物的有机半导体层。使用图案化技术将有机半导体层形成为存储单元。

10. 发明授权

US07018922B1 Patterning for elongated VSS contact flash memory 有权
标题翻译：扩展VSS接触闪存的图案化
公开(公告)号：US07018922B1
公开(公告)日：2006-03-28
申请号：US10968713
申请日：2004-10-19
申请人： Hung-eil Kim , Anna Minvielle , Christopher F. Lyons , Marina V. Plat , Ramkumar Subramanian
发明人： Hung-eil Kim , Anna Minvielle , Christopher F. Lyons , Marina V. Plat , Ramkumar Subramanian
IPC分类号： H01L21/4763
CPC分类号： H01L27/11521 , H01L21/76802 , H01L27/115
摘要： A method of forming a contact in a flash memory device is disclosed. The method increases the depth of focus margin and the overlay margin between the contact and the stacked gate layers. A plurality of stacked gate layers are formed on a semiconductor substrate, wherein each stacked gate layer extends in a predefined direction and is substantially parallel to other stacked gate layers. An interlayer insulating layer is deposited over the plurality of stacked gate layers, and a contact hole is patterned between a first stacked gate layer of the plurality of stacked gate layers and a second stacked gate layer of the plurality of stacked gate layers. The contact hole is formed in an elongated shape, wherein a major axis of the contact hole is substantially parallel to the stacked gate layers. A conductive layer is deposited in the contact hole and excess conductive material is removed.
摘要翻译：公开了一种在闪速存储器件中形成触点的方法。该方法增加了接触和层叠栅极层之间的焦距裕度和覆盖边缘的深度。在半导体衬底上形成多个层叠的栅极层，其中每个堆叠的栅极层沿预定的方向延伸并且基本上平行于其它堆叠的栅极层。层叠绝缘层沉积在多个堆叠的栅极层上，并且在多个堆叠的栅极层的第一堆叠的栅极层和多个堆叠的栅极层的第二叠层栅极层之间形成接触孔。接触孔形成为细长形状，其中接触孔的长轴基本上平行于堆叠的栅极层。导电层沉积在接触孔中，去除过量的导电材料。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式