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    • 1. 发明申请
    • Apparatus and method for detecting multiple hits in CAM arrays
    • 用于检测CAM阵列中多次命中的装置和方法
    • US20060002163A1
    • 2006-01-05
    • US10880719
    • 2004-06-30
    • Michael Ju LeeSheldon LevensteinEdelmar Seewann
    • Michael Ju LeeSheldon LevensteinEdelmar Seewann
    • G11C15/00
    • G11C15/00
    • An apparatus and method are disclosed for detecting multiple hits in CAM arrays. A binary address value is stored for each entry of the CAM array and is output to identify the matching entry for a single hit. However, to facilitate multiple hit detection, both the true and complement components of this address are stored and output to determine whether or not a multiple hit occurred. If a multiple hit occurs (e.g., more than one address location has been matched), all the bits that make up the binary address and the complement will not be complements of each other and a multiple hit condition can be detected by XORing each bit of an address location value with the complement of that address location value. If the XORed bits are equal to “1”, then a single hit has occurred. Otherwise, a multiple hit has occurred.
    • 公开了用于检测CAM阵列中的多个命中的装置和方法。 为CAM阵列的每个条目存储二进制地址值,并输出以识别单个命中的匹配条目。 然而,为了便于多次命中检测,存储和输出该地址的真实和补码成分,以确定是否发生多次命中。 如果发生多重命中(例如,多于一个地址位置已匹配),构成二进制地址和补码的所有位将不会互相补充,并且可以通过将每个位的异或来检测多个命中条件 具有该地址位置值的补码的地址位置值。 如果异或位等于“1”,则发生单击。 否则,发生多重命中。
    • 2. 发明申请
    • Lookahead mode sequencer
    • 前瞻模式音序器
    • US20060184772A1
    • 2006-08-17
    • US11055862
    • 2005-02-11
    • Miles DooleyScott FrommerHung LeSheldon LevensteinAnthony Saporito
    • Miles DooleyScott FrommerHung LeSheldon LevensteinAnthony Saporito
    • G06F9/30
    • G06F9/3836G06F9/3855G06F9/3857G06F9/3867
    • A method, system, and computer program product for enhancing performance of an in-order microprocessor with long stalls. In particular, the mechanism of the present invention provides a data structure for storing data within the processor. The mechanism of the present invention comprises a data structure including information used by the processor. The data structure includes a group of bits to keep track of which instructions preceded a rejected instruction and therefore will be allowed to complete and which instructions follow the rejected instruction. The group of bits comprises a bit indicating whether a reject was a fast or slow reject; and a bit for each cycle that represents a state of an instruction passing through a pipeline. The processor speculatively continues to execute a set bit's corresponding instruction during stalled periods in order to generate addresses that will be needed when the stall period ends and normal dispatch resumes.
    • 一种方法,系统和计算机程序产品,用于增强具有长档位的按顺序微处理器的性能。 特别地,本发明的机构提供了一种用于在处理器内存储数据的数据结构。 本发明的机构包括包括由处理器使用的信息的数据结构。 数据结构包括一组比特,用于跟踪被拒绝指令之前的哪些指令,因此将被允许完成,以及哪些指令遵循被拒绝的指令。 该比特组包括指示拒绝是否是快速或慢速拒绝的位; 以及表示通过管道的指令的状态的每个周期的一点。 处理器推测地在停滞时段期间继续执行设置位的相应指令,以便产生在停滞期结束并且恢复正常调度时将需要的地址。
    • 3. 发明申请
    • Mini-refresh processor recovery as bug workaround method using existing recovery hardware
    • 微型刷新处理器恢复作为使用现有恢复硬件的错误解决方法
    • US20060184771A1
    • 2006-08-17
    • US11055823
    • 2005-02-11
    • Michael FloydLarry LeitnerSheldon LevensteinScott SwaneyBrian Thompto
    • Michael FloydLarry LeitnerSheldon LevensteinScott SwaneyBrian Thompto
    • G06F9/30
    • G06F9/3863G06F9/3851
    • A method in a data processing system for avoiding a microprocessor's design defects and recovering a microprocessor from failing due to design defects, the method comprised of the following steps: The method detects and reports of events which warn of an error. Then the method locks a current checkpointed state and prevents instructions not checkpointed from checkpointing. After that, the method releases checkpointed state stores to a L2 cache, and drops stores not checkpointed. Next, the method blocks interrupts until recovery is completed. Then the method disables the power savings states throughout the processor. After that, the method disables an instruction fetch and an instruction dispatch. Next, the method sends a hardware reset signal. Then the method restores selected registers from the current checkpointed state. Next, the method fetches instructions from restored instruction addresses. Then the method resumes a normal execution after a programmable number of instructions.
    • 一种用于避免微处理器设计缺陷并由于设计缺陷而使微处理器故障恢复的数据处理系统中的方法,该方法包括以下步骤:该方法检测并报告发生错误的事件。 然后,该方法锁定当前的检查点状态,并防止从检查点进行检查点的指令。 之后,该方法将检查点状态存储发送到L2缓存,并且将不检查点丢弃存储。 接下来,该方法将阻止中断,直到恢复完成。 然后该方法将禁用整个处理器的省电状态。 之后,该方法禁用指令提取和指令分派。 接下来,该方法发送硬件复位信号。 然后,该方法将从当前检查点状态恢复所选寄存器。 接下来,该方法从恢复的指令地址获取指令。 然后,该方法在可编程指令数量之后恢复正常执行。
    • 4. 发明申请
    • Method and apparatus for efficiently accessing both aligned and unaligned data from a memory
    • 用于从存储器有效地访问对准和未对齐数据的方法和装置
    • US20060184734A1
    • 2006-08-17
    • US11055828
    • 2005-02-11
    • Eric FluhrSheldon Levenstein
    • Eric FluhrSheldon Levenstein
    • G06F12/00
    • G06F12/04G06F12/0846G06F12/0886
    • A technique for improving access times when accessing memory, such as when accessing data from cache. By a unique manipulation and usage of a specified memory address in combination with the cache's internal organization, the address range required by the requested data can be covered by one odd and one even segment of the cache, where the odd segment is always at the base address created by the summation of the source operands and set to the odd segment, and the even address is created by summation of the source operands plus an offset value equivalent to the size of the cache line. This structural regularity is used to efficiently generate both the even and odd addresses in parallel to retrieve the desired data.
    • 一种用于在访问内存时改进访问时间的技术,例如从缓存访问数据时。 通过与高速缓存的内部组织结合使用指定的存储器地址的独特操作和使用,所请求的数据所需的地址范围可以由高速缓存的一个奇数和一个偶数段覆盖,其中奇数段总是在基地 地址由源操作数的总和创建并设置为奇数段,偶数地址是通过源操作数的加法加上与缓存行大小相等的偏移值来创建的。 这种结构规律性用于有效地同时产生偶数和奇数地址以检索所需数据。