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1. 发明授权

US08756286B2 Alternate E-mail address configuration 有权
标题翻译：备用电子邮件地址配置
公开(公告)号：US08756286B2
公开(公告)日：2014-06-17
申请号：US12921762
申请日：2009-03-10
申请人： Len Albert Bayles , Ernie Dainow , Derek Williams , Joseph Chiu Kit Yee
发明人： Len Albert Bayles , Ernie Dainow , Derek Williams , Joseph Chiu Kit Yee
IPC分类号： G06F15/16
CPC分类号： H04L29/12594 , H04L51/066 , H04L51/14 , H04L51/28 , H04L61/3035 , H04L61/307
摘要： A method is provided for transmitting an electronic mail (e-mail) message from a sender having a non-ASCII e-mail address to a recipient. Provided is an e-mail directory associated with a requested primary e-mail address, having a non-ASCII form, and a corresponding alternate e-mail address having an ASCII form. The alternate e-mail is generated from the primary e-mail address using a reversible encoding scheme having a one-to-one relationship. The e-mail message, the alternate e-mail address, and the primary e-mail address are transmitted to the recipient via a plurality of mail delivery elements. The alternate e-mail address is transmitted to a mail delivery element incapable of processing non-ASCII characters. The alternate e-mail address is for use by the mail delivery element to identify the sender and deliver the e-mail message to the recipient for display.
摘要翻译：提供一种用于从具有非ASCII电子邮件地址的发送方向接收者发送电子邮件（电子邮件）消息的方法。提供了与所请求的主电子邮件地址相关联的电子邮件目录，具有非ASCII格式以及具有ASCII格式的对应备用电子邮件地址。使用具有一对一关系的可逆编码方案，从主电子邮件地址生成备用电子邮件。电子邮件消息，备用电子邮件地址和主要电子邮件地址通过多个邮件传递元件发送给接收者。备用电子邮件地址被传送到不能处理非ASCII字符的邮件传递元件。备用电子邮件地址由邮件传递元件用于识别发件人，并将电子邮件传送给收件人进行显示。

2. 发明申请

US20070234268A1 METHOD, SYSTEM AND PROGRAM PRODUCT FOR PROVIDING A CONFIGURATION SPECIFICATION LANGUAGE SUPPORTING SELECTIVE PRESENTATION OF CONFIGURATION ENTITIES 有权
标题翻译：用于提供配置规范语言的方法，系统和程序产品支持配置实体的选择性介绍
公开(公告)号：US20070234268A1
公开(公告)日：2007-10-04
申请号：US11762597
申请日：2007-06-13
申请人： WOLFGANG ROESNER , Derek Williams
发明人： WOLFGANG ROESNER , Derek Williams
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： In at least one hardware definition language (HDL) file, at least one design entity containing a functional portion of a digital system is specified. The design entity logically contains a latch having a respective plurality of different possible latch values. With one or more statements in one or more files, a configuration entity is associated with the latch. The configuration entity has a plurality of different settings and each setting reflects which of the plurality of different possible values is loaded in the associated latch. A controlling value set for at least one instance of the configuration entity is also defined in one or more files. The controlling value set indicates at least one controlling value for which presentation of a current setting of the configuration entity instance is restricted. Thereafter, in response to a request to present at least a partial state of the digital system, a current setting of the configuration entity instance is excluded from presentation by reference to a configuration database indicating the controlling value set.
摘要翻译：在至少一个硬件定义语言（HDL）文件中，指定包含数字系统的功能部分的至少一个设计实体。设计实体逻辑地包含具有相应多个不同可能锁存值的锁存器。在一个或多个文件中使用一个或多个语句，配置实体与锁存器相关联。配置实体具有多个不同的设置，并且每个设置反映多个不同的可能值中的哪一个加载到相关联的锁存器中。对于配置实体的至少一个实例设置的控制值也被定义在一个或多个文件中。控制值集合指示限制配置实体的当前设置的呈现的至少一个控制值。此后，响应于呈现数字系统的至少部分状态的请求，通过参考指示控制值集合的配置数据库将配置实体实例的当前设置排除在呈现之外。

3. 发明申请

US20070168618A1 Data processing system, cache system and method for precisely forming an invalid coherency state indicating a broadcast scope 失效
标题翻译：数据处理系统，缓存系统和精确形成指示广播范围的无效一致性状态的方法
公开(公告)号：US20070168618A1
公开(公告)日：2007-07-19
申请号：US11333615
申请日：2006-01-17
申请人： Leo Clark , Guy Guthrie , William Starke , Jeffrey Stuecheli , Derek Williams
发明人： Leo Clark , Guy Guthrie , William Starke , Jeffrey Stuecheli , Derek Williams
IPC分类号： G06F13/28
CPC分类号： G06F12/0831
摘要： A cache coherent data processing system includes at least first and second coherency domains. In a first cache memory within the first coherency domain of the data processing system, a memory block is held in a storage location associated with an address tag and a coherency state field. A determination is made if a home system memory assigned an address associated with the memory block is within the first coherency domain. If not, the coherency state field is set to a coherency state that indicates that the address tag is valid, that the storage location does not contain valid data, the first coherency domain does not contain the home system memory, and that, following formation of the coherency state, the memory block is cached outside of the first coherency domain.
摘要翻译：缓存相干数据处理系统至少包括第一和第二相干域。在数据处理系统的第一相关域内的第一高速缓存存储器中，存储块被保存在与地址标签和一致性状态字段相关联的存储位置中。如果分配了与存储器块相关联的地址的归属系统存储器在第一相干域内，则确定。如果不是，则将一致性状态字段设置为指示地址标签有效的一致性状态，即存储位置不包含有效数据，第一相干域不包含家庭系统存储器，并且在形成一致性状态下，内存块被缓存在第一个相干域之外。

4. 发明申请

US20070083717A1 Chained cache coherency states for sequential homogeneous access to a cache line with outstanding data response 失效
标题翻译：链接高速缓存一致性状态用于对具有出色数据响应的高速缓存行进行顺序同步访问
公开(公告)号：US20070083717A1
公开(公告)日：2007-04-12
申请号：US11245313
申请日：2005-10-06
申请人： Ramakrishnan Rajamony , Hazim Shafi , Derek Williams , Kenneth Wright
发明人： Ramakrishnan Rajamony , Hazim Shafi , Derek Williams , Kenneth Wright
IPC分类号： G06F13/28
CPC分类号： G06F12/0831 , G06F12/0822
摘要： A method and data processing system for sequentially coupling successive, homogenous processor requests for a cache line in a chain before the data is received in the cache of a first processor within the chain. Chained intermediate coherency states are assigned to track the chain of processor requests and subsequent access permission provided, prior to receipt of the data at the first processor starting the chain. The chained intermediate coherency state assigned identifies the processor operation and a directional identifier identifies the processor to which the cache line is to be forwarded. When the data is received at the cache of the first processor within the chain, the first processor completes its operation on (or with) the data and then forwards the data to the next processor in the chain. The chain is immediately stopped when a non-homogenous operation is snooped by the last-in-chain processor.
摘要翻译：一种方法和数据处理系统，用于在数据在链中的第一处理器的高速缓存中接收之前，将链接中的高速缓存行的连续的均匀处理器请求顺序耦合。分配链接的中间一致性状态，以便在启动链路的第一个处理器接收到数据之前跟踪处理器请求链和后续访问权限。所分配的链接中间一致性状态标识处理器操作，并且方向标识符标识要向其转发高速缓存行的处理器。当在链中的第一处理器的高速缓存处接收数据时，第一处理器完成其数据处理（或与数据）的操作，然后将数据转发到链中的下一个处理器。当最后一个链接处理器窥探非均匀操作时，链条立即停止。

5. 发明申请

US20060277370A1 Data processing system and method for selectively updating an invalid coherency state in response to snooping a castout 有权
公开(公告)号：US20060277370A1
公开(公告)日：2006-12-07
申请号：US11146443
申请日：2005-06-06
申请人： Guy Guthrie , William Starke , Jeffrey Stuecheli , Derek Williams
发明人： Guy Guthrie , William Starke , Jeffrey Stuecheli , Derek Williams
IPC分类号： G06F13/28
CPC分类号： G06F12/0831 , G06F12/0813
摘要： In an entry of a first cache memory within a first coherency domain of a data processing system including at least first and second coherency domains, a coherency state field is set to a first state that indicates that an associated address tag is valid, an associated storage location does not contain valid data, and a memory block identified by the address tag is likely cached outside the first coherency domain. In response to snooping a castout operation, the first cache memory determines if the castout operation hits in the entry and, if so, updates the coherency state field from the first state to a second state indicating that the associated address tag is invalid.

6. 发明申请

US20060271742A1 Data processing system, cache system and method for actively scrubbing a domain indication 失效
公开(公告)号：US20060271742A1
公开(公告)日：2006-11-30
申请号：US11136651
申请日：2005-05-24
申请人： Leo Clark , James Fields , Guy Guthrie , William Starke , Derek Williams
发明人： Leo Clark , James Fields , Guy Guthrie , William Starke , Derek Williams
IPC分类号： G06F13/28
CPC分类号： G06F12/0817 , G06F12/0822
摘要： Scrubbing logic in a local coherency domain issues to at least one cache hierarchy in a remote coherency domain a domain reset request that forces invalidation of any cached copy of a target memory block then held in said remote coherency domain. A coherency response to said domain reset request is received. In response to said coherency response indicating that said target memory block is not cached in said remote coherency domain, a domain indication of said local coherency domain is updated to indicate that said target memory block is cached, if at all, only within said local coherency domain.

7. 发明申请

US20060190910A1 Method, system and program product providing a configuration specification language supporting arbitrary mapping functions for configuration constructs 有权
公开(公告)号：US20060190910A1
公开(公告)日：2006-08-24
申请号：US11408583
申请日：2006-04-21
申请人： Wolfgang Roesner , Derek Williams
发明人： Wolfgang Roesner , Derek Williams
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F17/5022
摘要： A method is disclosed of associating a mapping function with a configuration construct of a digital design defined by one or more hardware description language (HDL) files. According to the method, in the HDL files, a configuration latch is specified within a design entity forming at least a portion of the digital design. In addition, a Dial is specified that defines a relationship between each of a plurality of input values and a respective one of a plurality of different output values. The HDL files also include a statement that instantiates an instance of the Dial in association with the configuration latch such that a one-to-one correspondence exists between a value contained within the configuration latch and an input value of the instance of the Dial. The HDL files further include a statement associating the Dial with a mapping function that applies a selected transformation to values read from or written to the instance of the Dial.

8. 发明申请

US20060184748A1 Reducing number of rejected snoop requests by extending time to respond to snoop request 失效
公开(公告)号：US20060184748A1
公开(公告)日：2006-08-17
申请号：US11056740
申请日：2005-02-11
申请人： Benjiman Goodman , Guy Guthrie , William Starke , Jeffrey Stuecheli , Derek Williams
发明人： Benjiman Goodman , Guy Guthrie , William Starke , Jeffrey Stuecheli , Derek Williams
IPC分类号： G06F13/28
CPC分类号： G06F12/0831
摘要： A cache, system and method for reducing the number of rejected snoop requests. A “stall/reorder unit” in a cache receives a snoop request from an interconnect. Information, such as the address, of the snoop request is stored in a queue of the stall/reorder unit. The stall/reorder unit forwards the snoop request to a selector which also receives a request from a processor. An arbitration mechanism selects either the snoop request or the request from the processor. If the snoop request is denied by the arbitration mechanism, information, e.g., address, about the snoop request may be maintained in the stall/reorder unit. The request may be later resent to the selector. This process may be repeated up to “n” clock cycles. By providing the snoop request additional opportunities (n clock cycles) to be accepted by the arbitration mechanism, fewer snoop requests may ultimately be denied.

9. 发明申请

US20060179226A1 System and method of re-ordering store operations within a processor 失效
标题翻译：在处理器内重新排序存储操作的系统和方法
公开(公告)号：US20060179226A1
公开(公告)日：2006-08-10
申请号：US11054450
申请日：2005-02-09
申请人： Guy Guthrie , Hugh Shen , William Starke , Derek Williams
发明人： Guy Guthrie , Hugh Shen , William Starke , Derek Williams
IPC分类号： G06F12/00
CPC分类号： G06F9/3834 , G06F9/30043 , G06F9/3824 , G06F12/0817
摘要： A system and method for re-ordering store operations from a processor core to a store queue. When a store queue receives a new processor-issued store operation from the processor core, a store queue controller allocates a new entry in the store queue. In response to allocating the new entry in the store queue, the store queue controller determines whether or not the new entry is dependent on at least one other valid entry in the store queue. In response to determining the new entry is dependent on at least one other valid entry in the store queue, the store queue controller inhibits requesting of the new entry to the RC dispatch logic until each valid entry on which the new entry is dependent has been successfully dispatched to an RC machine by the RC dispatch logic.
摘要翻译：一种用于重新排序从处理器核到存储队列的存储操作的系统和方法。当存储队列从处理器核心接收到新的处理器发出的存储操作时，存储队列控制器在存储队列中分配新的条目。响应于在商店队列中分配新条目，商店队列控制器确定新条目是否依赖于商店队列中的至少一个其他有效条目。响应于确定新条目取决于存储队列中的至少一个其他有效条目，存储队列控制器禁止向RC调度逻辑请求新条目，直到新条目依赖于其上的每个有效条目已经成功通过RC调度逻辑调度到RC机器。

10. 发明申请

US20060122818A1 Method, system and program product for defining and recording threshold-qualified count events of a simulation by testcases 失效
标题翻译：方法，系统和程序产品，用于通过测试案例定义和记录模拟的阈值限定计数事件
公开(公告)号：US20060122818A1
公开(公告)日：2006-06-08
申请号：US11006093
申请日：2004-12-07
申请人： Michael Behm , Carol Gabele , Wolfgang Roesner , Derek Williams
发明人： Michael Behm , Carol Gabele , Wolfgang Roesner , Derek Williams
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： According to a one method of simulation processing, a count event counter for a count event is created within instrumentation of a hardware description language (HDL) simulation model of a design and a threshold greater than 1 is established for the count event counter. The design is then simulated utilizing the HDL simulation model, and occurrences of the count event are accumulated in the count event counter to obtain a count event value. Thereafter, an indication of whether the count event value of the count event exceeds the threshold is recorded within a data storage subsystem.
摘要翻译：根据模拟处理的一种方法，在设计的硬件描述语言（HDL）仿真模型的仪表内创建计数事件的计数事件计数器，并为计数事件计数器建立大于1的阈值。然后利用HDL仿真模型对该设计进行仿真，并且计数事件的发生被累积在计数事件计数器中以获得计数事件值。此后，计数事件的计数事件值是否超过阈值的指示被记录在数据存储子系统内。

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