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1. 发明申请

US20130313723A1 SEMICONDUCTOR CHIP LAYOUT WITH STAGGERED TX AND TX DATA LINESS 有权
标题翻译：带有STAGGERED TX和TX数据线的半导体芯片布局
公开(公告)号：US20130313723A1
公开(公告)日：2013-11-28
申请号：US13843427
申请日：2013-03-15
申请人： Michael J. Miller , Mark William Baumann , Richard S. Roy
发明人： Michael J. Miller , Mark William Baumann , Richard S. Roy
IPC分类号： H01L23/538
CPC分类号： H01L23/5384 , H01L23/49838 , H01L23/50 , H01L23/5286 , H01L23/5383 , H01L23/5386 , H01L2224/16225 , H01L2924/15311
摘要： A chip layout for a high speed semiconductor device is disclosed. The chip layout isolates Rx terminals and Rx ports from Tx terminals and Tx ports. A serial interface is centrally located to reduce latency, power and propagation delays. Stacked die that contain one or more devices with the chip layout are characterized by having improved latency, bandwidth, power consumption, and propagation delays.
摘要翻译：公开了一种用于高速半导体器件的芯片布局。芯片布局将Rx端子和Rx端口与Tx端子和Tx端口隔离。串行接口位于中心位置，以减少延迟，功率和传播延迟。包含一个或多个具有芯片布局的器件的堆叠裸片的特征在于具有改进的延迟，带宽，功耗和传播延迟。

2. 发明授权

US08901747B2 Semiconductor chip layout 有权
标题翻译：半导体芯片布局
公开(公告)号：US08901747B2
公开(公告)日：2014-12-02
申请号：US12846763
申请日：2010-07-29
申请人： Michael J. Miller , Mark Baumann , Richard S. Roy
发明人： Michael J. Miller , Mark Baumann , Richard S. Roy
IPC分类号： H01L29/40 , H01L23/50
CPC分类号： H01L23/50 , H01L2924/0002 , H01L2924/00
摘要： A chip layout for a high speed semiconductor device is disclosed. The chip layout isolates Rx terminals and Rx ports from Tx terminals and Tx ports. A serial interface is centrally located to reduce latency, power and propagation delays. Stacked die that contain one or more devices with the chip layout are characterized by having improved latency, bandwidth, power consumption, and propagation delays.
摘要翻译：公开了一种用于高速半导体器件的芯片布局。芯片布局将Rx端子和Rx端口与Tx端子和Tx端口隔离。串行接口位于中心位置，以减少延迟，功率和传播延迟。包含一个或多个具有芯片布局的器件的堆叠裸片的特征在于具有改进的延迟，带宽，功耗和传播延迟。

3. 发明授权

US08890332B2 Semiconductor chip layout with staggered Tx and Tx data lines 有权
标题翻译：具有交错Tx和Tx数据线的半导体芯片布局
公开(公告)号：US08890332B2
公开(公告)日：2014-11-18
申请号：US13843427
申请日：2013-03-15
申请人： Michael J. Miller , Mark William Baumann , Richard S. Roy
发明人： Michael J. Miller , Mark William Baumann , Richard S. Roy
IPC分类号： H01L29/40
CPC分类号： H01L23/5384 , H01L23/49838 , H01L23/50 , H01L23/5286 , H01L23/5383 , H01L23/5386 , H01L2224/16225 , H01L2924/15311
摘要： A chip layout for a high speed semiconductor device is disclosed. The chip layout isolates Rx terminals and Rx ports from Tx terminals and Tx ports. A serial interface is centrally located to reduce latency, power and propagation delays. Stacked die that contain one or more devices with the chip layout are characterized by having improved latency, bandwidth, power consumption, and propagation delays.
摘要翻译：公开了一种用于高速半导体器件的芯片布局。芯片布局将Rx端子和Rx端口与Tx端子和Tx端口隔离。串行接口位于中心位置，以减少延迟，功率和传播延迟。包含一个或多个具有芯片布局的器件的堆叠裸片的特征在于具有改进的延迟，带宽，功耗和传播延迟。

4. 发明申请

US20110191548A1 High Utilization Multi-Partitioned Serial Memory 有权
标题翻译：高利用多分区串行存储器
公开(公告)号：US20110191548A1
公开(公告)日：2011-08-04
申请号：US12697141
申请日：2010-01-29
申请人： Michael J. Miller , Richard S. Roy
发明人： Michael J. Miller , Richard S. Roy
IPC分类号： G06F12/08 , G06F13/12
CPC分类号： G06F13/1647
摘要： A memory device that includes an input interface that receives instructions and input data on a first plurality of serial links. The instructions and input data are deserialized on the memory device, and are provided to a memory controller. The memory controller initiates accesses to a memory core in response to the received instructions. The memory core includes a plurality of memory partitions, which are accessed in a cyclic and overlapping manner. This allows each memory partition to operate at a slower frequency than the serial links, while properly servicing the received instructions. Accesses to the memory device are performed in a synchronous manner, wherein each access exhibits a known fixed latency.
摘要翻译：一种存储装置，包括在第一多个串行链路上接收指令和输入数据的输入接口。指令和输入数据在存储器件上反序列化，并被提供给存储器控制器。存储器控制器响应于接收的指令启动对存储器内核的访问。存储器核心包括以循环和重叠的方式访问的多个存储器分区。这允许每个存储器分区以比串行链路更低的频率工作，同时正确地维护接收到的指令。以同步方式执行对存储设备的访问，其中每个访问呈现已知的固定等待时间。

5. 发明授权

US08368217B2 Integrated circuit package with segregated Tx and Rx data channels 有权
标题翻译：集成电路封装，具有隔离的Tx和Rx数据通道
公开(公告)号：US08368217B2
公开(公告)日：2013-02-05
申请号：US13541658
申请日：2012-07-03
申请人： Michael J. Miller , Mark William Baumann , Richard S. Roy
发明人： Michael J. Miller , Mark William Baumann , Richard S. Roy
IPC分类号： H01L23/48
CPC分类号： H01L23/50 , H01L2924/0002 , H01L2924/00
摘要： A chip layout isolates Rx terminals and Rx ports from Tx terminals and Tx ports. Tx terminals are grouped contiguously to each other, and are segregated as a group to a given edge of the package, Rx terminals are similarly grouped and segregated to a different edge of the package. Tx and Rx data channels are disposed in a respective single layer of the package, or both are disposed in a same single layer of the package. Rx ports and Tx ports are located at an approximate center of the package, with Tx and Rx ports disposed on respective opposite sides of an axis bisecting the package. Data signals received by, and transmitted from, the chip flow in a same direction, from a first edge of the package to the center of the package and from the center of the package to a second edge of the package, respectively.
摘要翻译：芯片布局将Rx端子和Rx端口与Tx端子和Tx端口隔离。 Tx端子彼此连续分组，并且作为组分离到包装的给定边缘，Rx端子被类似地分组并分离到包装的不同边缘。 Tx和Rx数据通道设置在封装的相应单层中，或者两者都被布置在封装的相同的单层中。 Rx端口和Tx端口位于封装的大致中心处，Tx和Rx端口设置在平分封装的轴的相应相对两侧。分别从包装的第一边缘到包装的中心以及从包装的中心到包装的第二边缘的相同方向从芯片流接收和传输的数据信号。

6. 发明申请

US20120267769A1 INTEGRATED CIRCUIT PACKAGE WITH SEGREGATED TX AND RX DATA CHANNELS 有权
标题翻译：集成电路封装与分离的TX和RX数据通道
公开(公告)号：US20120267769A1
公开(公告)日：2012-10-25
申请号：US13541658
申请日：2012-07-03
申请人： Michael J. Miller , Mark Baumann , Richard S. Roy
发明人： Michael J. Miller , Mark Baumann , Richard S. Roy
IPC分类号： H01L23/58
CPC分类号： H01L23/50 , H01L2924/0002 , H01L2924/00
摘要： A chip layout isolates Rx terminals and Rx ports from Tx terminals and Tx ports. Tx terminals are grouped contiguously to each other, and are segregated as a group to a given edge of the package, Rx terminals are similarly grouped and segregated to a different edge of the package. Tx and Rx data channels are disposed in a respective single layer of the package, or both are disposed in a same single layer of the package. Rx ports and Tx ports are located at an approximate center of the package, with Tx and Rx ports disposed on respective opposite sides of an axis bisecting the package. Data signals received by, and transmitted from, the chip flow in a same direction, from a first edge of the package to the center of the package and from the center of the package to a second edge of the package, respectively.
摘要翻译：芯片布局将Rx端子和Rx端口与Tx端子和Tx端口隔离。 Tx端子彼此连续分组，并且作为组分离到包装的给定边缘，Rx端子被类似地分组并分离到包装的不同边缘。 Tx和Rx数据通道设置在封装的相应单层中，或者两者都被布置在封装的相同的单层中。 Rx端口和Tx端口位于封装的大致中心处，Tx和Rx端口设置在平分封装的轴的相应相对两侧。分别从包装的第一边缘到包装的中心以及从包装的中心到包装的第二边缘的相同方向从芯片流接收和传输的数据信号。

7. 发明授权

US09342471B2 High utilization multi-partitioned serial memory 有权
标题翻译：高利用率多分区串行存储器
公开(公告)号：US09342471B2
公开(公告)日：2016-05-17
申请号：US12697141
申请日：2010-01-29
申请人： Michael J. Miller , Richard S. Roy
发明人： Michael J. Miller , Richard S. Roy
IPC分类号： G06F12/00 , G06F13/16
CPC分类号： G06F13/1647
摘要： A memory device that includes an input interface that receives instructions and input data on a first plurality of serial links. The instructions and input data are deserialized on the memory device, and are provided to a memory controller. The memory controller initiates accesses to a memory core in response to the received instructions. The memory core includes a plurality of memory partitions, which are accessed in a cyclic and overlapping manner. This allows each memory partition to operate at a slower frequency than the serial links, while properly servicing the received instructions. Accesses to the memory device are performed in a synchronous manner, wherein each access exhibits a known fixed latency.
摘要翻译：一种存储装置，包括在第一多个串行链路上接收指令和输入数据的输入接口。指令和输入数据在存储器件上反序列化，并被提供给存储器控制器。存储器控制器响应于接收的指令启动对存储器内核的访问。存储器核心包括以循环和重叠的方式访问的多个存储器分区。这允许每个存储器分区以比串行链路更低的频率工作，同时正确地维护接收到的指令。以同步方式执行对存储设备的访问，其中每个访问呈现已知的固定等待时间。

8. 发明授权

US08446755B2 Multiple cycle memory write completion 有权
标题翻译：多周期内存写入完成
公开(公告)号：US08446755B2
公开(公告)日：2013-05-21
申请号：US13369253
申请日：2012-02-08
申请人： Richard S. Roy
发明人： Richard S. Roy
IPC分类号： G11C11/24 , G11C7/00 , G11C8/00
CPC分类号： G11C7/1015 , G11C11/406 , G11C11/40618 , G11C2207/229
摘要： A memory system that reduces the memory cycle time of a memory cell by performing an incomplete write operation. The voltage on a storage node of the memory cell does not reach a full supply voltage during the incomplete write operation. The incomplete write operation is subsequently completed by one or more additional accesses, wherein the voltage on the storage node is pulled to a full supply voltage. The incomplete write operation may be completed by: subsequently writing the same data to the memory cell during an idle cycle; subsequently writing data to other memory cells in the same row as the memory cell; subsequently reading data from the row that includes the memory cell; or refreshing the row that includes the memory cell during an idle cycle. One or more idle cycles may be forced to cause the incomplete write operation to be completed in a timely manner.
摘要翻译：一种通过执行不完整的写入操作来减少存储器单元的存储器周期时间的存储器系统。在不完全写入操作期间，存储单元的存储节点上的电压未达到全电源电压。随后通过一个或多个附加访问完成不完整的写入操作，其中存储节点上的电压被拉至完全电源电压。可以通过以下方式完成不完整的写入操作：随后在空闲周期期间将相同的数据写入存储器单元; 随后将数据写入到与存储器单元相同的行中的其他存储单元; 随后从包括存储器单元的行读取数据; 或者在空闲周期期间刷新包含存储单元的行。可能会迫使一个或多个空闲周期及时完成不完整的写入操作。

9. 发明申请

US20110191564A1 Hierarchical Organization Of Large Memory Blocks 有权
标题翻译：大内存块的分层结构
公开(公告)号：US20110191564A1
公开(公告)日：2011-08-04
申请号：US12697132
申请日：2010-01-29
申请人： Richard S. Roy
发明人： Richard S. Roy
IPC分类号： G06F12/00 , G06F12/02
CPC分类号： G11C11/408 , G11C5/025 , G11C5/063 , G11C7/1006 , G11C7/1039 , G11C7/1042 , G11C7/1069 , G11C7/1096 , G11C11/4096 , G11C11/4097
摘要： A multi-bank memory system includes one or more levels of logical memory hierarchy to increase the available random cyclic transaction rate of the memory system. The memory system includes a plurality of multi-bank partitions, each having a corresponding partition interface. Each partition interface accesses the corresponding multi-bank partition at a first frequency. A global interface may access the partition interfaces at a second frequency, which is equal to the first frequency times the number of partition interfaces. Alternately, a plurality of cluster interfaces may access corresponding groups of the partition interfaces, wherein each cluster interface accesses the corresponding group of partition interfaces at a second frequency that is faster than the first frequency. A global interface accesses the cluster interfaces at a third frequency that is greater than the second frequency.
摘要翻译：多存储存储器系统包括一个或多个逻辑存储器层级以增加存储器系统的可用随机循环事务速率。存储器系统包括多个多块分区，每个分区具有对应的分区接口。每个分区接口以第一个频率访问相应的多存储体分区。全局接口可以以等于第一个频率乘以分区接口数的第二个频率访问分区接口。或者，多个集群接口可以访问分区接口的相应组，其中每个集群接口以比第一频率快的第二频率访问对应的分组接口组。全局接口以大于第二个频率的第三个频率访问集群接口。

10. 发明授权

US06499121B1 Distributed interface for parallel testing of multiple devices using a single tester channel 失效
标题翻译：分布式接口，用于使用单个测试仪通道并行测试多个设备
公开(公告)号：US06499121B1
公开(公告)日：2002-12-24
申请号：US09260463
申请日：1999-03-01
申请人： Richard S. Roy , Charles A. Miller
发明人： Richard S. Roy , Charles A. Miller
IPC分类号： G01R3128
CPC分类号： G11C29/48 , G01R31/31905 , G01R31/31926 , G01R31/3193 , G11C29/56 , G11C2029/2602 , G11C2029/5606 , H01L2224/16225
摘要： A system for testing a number of integrated circuit (IC) devices under test (DUTs) having interface circuitry coupled to a single or multi-channel tester for receiving data values from the tester and providing error information concerning the DUTs. The interface circuitry forwards data values (received from the tester over a single channel) to a number of DUTs in parallel. The circuitry performs comparisons using data values read from the DUTs, and in response generates error values indicative of the comparison. The error values may then be returned to the tester over the same or a different channel.
摘要翻译：一种用于测试许多被测试的集成电路（IC）器件（DUT）的系统，其具有耦合到单通道或多通道测试器的接口电路，用于从测试器接收数据值并提供关于DUT的错误信息。接口电路将数据值（通过单个通道从测试仪接收）并行转发到多个DUT。该电路使用从DUT读取的数据值执行比较，并且响应于产生指示比较的误差值。然后可以通过相同或不同的通道将错误值返回给测试仪。

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