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1. 发明申请

US20050266664A1 Method for forming a fully silicided semiconductor device 审中-公开
标题翻译：形成全硅化半导体器件的方法
公开(公告)号：US20050266664A1
公开(公告)日：2005-12-01
申请号：US10857726
申请日：2004-05-28
申请人： Michael Harrison , Olubunmi Adetutu , Sam Garcia
发明人： Michael Harrison , Olubunmi Adetutu , Sam Garcia
IPC分类号： H01L21/28 , H01L21/324 , H01L21/44
CPC分类号： H01L21/324 , H01L21/28097
摘要： A method for forming an improved fully silicided gate electrode in a semiconductor device in which the fully silicided gate electrode is formed using indirect heating. One embodiment relates to a method of manufacturing at least one semiconductor device. The method includes depositing silicon to a first thickness, depositing metal over the silicon, and indirectly heating the metal and silicon to form a metal silicide having a second thickness not less than the first thickness. Another embodiment relates to a method of manufacturing semiconductor devices, each semiconductor device having a fully silicided control electrode. The method includes providing a substrate, forming a dielectric layer over the substrate, forming a silicon-containing layer over the dielectric layer, depositing a metal-containing layer over the silicon-containing layer, and indirectly heating the metal-containing and silicon-containing layers to form a silicide layer in contact with the dielectric layer.
摘要翻译：一种在半导体器件中形成改进的全硅化物栅电极的方法，其中使用间接加热形成全硅化栅电极。一个实施例涉及制造至少一个半导体器件的方法。该方法包括将硅沉积到第一厚度，在硅上沉积金属，并间接加热金属和硅以形成具有不小于第一厚度的第二厚度的金属硅化物。另一实施例涉及制造半导体器件的方法，每个半导体器件具有完全硅化的控制电极。该方法包括提供衬底，在衬底上形成电介质层，在电介质层上形成含硅层，在含硅层上沉积含金属层，并间接加热含金属和含硅的以形成与介电层接触的硅化物层。

2. 发明申请

US20070042546A1 Method for forming floating gates within NVM process 有权
标题翻译：在NVM过程中形成浮动门的方法
公开(公告)号：US20070042546A1
公开(公告)日：2007-02-22
申请号：US11208670
申请日：2005-08-22
申请人： Jeffrey Thomas , Olubunmi Adetutu
发明人： Jeffrey Thomas , Olubunmi Adetutu
IPC分类号： H01L21/336
CPC分类号： H01L21/28123 , H01L21/28273 , H01L27/115 , H01L27/11521
摘要： A semiconductor process and apparatus includes forming a semiconductor device by depositing a layer of nitride (20) over a semiconductor structure (10), patterning and etching the nitride layer to form a patterned nitride layer (42, 44), depositing a layer of polysilicon (62), planarizing the polysilicon layer with a CMP process to remove any portion of the polysilicon layer (62) above the patterned dielectric layer (42, 44), and then removing the patterned nitride layer (42, 44), thereby defining one or more polysilicon features (72, 74, 76) that can be used as floating gates, transistors gates, bit lines or any other semiconductor device feature.
摘要翻译：半导体工艺和设备包括通过在半导体结构（10）上沉积氮化物层（20）来形成半导体器件，图案化和蚀刻氮化物层以形成图案化氮化物层（42,44），沉积多晶硅层（62），用CMP工艺平坦化多晶硅层，以去除图案化的介电层（42,44）上方的多晶硅层（62）的任何部分，然后去除图案化的氮化物层（42,44），由此限定一个或更多个可用作浮动栅极，晶体管栅极，位线或任何其它半导体器件特征的多晶硅特征（72,74,76）。

3. 发明申请

US20060273411A1 In-situ nitridation of high-k dielectrics 有权
标题翻译：高k电介质的原位氮化
公开(公告)号：US20060273411A1
公开(公告)日：2006-12-07
申请号：US11146826
申请日：2005-06-07
申请人： Dina Triyoso , Olubunmi Adetutu , Hsing Tseng
发明人： Dina Triyoso , Olubunmi Adetutu , Hsing Tseng
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/517 , H01L21/28194 , H01L21/28202 , H01L21/28229 , H01L29/513 , H01L29/518 , H01L29/78
摘要： A semiconductor fabrication process for forming a gate dielectric includes depositing a high-k dielectric stack including incorporating nitrogen into the high-k dielectric stack in-situ. A top high-k dielectric is formed overlying the dielectric stack and the dielectric stack and the top dielectric are annealed. Depositing the dielectric stack may include depositing a plurality of high-k dielectric layers where each layer is formed in a distinct processing step or set of steps. Depositing one of the dielectric layers may include performing a plurality of atomic layer deposition processes to form a plurality of high-k sublayers, wherein each sublayer is a monolayer film. Depositing the plurality of sublayers may include depositing a nitrogen free sublayer and depositing a nitrogen bearing sublayer. Depositing the nitrogen free sublayer may include pulsing an ALD chamber with HfCl4, purging the chamber with an inert, pulsing the chamber with an H2O or D2O, and purging the chamber with an inert.
摘要翻译：用于形成栅极电介质的半导体制造工艺包括沉积高k电介质堆叠，其包括将氮掺杂到原位的高k电介质堆叠中。形成覆盖在电介质堆叠上的顶部高k电介质，并且电介质堆叠和顶部电介质被退火。沉积介质堆叠可以包括沉积多个高k电介质层，其中每个层以不同的处理步骤或一组步骤形成。沉积一个电介质层可以包括执行多个原子层沉积工艺以形成多个高k子层，其中每个子层是单层膜。沉积多个子层可以包括沉积无氮的子层并沉积含氮的子层。沉积无氮子层可以包括用HfCl 4脉冲发射ALD室，用惰性气体冲洗室，用H 2 O 2或D 2 并且用惰性气体清洗室。

4. 发明申请

US20060110892A1 Semiconductor process for forming stress absorbent shallow trench isolation structures 有权
标题翻译：用于形成应力吸收性浅沟槽隔离结构的半导体工艺
公开(公告)号：US20060110892A1
公开(公告)日：2006-05-25
申请号：US10996319
申请日：2004-11-22
申请人： Marius Orlowski , Mark Foisy , Olubunmi Adetutu
发明人： Marius Orlowski , Mark Foisy , Olubunmi Adetutu
IPC分类号： H01L21/76
CPC分类号： H01L29/7842 , H01L21/76224 , H01L21/76229 , H01L21/823807 , H01L21/823878
摘要： A semiconductor fabrication process includes patterning a hard mask over a semiconductor substrate to expose an isolation region and forming a trench in the isolation region. A flowable dielectric is deposited in the trench to partially fill the trench and a capping dielectric is deposited overlying the first oxide to fill the trench. The substrate may be a silicon on insulator (SOI) substrate including a buried oxide (BOX) layer and the trench may extend partially into the BOX layer. The flowable dielectric may be a spin deposited flowable oxide or a CVD BPSG oxide. The flowable dielectric isolation structure provides a buffer that prevents stress induced on one side of the isolation structure from creating stress on the other side of the structure. Thus, for example, compressive stress created by forming silicon germanium on silicon in PMOS regions does not create compressive stress in NMOS regions.
摘要翻译：半导体制造工艺包括在半导体衬底上图案化硬掩模以暴露隔离区域并在隔离区域中形成沟槽。在沟槽中沉积可流动电介质以部分地填充沟槽，并且覆盖覆盖第一氧化物的覆盖电介质以填充沟槽。衬底可以是包括掩埋氧化物（BOX）层的绝缘体上硅（SOI）衬底，并且沟槽可以部分地延伸到BOX层中。可流动电介质可以是自旋沉积的可流动氧化物或CVD BPSG氧化物。可流动介电隔离结构提供了缓冲器，其防止在隔离结构的一侧上引起的应力在结构的另一侧上产生应力。因此，例如，通过在PMOS区域中的硅上形成硅锗产生的压缩应力在NMOS区域中不产生压应力。

5. 发明申请

US20060094259A1 Forming gas anneal process for high dielectric constant gate dielectrics in a semiconductor fabrication process 审中-公开
标题翻译：在半导体制造工艺中形成用于高介电常数栅极电介质的气体退火工艺
公开(公告)号：US20060094259A1
公开(公告)日：2006-05-04
申请号：US10980445
申请日：2004-11-03
申请人： David Gilmer , Olubunmi Adetutu , Hsing Tseng
发明人： David Gilmer , Olubunmi Adetutu , Hsing Tseng
IPC分类号： H01L21/4763 , H01L21/31 , H01L21/469
CPC分类号： H01L21/02318 , H01L21/02123 , H01L21/02178 , H01L21/02181 , H01L21/28185 , H01L21/31645 , H01L29/517 , H01L29/6659 , H01L29/7833
摘要： A semiconductor fabrication annealing process includes depositing a high dielectric constant gate dielectric over a substrate and annealing the gate dielectric. Annealing the gate dielectric includes exposing the gate dielectric to an inert ambient and ramping the inert ambient to an annealing temperature. A passivating gas is then introduced into the ambient while maintaining the ambient at the annealing temperature. This passivating ambient is then maintained at the annealing temperature for a specified duration. While maintaining the presence of the passivating gas in the ambient, the ambient temperature is then ramped down from the annealing temperature to a second temperature, which is preferably less than 100° C. The passivating gas is preferably hydrogen gas, deuterium gas, or a combination of the two. The annealing temperature is preferably greater than approximately 470° C.
摘要翻译：半导体制造退火工艺包括在衬底上沉积高介电常数栅极电介质并退火栅极电介质。对栅极电介质进行退火包括将栅极电介质暴露于惰性环境，并将惰性环境升温至退火温度。然后将钝化气体引入环境中，同时保持环境处于退火温度。然后将该钝化环境在退火温度下保持规定的持续时间。在保持环境中的钝化气体的存在的同时，环境温度然后从退火温度下降到第二温度，其优选小于100℃。钝化气体优选为氢气，氘气或两者的结合。退火温度优选大于约470℃

6. 发明申请

US20050277294A1 Method for treating a semiconductor surface to form a metal-containing layer 有权
标题翻译：用于处理半导体表面以形成含金属层的方法
公开(公告)号：US20050277294A1
公开(公告)日：2005-12-15
申请号：US10865268
申请日：2004-06-10
申请人： James Schaeffer , Darrell Roan , Dina Triyoso , Olubunmi Adetutu
发明人： James Schaeffer , Darrell Roan , Dina Triyoso , Olubunmi Adetutu
IPC分类号： C23C16/02 , H01L21/314 , H01L21/316 , H01L21/44
CPC分类号： H01L21/02181 , C23C16/0272 , H01L21/3141 , H01L21/31645
摘要： A method for treating a semiconductor surface to form a metal-containing layer includes providing a semiconductor substrate having an exposed surface. The exposed surface of the semiconductor substrate is treated by forming one or more metals overlying the semiconductor substrate but not completely covering the exposed surface of the semiconductor substrate. The one or more metals enhance nucleation for subsequent material growth. A metal-containing layer is formed on the exposed surface of the semiconductor substrate that has been treated. The treatment of the exposed surface of the semiconductor substrate assists the metal-containing layer to coalesce. In one embodiment, treatment of the exposed surface to enhance nucleation may be performed by spin-coating, atomic layer deposition (ALD), physical layer deposition (PVD), electroplating, or electroless plating. The one or more metals used to treat the exposed surface may include any rare earth or transition metal, such as, for example, hafnium, lanthanum, etc.
摘要翻译：一种用于处理半导体表面以形成含金属层的方法包括提供具有暴露表面的半导体衬底。半导体衬底的暴露表面通过形成覆盖半导体衬底但不完全覆盖半导体衬底的暴露表面的一种或多种金属来处理。一种或多种金属增强成核以用于随后的材料生长。在已经处理的半导体衬底的暴露表面上形成含金属层。半导体衬底的暴露表面的处理有助于含金属层的聚结。在一个实施方案中，可以通过旋涂，原子层沉积（ALD），物理层沉积（PVD），电镀或无电镀来进行暴露表面的处理以增强成核。用于处理暴露表面的一种或多种金属可以包括任何稀土或过渡金属，例如铪，镧等。

7. 发明授权

US06376349B1 Process for forming a semiconductor device and a conductive structure 有权
标题翻译：用于形成半导体器件和导电结构的工艺
公开(公告)号：US06376349B1
公开(公告)日：2002-04-23
申请号：US09487472
申请日：2000-01-19
申请人： Philip J. Tobin , Olubunmi Adetutu , Bikas Maiti
发明人： Philip J. Tobin , Olubunmi Adetutu , Bikas Maiti
IPC分类号： H01L213205
CPC分类号： H01L29/4958 , H01L21/28079
摘要： Semiconductor devices and conductive structures can be formed having a metallic layer. In one embodiment, a semiconductor device includes an amorphous metallic layer (22) and a crystalline metallic layer (42). The amorphous metallic layer (22) helps to reduce the likelihood of penetration of contaminants through the amorphous metallic layer (22). A more conductive crystalline metallic layer (42) can be formed on the amorphous metallic layer (22) to help keep resistivity relatively low. When forming a conductive structure, a metal-containing gas and a scavenger gas flow simultaneously during at least one point in time. The conductive structure may be part of a gate electrode.
摘要翻译：可以形成具有金属层的半导体器件和导电结构。在一个实施例中，半导体器件包括非晶金属层（22）和结晶金属层（42）。无定形金属层（22）有助于降低污染物穿过非晶金属层（22）的可能性。可以在非晶金属层（22）上形成更导电的晶体金属层（42），以帮助保持电阻率相对较低。当形成导电结构时，含金属的气体和清除气体在至少一个时间点内同时流动。导电结构可以是栅电极的一部分。

8. 发明授权

US5888588A Process for forming a semiconductor device 失效
标题翻译：用于形成半导体器件的工艺
公开(公告)号：US5888588A
公开(公告)日：1999-03-30
申请号：US828638
申请日：1997-03-31
申请人： Rajan Nagabushnam , Olubunmi Adetutu , Yeong-Jyh Tom Lii
发明人： Rajan Nagabushnam , Olubunmi Adetutu , Yeong-Jyh Tom Lii
IPC分类号： C23C16/34 , H01L21/28 , H01L29/49 , C23C16/00 , H01L21/285
CPC分类号： C23C16/34 , H01L21/28061 , H01L29/4941
摘要： A semiconductor device (10) includes a gate electrode (61) having a silicon/tungsten nitride/tungsten silicon nitride/tungsten silicide composition. The tungsten nitride film (21) and tungsten suicide film (23) are formed using chemical vapor deposition (CVD). The tungsten nitride film is formed using a tungsten halide and N.sub.2 R.sup.1 R.sup.2, where each of R.sup.1 and R.sup.2 is hydrogen, an alkyl group, an alkenyl group, or an alkynyl group. The tungsten nitride film (21) is an etch stop when patterning the tungsten silicide film (23). The CVD tungsten nitride film (21) helps to improve gate dielectric integrity and reduces interface traps when compared to a sputtered tungsten nitride film (21). Also, N.sub.2 R.sup.1 R.sup.2 can be used to remove halogens that are adsorbed onto walls of a reaction chamber than is cleaned between depositions of substrates.
摘要翻译：半导体器件（10）包括具有硅/氮化钨/氮化钨/硅化钨组合物的栅电极（61）。使用化学气相沉积（CVD）形成氮化钨膜（21）和硅化钨膜（23）。氮化钨膜使用卤化钨和N 2 R 1 R 2形成，其中R 1和R 2各自为氢，烷基，烯基或炔基。当图案化硅化钨膜（23）时，氮化钨膜（21）是蚀刻停止层。与溅射的氮化钨膜（21）相比，CVD氮化钨膜（21）有助于提高栅极电介质完整性并减少界面陷阱。此外，N2R1R2可用于除去吸附到反应室壁上的卤素，而不是在底物沉积之间清洗的卤素。

9. 发明申请

US20080048270A1 ELECTRONIC DEVICE COMPRISING A GATE ELECTRODE INCLUDING A METAL-CONTAINING LAYER HAVING ONE OR MORE IMPURITIES 有权
标题翻译：包含门电极的电子设备，包括具有一个或更多污染物的含金属的层
公开(公告)号：US20080048270A1
公开(公告)日：2008-02-28
申请号：US11928314
申请日：2007-10-30
申请人： Olubunmi Adetutu , David Gilmer , Philip Tobin
发明人： Olubunmi Adetutu , David Gilmer , Philip Tobin
IPC分类号： H01L29/76
CPC分类号： H01L21/823857 , H01L21/823842
摘要： One or more impurities may be incorporated within a metal-containing layer of a metal-containing gate electrode to modify the work function of the metal-containing gate electrode of a transistor can affect the threshold voltage of the transistor. In one embodiment, the impurity can be used in a p-channel transistor to allow the work function of a metal-containing gate electrode to be closer to the valence band for silicon. In another embodiment, the impurity can be used in an n-channel transistor to allow the work function of a metal-containing gate electrode to be closer to the conduction band for silicon. In a particular embodiment, a boron-containing species is implanted into a metal-containing layer within the metal-containing gate electrode within a p-channel transistor, so that the metal-containing gate electrode has a work function closer to the valence band for silicon as compared to the metal-containing gate electrode without the boron-containing species.
摘要翻译：可以在含金属的栅电极的含金属层内并入一种或多种杂质以改变晶体管的含金属栅电极的功函数可影响晶体管的阈值电压。在一个实施例中，杂质可用于p沟道晶体管，以允许含金属的栅电极的功函数更接近硅的价带。在另一实施例中，杂质可用于n沟道晶体管，以允许含金属的栅电极的功函数更接近于硅的导带。在一个具体的实施方案中，将含硼物质注入到在p沟道晶体管内的含金属栅电极内的含金属层中，使得含金属栅电极具有更接近价带的功函数与没有含硼物质的含金属栅电极相比。

10. 发明申请

US20070134891A1 SOI active layer with different surface orientation 有权
标题翻译：具有不同表面取向的SOI活性层
公开(公告)号：US20070134891A1
公开(公告)日：2007-06-14
申请号：US11302770
申请日：2005-12-14
申请人： Olubunmi Adetutu , Robert Jones , Ted White
发明人： Olubunmi Adetutu , Robert Jones , Ted White
IPC分类号： H01L21/00
CPC分类号： H01L21/76254 , H01L21/02002
摘要： A wafer having an SOI configuration and active regions having different surface orientations for different channel type transistors. In one example, semiconductor structures having a first surface orientation are formed on a donor wafer. Semiconductor structures having a second surface orientation are formed on a second wafer. Receptor openings are formed on the second wafer. The semiconductor structures having the first surface orientation are located in the receptor openings and transferred to the second wafer. The resultant wafer has semiconductor regions having a first surface orientation for a first channel type of transistor and semiconductor regions having a second surface orientation for a second channel type transistor.
摘要翻译：具有SOI配置的晶片和对不同沟道型晶体管具有不同表面取向的有源区。在一个示例中，在施主晶片上形成具有第一表面取向的半导体结构。具有第二表面取向的半导体结构形成在第二晶片上。受体开口形成在第二晶片上。具有第一表面取向的半导体结构位于接收器开口中并被转移到第二晶片。所得到的晶片具有用于第一沟道型晶体管的具有第一表面取向的半导体区域和具有用于第二沟道型晶体管的第二表面取向的半导体区域。

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