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1. 发明申请

US20080048270A1 ELECTRONIC DEVICE COMPRISING A GATE ELECTRODE INCLUDING A METAL-CONTAINING LAYER HAVING ONE OR MORE IMPURITIES 有权
标题翻译：包含门电极的电子设备，包括具有一个或更多污染物的含金属的层
公开(公告)号：US20080048270A1
公开(公告)日：2008-02-28
申请号：US11928314
申请日：2007-10-30
申请人： Olubunmi Adetutu , David Gilmer , Philip Tobin
发明人： Olubunmi Adetutu , David Gilmer , Philip Tobin
IPC分类号： H01L29/76
CPC分类号： H01L21/823857 , H01L21/823842
摘要： One or more impurities may be incorporated within a metal-containing layer of a metal-containing gate electrode to modify the work function of the metal-containing gate electrode of a transistor can affect the threshold voltage of the transistor. In one embodiment, the impurity can be used in a p-channel transistor to allow the work function of a metal-containing gate electrode to be closer to the valence band for silicon. In another embodiment, the impurity can be used in an n-channel transistor to allow the work function of a metal-containing gate electrode to be closer to the conduction band for silicon. In a particular embodiment, a boron-containing species is implanted into a metal-containing layer within the metal-containing gate electrode within a p-channel transistor, so that the metal-containing gate electrode has a work function closer to the valence band for silicon as compared to the metal-containing gate electrode without the boron-containing species.
摘要翻译：可以在含金属的栅电极的含金属层内并入一种或多种杂质以改变晶体管的含金属栅电极的功函数可影响晶体管的阈值电压。在一个实施例中，杂质可用于p沟道晶体管，以允许含金属的栅电极的功函数更接近硅的价带。在另一实施例中，杂质可用于n沟道晶体管，以允许含金属的栅电极的功函数更接近于硅的导带。在一个具体的实施方案中，将含硼物质注入到在p沟道晶体管内的含金属栅电极内的含金属层中，使得含金属栅电极具有更接近价带的功函数与没有含硼物质的含金属栅电极相比。

2. 发明申请

US20070178633A1 Semiconductor device comprising a transistor having a counter-doped channel region and method for forming the same 有权
标题翻译：包括具有反掺杂沟道区的晶体管的半导体器件及其形成方法
公开(公告)号：US20070178633A1
公开(公告)日：2007-08-02
申请号：US11342025
申请日：2006-01-27
申请人： Olubunmi Adetutu , David Gilmer , Philip Tobin
发明人： Olubunmi Adetutu , David Gilmer , Philip Tobin
IPC分类号： H01L21/8238
CPC分类号： H01L21/823807 , H01L21/823842
摘要： A method for making a semiconductor device includes providing a first substrate region and a second substrate region, wherein at least a part of the first substrate region has a first conductivity type and at least a part of the second substrate region has a second conductivity type different from the first conductivity type. The method further includes forming a dielectric layer over at least a portion of the first substrate region and at least a portion of the second substrate region. The method further includes forming a metal-containing gate layer over at least a portion of the dielectric layer overlying the first substrate region. The method further includes introducing dopants into at least a portion of the first substrate region through the metal-containing gate layer.
摘要翻译：一种制造半导体器件的方法包括提供第一衬底区域和第二衬底区域，其中第一衬底区域的至少一部分具有第一导电类型，并且第二衬底区域的至少一部分具有不同的第二导电类型从第一导电类型。该方法还包括在第一衬底区域的至少一部分和第二衬底区域的至少一部分上形成电介质层。该方法还包括在覆盖第一衬底区域的介电层的至少一部分上形成含金属的栅极层。该方法还包括通过含金属的栅极层将掺杂剂引入到第一衬底区域的至少一部分中。

3. 发明申请

US20060172516A1 Electronic device comprising a gate electrode including a metal-containing layer having one or more impurities and a process for forming the same 有权
标题翻译：电子器件包括含有含有一种或多种杂质的含金属层的栅电极及其形成方法
公开(公告)号：US20060172516A1
公开(公告)日：2006-08-03
申请号：US11046079
申请日：2005-01-28
申请人： Olubunmi Adetutu , David Gilmer , Philip Tobin
发明人： Olubunmi Adetutu , David Gilmer , Philip Tobin
IPC分类号： H01L21/425
CPC分类号： H01L21/823857 , H01L21/823842
摘要： One or more impurities may be incorporated within a metal-containing layer of a metal-containing gate electrode to modify the work function of the metal-containing gate electrode of a transistor can affect the threshold voltage of the transistor. In one embodiment, the impurity can be used in a p-channel transistor to allow the work function of a metal-containing gate electrode to be closer to the valence band for silicon. In another embodiment, the impurity can be used in an n-channel transistor to allow the work function of a metal-containing gate electrode to be closer to the conduction band for silicon. In a particular embodiment, a boron-containing species is implanted into a metal-containing layer within the metal-containing gate electrode within a p-channel transistor, so that the metal-containing gate electrode has a work function closer to the valence band for silicon as compared to the metal-containing gate electrode without the boron-containing species.
摘要翻译：可以在含金属的栅电极的含金属层内并入一种或多种杂质以改变晶体管的含金属栅电极的功函数可影响晶体管的阈值电压。在一个实施例中，杂质可用于p沟道晶体管，以允许含金属的栅电极的功函数更接近硅的价带。在另一实施例中，杂质可用于n沟道晶体管，以允许含金属的栅电极的功函数更接近于硅的导带。在一个具体的实施方案中，将含硼物质注入到在p沟道晶体管内的含金属栅电极内的含金属层中，使得含金属栅电极具有更接近价带的功函数与没有含硼物质的含金属栅电极相比。

4. 发明申请

US20070077698A1 METHOD FOR FABRICATING DUAL-METAL GATE DEVICE 有权
标题翻译：用于制造双金属栅极装置的方法
公开(公告)号：US20070077698A1
公开(公告)日：2007-04-05
申请号：US11530058
申请日：2006-09-08
申请人： David Gilmer , Srikanth Samavedam , Philip Tobin
发明人： David Gilmer , Srikanth Samavedam , Philip Tobin
IPC分类号： H01L21/8238
CPC分类号： H01L21/823842
摘要： A method of fabricating a MOS transistor that comprises a dual-metal gate that is formed from heterotypical metals. A gate dielectric (34), such as HfO2, is deposited on a semiconductor substrate. A sacrificial layer (35), is next deposited over the gate dielectric. The sacrificial layer is patterned so that the gate dielectric over a first (pMOS, for example) area (32) of the substrate is exposed and gate dielectric over a second (nMOS, for example) area (33) of the substrate continues to be protected by the sacrificial layer. A first gate conductor material (51) is deposited over the remaining sacrificial area and over the exposed gate dielectric. The first gate conductor material is patterned so that first gate conductor material over the second area of the substrate is etched away. The sacrificial layer over the second area prevents damage to the underlying dielectric material as the first gate conductor material is removed.
摘要翻译：一种制造包括由异型金属形成的双金属栅极的MOS晶体管的方法。在半导体衬底上沉积诸如HfO 2 N的栅极电介质（34）。牺牲层（35）接着沉积在栅极电介质上。牺牲层被图案化，使得衬底的第一（pMOS，例如）区域（32）上的栅极电介质被暴露，并且衬底的第二（nMOS，例如）区域（33）上的栅极电介质继续是受牺牲层保护。第一栅极导体材料（51）沉积在剩余的牺牲区域上并暴露在栅极电介质上。图案化第一栅极导体材料，使得衬底的第二区域上方的第一栅极导体材料被蚀刻掉。第二区域上的牺牲层防止在去除第一栅极导体材料时损坏下面的介电材料。

5. 发明申请

US20050282326A1 Method for fabricating dual-metal gate device 审中-公开
标题翻译：双金属栅极器件制造方法
公开(公告)号：US20050282326A1
公开(公告)日：2005-12-22
申请号：US11211798
申请日：2005-08-25
申请人： David Gilmer , Srikanth Samavedam , Philip Tobin
发明人： David Gilmer , Srikanth Samavedam , Philip Tobin
IPC分类号： H01L21/8238 , H01L21/338
CPC分类号： H01L21/823842
摘要： A method of fabricating a MOS transistor that comprises a dual-metal gate that is formed from heterotypical metals. A gate dielectric (34), such as HfO2, is deposited on a semiconductor substrate. A sacrificial layer (35), is next deposited over the gate dielectric. The sacrificial layer is patterned so that the gate dielectric over a first (pMOS, for example) area (32) of the substrate is exposed and gate dielectric over a second (nMOS, for example) area (33) of the substrate continues to be protected by the sacrificial layer. A first gate conductor material (51) is deposited over the remaining sacrificial area and over the exposed gate dielectric. The first gate conductor material is patterned so that first gate conductor material over the second area of the substrate is etched away. The sacrificial layer over the second area prevents damage to the underlying dielectric material as the first gate conductor material is removed.
摘要翻译：一种制造包括由异型金属形成的双金属栅极的MOS晶体管的方法。在半导体衬底上沉积诸如HfO 2 N的栅极电介质（34）。牺牲层（35）接着沉积在栅极电介质上。牺牲层被图案化，使得衬底的第一（pMOS，例如）区域（32）上的栅极电介质被暴露，并且衬底的第二（nMOS，例如）区域（33）上的栅极电介质继续是受牺牲层保护。第一栅极导体材料（51）沉积在剩余的牺牲区域上并暴露在栅极电介质上。图案化第一栅极导体材料，使得衬底的第二区域上方的第一栅极导体材料被蚀刻掉。第二区域上的牺牲层防止在去除第一栅极导体材料时损坏下面的介电材料。

6. 发明申请

US20100211495A1 SYSTEMS, METHODS AND COMPUTER PROGRAM PRODUCTS FOR IMPROVING FOREIGN CURRENCY EXCHANGE IN A COMPREHENSIVE PAYMENT HUB SYSTEM 审中-公开
标题翻译：系统，方法和计算机程序产品，用于改善综合支付系统中的外汇交换
公开(公告)号：US20100211495A1
公开(公告)日：2010-08-19
申请号：US12434374
申请日：2009-05-01
申请人： Mark D. Zanzot , Garrett C. Briggs , Eric Dryer , Anthony B. Calderone , William Earl Thomas, II , Philip Tobin , David Todd Frew , Kerry Cantley
发明人： Mark D. Zanzot , Garrett C. Briggs , Eric Dryer , Anthony B. Calderone , William Earl Thomas, II , Philip Tobin , David Todd Frew , Kerry Cantley
IPC分类号： G06Q20/00 , G06Q40/00
CPC分类号： G06Q20/381 , G06Q20/04 , G06Q20/10 , G06Q20/102 , G06Q40/00 , G06Q40/04
摘要： Systems, methods, and computer program products are provided for improving foreign currency exchange processing of financial payment requests and, more specifically improving the bid/ask spread in foreign currency exchange so as to increase the profitability realized by the financial institution processing the payment. In accordance with embodiments herein disclosed, international financial payment requests are pooled together based on currency type and payment time requirements to provide for better exchange rates.
摘要翻译：提供系统，方法和计算机程序产品，用于改善金融支付请求的外币兑换处理，更具体地说是改善外币兑换的买卖价差，从而提高处理支付金融机构实现的盈利能力。根据本文所公开的实施例，国际金融支付请求基于货币类型和支付时间要求汇总在一起以提供更好的汇率。

7. 发明申请

US20050070056A1 SOI template layer 有权
标题翻译： SOI模板层
公开(公告)号：US20050070056A1
公开(公告)日：2005-03-31
申请号：US10670928
申请日：2003-09-25
申请人： Chun-Li Liu , Marius Orlowski , Matthew Stoker , Philip Tobin , Mariam Sadaka , Alexander Barr , Bich-Yen Nguyen , Voon-Yew Thean , Shawn Thomas , Ted White
发明人： Chun-Li Liu , Marius Orlowski , Matthew Stoker , Philip Tobin , Mariam Sadaka , Alexander Barr , Bich-Yen Nguyen , Voon-Yew Thean , Shawn Thomas , Ted White
IPC分类号： H01L20060101 , H01L21/00 , H01L21/338
CPC分类号： H01L29/161 , H01L21/26506 , H01L21/823807 , H01L21/823878 , H01L21/84 , H01L29/1054 , Y10S438/933
摘要： A vacancy injecting process for injecting vacancies in template layer material of an SOI substrate. The template layer material has a crystalline structure that includes, in some embodiments, both germanium and silicon atoms. A strained silicon layer is then epitaxially grown on the template layer material with the beneficial effects that straining has on electron and hole mobility. The vacancy injecting process is performed to inject vacancies and germanium atoms into the crystalline structure wherein germanium atoms recombine with the vacancies. One embodiment, a nitridation process is performed to grow a nitride layer on the template layer material and consume silicon in a way that injects vacancies in the crystalline structure while also allowing germanium atoms to recombine with the vacancies. Other examples of a vacancy injecting processes include silicidation processes, oxynitridation processes, oxidation processes with a chloride bearing gas, or inert gas post bake processes subsequent to an oxidation process.
摘要翻译：用于在SOI衬底的模板层材料中注入空位的空位注入工艺。模板层材料具有在一些实施方案中包括锗和硅原子的晶体结构。然后在模板层材料上外延生长应变硅层，具有应力对电子和空穴迁移率的有益效果。进行空位注入处理以将空位和锗原子注入晶格结构中，其中锗原子与空位重新组合。一个实施方案中，进行氮化处理以在模板层材料上生长氮化物层，并以注入晶体结构中的空位并且还允许锗原子与空位复合的方式消耗硅。空位注入方法的其它实例包括硅化工艺，氧氮化工艺，含氯化物气体的氧化工艺或氧化工艺之后的惰性气体后烘烤工艺。

8. 发明授权

US10240548B2 Control system and method of operating a control system 有权
公开(公告)号：US10240548B2
公开(公告)日：2019-03-26
申请号：US14905205
申请日：2013-07-23
申请人： Mike Garrard , Anoop K. Aggarwal , William E. Edwards , Philip Tobin
发明人： Mike Garrard , Anoop K. Aggarwal , William E. Edwards , Philip Tobin
IPC分类号： F02D41/22 , B60R16/023 , G05B15/02 , G07C5/00 , F02D41/28
摘要： An electronic control unit suitable for a motorcycle provides diagnostic support, tachometer drive and warning lamp drive all multiplexed onto one pin and driven by a single driver circuit. In a diagnostics mode, the pin is connected to diagnostic equipment. When a diagnostic test has been completed, a tachometer drive signal is output on the pin, the drive signal having a duty cycle set high enough to illuminate the warning lamp if a fault condition is detected by on-board sensors. By combining multiple functions onto a single pin with a single driver circuit, the cost of implementing an engine control unit may be reduced compared with existing arrangements which require separate pins and drivers for each function.

9. 发明申请

US20100211483A1 SYSTEMS, METHODS AND COMPUTER PROGRAM PRODUCTS FOR MANAGING PAYMENT PROCESSES IN A COMPREHENSIVE PAYMENT HUB SYSTEM 有权
标题翻译：管理综合支付系统支付过程的系统，方法和计算机程序产品
公开(公告)号：US20100211483A1
公开(公告)日：2010-08-19
申请号：US12433267
申请日：2009-04-30
申请人： Mark D. Zanzot , Garrett C. Briggs , Eric Dryer , Anthony B. Calderone , William Earl Thomas, II , Philip Tobin , David Todd Frew , Kerry Cantley
发明人： Mark D. Zanzot , Garrett C. Briggs , Eric Dryer , Anthony B. Calderone , William Earl Thomas, II , Philip Tobin , David Todd Frew , Kerry Cantley
IPC分类号： G06Q20/00 , G06Q10/00
CPC分类号： G06Q20/10 , G06Q20/102 , G06Q40/12
摘要： Systems, methods, and computer program products are provided for managing the processing of a financial payment and, more specifically managing the processing of a financial payment in a comprehensive payment hub environment that provides for payment processing, including payment route determination, irrespective of the payment input channel. In accordance with embodiments herein disclosed, managing the processing of the payment includes automatically determining the payment processes and automatically determining the arrangement of the payment processes. As such, the methods, systems, and computer program products herein described provide for an efficient and cost-effective approach to processing payments.
摘要翻译：提供了系统，方法和计算机程序产品，用于管理金融支付的处理，并且更具体地管理在提供支付处理的综合支付中心环境中的金融支付的处理，包括支付路线确定，而不管支付输入通道。根据本文公开的实施例，管理付款的处理包括自动确定支付过程并自动确定支付过程的布置。因此，本文描述的方法，系统和计算机程序产品提供了处理支付的有效和成本有效的方法。

10. 发明申请

US20100211422A1 SYSTEMS, METHODS AND COMPUTER PROGRAM PRODUCTS FOR STANDARDIZATION OF PAYMENT REQUESTS TO FACILITATE COMPREHENSIVE PAYMENT HUB PROCESSING 有权
标题翻译：系统，方法和计算机程序产品，用于标准化付款要求，以便促进综合付款处理
公开(公告)号：US20100211422A1
公开(公告)日：2010-08-19
申请号：US12433272
申请日：2009-04-30
申请人： Mark D. Zanzot , Garrett C. Briggs , Eric Dryer , Anthony B. Calderone , William Earl Thomas, II , Philip Tobin , David Todd Frew , Kerry Cantley
发明人： Mark D. Zanzot , Garrett C. Briggs , Eric Dryer , Anthony B. Calderone , William Earl Thomas, II , Philip Tobin , David Todd Frew , Kerry Cantley
IPC分类号： G06Q20/00 , G06Q10/00
CPC分类号： G06Q20/023 , G06Q20/02 , G06Q20/10 , G06Q20/102 , G06Q40/12
摘要： Systems, methods, and computer program products are provided for conducting comprehensive payment processing of all payment requests regardless of the payment request channel. Payment requests are transformed from the initial format to a standardized format, which allows for the occurrence of further comprehensive payment processing, referred to herein as payment hub processing. Once the payment request has undergone necessary payment hub processing, the request undergoes further transformation/conversion from the standardized format to a target clearing format. In one embodiment of the invention, the processing hub provides for determining the clearing or remittance channel based on payment routing rules, which may take into account cost, time, risk and any other payment factors.
摘要翻译：提供系统，方法和计算机程序产品，用于对所有支付请求进行全面的支付处理，而不管支付请求信道如何。支付请求从初始格式转换为标准格式，这允许进一步全面支付处理的发生，这里称为支付集线器处理。一旦支付请求经过必要的支付中心处理，该请求将从标准化格式进一步转换/转换为目标清算格式。在本发明的一个实施例中，处理集线器提供基于支付路由规则来确定清算或汇款信道，这可以考虑到成本，时间，风险和任何其他支付因素。

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