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1. 发明申请

US20050179112A1 Filling high aspect ratio isolation structures with polysilazane based material 审中-公开
标题翻译：用聚硅氮烷基材料填充高纵横比隔离结构
公开(公告)号：US20050179112A1
公开(公告)日：2005-08-18
申请号：US11035392
申请日：2005-01-12
申请人： Michael Belyansky , Rama Divakaruni , Laertis Economikos , Rajarao Jammy , Kenneth Settlemyer , Padraic Shafer
发明人： Michael Belyansky , Rama Divakaruni , Laertis Economikos , Rajarao Jammy , Kenneth Settlemyer , Padraic Shafer
IPC分类号： H01L21/76 , H01L21/762 , H01L21/8242 , H01L27/108
CPC分类号： H01L21/76229
摘要： Isolation trenches and capacitor trenches containing vertical FETs (or any prior levels p-n junctions or dissimilar material interfaces) having an aspect ratio up to 60 are filled with a process comprising: applying a spin-on material based on silazane and having a low molecular weight; pre-baking the applied material in an oxygen ambient at a temperature below about 450 deg C.; converting the stress in the material by heating at an intermediate temperature between 450 deg C. and 800 deg C. in an H20 ambient; and heating again at an elevated temperature in an O2 ambient, resulting in a material that is stable up to 1000 deg C., has a compressive stress that may be tuned by variation of the process parameters, has an etch rate comparable to oxide dielectric formed by HDP techniques, and is durable enough to withstand CMP polishing.
摘要翻译：包含具有高达60的纵横比的垂直FET（或任何先前级别的p-n结或异种材料界面）的隔离沟槽和电容器沟槽被填充了一种方法，其包括：施加基于硅氮烷并且具有低分子量的旋涂材料; 在低于约450℃的温度下在氧环境中预烘烤施加的材料; 通过在H 2 O环境中在450摄氏度和800摄氏度之间的中间温度下加热来转化材料中的应力; 并且在高温下再次在O 2环境中加热，得到稳定至高达1000℃的材料，具有可通过工艺参数变化调节的压缩应力，具有与形成的氧化物电介质相当的蚀刻速率通过HDP技术，并且耐用性足以承受CMP抛光。

2. 发明申请

US20060128055A1 REPLACEMENT GATE WITH TERA CAP 失效
标题翻译：用TERA CAP更换门
公开(公告)号：US20060128055A1
公开(公告)日：2006-06-15
申请号：US10905070
申请日：2004-12-14
申请人： Kangguo Cheng , Ramachandra Divakaruni , Kenneth Settlemyer
发明人： Kangguo Cheng , Ramachandra Divakaruni , Kenneth Settlemyer
IPC分类号： H01L21/00
CPC分类号： H01L29/6656 , H01L29/495 , H01L29/4966 , H01L29/51 , H01L29/66545 , H01L29/6659 , H01L29/7833
摘要： A field effect transistor formed by a sacrificial gate process has a simplified process and improved yield by using a tunable resistant anti-reflective coating (TERA) as the cap layer over the sacrificial gate layer. The TERA layer serves as a tunable anti-reflection layer for photolithography patterning, a hardmask for etching the sacrificial gate, a polish stopping layer for planarization, and a blocking layer for preventing silicide formation over the sacrificial gate. The TERA is stripped by a two-step process that is highly selective to the nitride spacers, so that the spacers are not damaged in the process of stripping the sacrificial gate.
摘要翻译：通过牺牲栅极工艺形成的场效应晶体管通过使用可调阻抗抗反射涂层（TERA）作为牺牲栅极层上的覆盖层，具有简化的工艺和提高的产量。 TERA层用作光刻图案的可调谐抗反射层，用于蚀刻牺牲栅极的硬掩模，用于平坦化的抛光停止层，以及用于防止在牺牲栅极上形成硅化物的阻挡层。通过对氮化物间隔物具有高度选择性的两步法来剥离TERA，使得在剥离牺牲栅极的过程中间隔体不被损坏。

3. 发明申请

US20060105526A1 Method of fabricating a bottle trench and a bottle trench capacitor 有权
公开(公告)号：US20060105526A1
公开(公告)日：2006-05-18
申请号：US10904582
申请日：2004-11-17
申请人： Oh-Jung Kwon , Kenneth Settlemyer , Ravikumar Ramachandran , Min-Soo Kim
发明人： Oh-Jung Kwon , Kenneth Settlemyer , Ravikumar Ramachandran , Min-Soo Kim
IPC分类号： H01L21/336
CPC分类号： H01L27/1087 , H01L29/66181
摘要： A method of fabricating a bottle trench and a bottle trench capacitor. The method including: providing a substrate; forming a trench in the substrate, the trench having sidewalls and a bottom, the trench having an upper region adjacent to a top surface of the substrate and a lower region adjacent to the bottom of the trench; forming an oxidized layer of the substrate in the bottom region of the trench; and removing the oxidized layer of the substrate from the bottom region of the trench, a cross-sectional area of the lower region of the trench greater than a cross-sectional area of the upper region of the trench.

4. 发明申请

US20050255386A1 METHODS AND STRUCTURES FOR PROTECTING ONE AREA WHILE PROCESSING ANOTHER AREA ON A CHIP 失效
标题翻译：在芯片上处理其他区域时保护一个区域的方法和结构
公开(公告)号：US20050255386A1
公开(公告)日：2005-11-17
申请号：US10709514
申请日：2004-05-11
申请人： Deok-kee Kim , Kenneth Settlemyer , Kangguo Cheng , Ramachandra Divakaruni , Carl Radens , Dirk Pfeiffer , Timothy Dalton , Katherina Babich , Arpan Mahorowala , Harald Okorn-Schmidt
发明人： Deok-kee Kim , Kenneth Settlemyer , Kangguo Cheng , Ramachandra Divakaruni , Carl Radens , Dirk Pfeiffer , Timothy Dalton , Katherina Babich , Arpan Mahorowala , Harald Okorn-Schmidt
IPC分类号： G03C5/00 , G03F7/11 , G03F9/00 , H01L21/033 , H01L21/311 , H01L21/331
CPC分类号： H01L21/0337 , G03F7/11 , H01L21/027 , H01L21/0332 , H01L21/0334 , H01L21/0338 , H01L21/31144
摘要： Increased protection of areas of a chip are provided by both a mask structure of increased robustness in regard to semiconductor manufacturing processes or which can be removed with increased selectivity and controllability in regard to underlying materials, or both. Mask structures are provided which exhibit an interface of a chemical reaction, grain or material type which can be exploited to enhance either or both types of protection. Structures of such masks include TERA material which can be converted or hydrated and selectively etched using a mixture of hydrogen fluoride and a hygroscopic acid or organic solvent, and two layer structures of similar or dissimilar materials.
摘要翻译：增加对芯片区域的保护是通过在半导体制造工艺方面具有增强的鲁棒性的掩模结构来提供的，或者可以以相对于下面的材料或两者的增加的选择性和可控性被去除。提供掩模结构，其显示化学反应，颗粒或材料类型的界面，其可被利用以增强任一种或两种类型的保护。这种掩模的结构包括TERA材料，其可以使用氟化氢和吸湿性酸或有机溶剂的混合物以及相似或不同材料的两层结构进行转化或水合并选择性蚀刻。

5. 发明授权

US06967136B2 Method and structure for improved trench processing 失效
标题翻译：改进沟槽加工的方法和结构
公开(公告)号：US06967136B2
公开(公告)日：2005-11-22
申请号：US10604594
申请日：2003-08-01
申请人： Hiroyuki Akatsu , Kangguo Cheng , Kenneth Settlemyer
发明人： Hiroyuki Akatsu , Kangguo Cheng , Kenneth Settlemyer
IPC分类号： H01L21/20 , H01L21/8242
CPC分类号： H01L27/1087 , H01L27/10864
摘要： A method is provided for making a trench capacitor by forming a trench in a substrate. The trench is then widened and a sacrificial collar is formed on sidewalls of the widened trench. The trench is then vertically deepened to extend below the sidewalls of the sacrificial collar. Subsequently, a capacitor is formed in the trench below the sacrificial collar. An integrated circuit includes a deep trench structure formed in a single-crystal region of a semiconductor substrate including an upper trench portion, the upper trench portion having an opening of rectangular shape. A lower trench portion is formed below the upper trench portion. The lower portion may be widened to have a bottle shape. Alternatively, the upper trench portion may be widened relative to the lower trench portion.
摘要翻译：提供一种通过在衬底中形成沟槽来制造沟槽电容器的方法。然后加宽沟槽，并且在加宽的沟槽的侧壁上形成牺牲套环。然后将沟槽垂直加深以在牺牲套环的侧壁下方延伸。随后，在牺牲套环下方的沟槽中形成电容器。集成电路包括形成在包括上沟槽部分的半导体衬底的单晶区域中的深沟槽结构，上沟槽部分具有矩形形状的开口。下沟槽部分形成在上沟槽部分的下方。下部可以被加宽以具有瓶子形状。或者，上沟槽部分可以相对于下沟槽部分加宽。

6. 发明申请

US20050121412A1 Pull-back method of forming fins in FinFETs 失效
标题翻译： FinFET形成翅片的回拉法
公开(公告)号：US20050121412A1
公开(公告)日：2005-06-09
申请号：US10730234
申请日：2003-12-09
申请人： Jochen Beintner , Dureseti Chidambarrao , Yujun Li , Kenneth Settlemyer
发明人： Jochen Beintner , Dureseti Chidambarrao , Yujun Li , Kenneth Settlemyer
IPC分类号： H01L21/308 , H01L21/336 , H01L29/78 , H01L29/786 , B44C1/22 , C25F3/00
CPC分类号： H01L29/785 , H01L21/3086 , H01L21/3088 , H01L29/66795
摘要： A method of forming integrated circuits having FinFET transistors includes a method of forming sub-lithographic fins, in which a mask defining a block of silicon including a pair of fins in reduced in width or pulled back by the thickness of one fin on each side, after which a second mask is formed around the first mask, so that after the first mask is removed, an aperture remains in the second mask having the width of the separation distance between the pair of fins. When the silicon is etched through the aperture, the fins are protected by the second mask, thereby defining fin thickness by the pullback step. An alternative method uses lithography of opposite polarity, first defining the central etch aperture between the two fins lithographically, then expanding the width of the aperture by a pullback step, so that filling the widened aperture with an etch-resistant plug defines the outer edges of the pair of fins, thereby setting the fin width without an alignment kstep.
摘要翻译：一种形成具有FinFET晶体管的集成电路的方法包括形成次光刻鳍片的方法，其中限定包含一对鳍片的硅块的掩模，所述掩模的宽度被减小或者被拉回每边的一个鳍片的厚度，之后在第一掩模周围形成第二掩模，使得在去除第一掩模之后，在第二掩模中保留具有一对散热片之间的间隔距离的宽度的孔。当通过孔蚀刻硅时，翅片被第二掩模保护，从而通过拉回步骤限定翅片厚度。一种替代方法是使用相反极性的光刻法，首先在两个散热片之间光刻地限定中心蚀刻孔径，然后通过拉回步骤扩大孔径的宽度，以便用耐蚀刻塞子填充加宽的孔径限定了一对翅片，从而设置翅片宽度而没有对准kstep。

7. 发明授权

US08853746B2 CMOS devices with stressed channel regions, and methods for fabricating the same 有权
标题翻译：具有应力沟道区的CMOS器件及其制造方法
公开(公告)号：US08853746B2
公开(公告)日：2014-10-07
申请号：US11427495
申请日：2006-06-29
申请人： Xiangdong Chen , Thomas W. Dyer , Kenneth Settlemyer , Haining S. Yang
发明人： Xiangdong Chen , Thomas W. Dyer , Kenneth Settlemyer , Haining S. Yang
IPC分类号： H01L29/76 , H01L27/148 , H01L29/66 , H01L29/165 , H01L29/786 , H01L29/78 , H01L27/12 , H01L21/84 , H01L29/04 , H01L29/10 , H01L21/762 , H01L21/8238
CPC分类号： H01L29/7848 , H01L21/02532 , H01L21/30604 , H01L21/7624 , H01L21/823807 , H01L21/823878 , H01L21/84 , H01L27/092 , H01L27/1203 , H01L29/045 , H01L29/1054 , H01L29/16 , H01L29/161 , H01L29/165 , H01L29/66636 , H01L29/66772 , H01L29/78 , H01L29/78684 , H01L29/78696
摘要： The present invention relates to improved complementary metal-oxide-semiconductor (CMOS) devices with stressed channel regions. Specifically, each improved CMOS device comprises an field effect transistor (FET) having a channel region located in a semiconductor device structure, which has a top surface oriented along one of a first set of equivalent crystal planes and one or more additional surfaces oriented along a second, different set of equivalent crystal planes. Such additional surfaces can be readily formed by crystallographic etching. Further, one or more stressor layers with intrinsic compressive or tensile stress are located over the additional surfaces of the semiconductor device structure and are arranged and constructed to apply tensile or compressive stress to the channel region of the FET. Such stressor layers can be formed by pseudomorphic growth of a semiconductor material having a lattice constant different from the semiconductor device structure.
摘要翻译：本发明涉及具有应力通道区域的改进的互补金属氧化物半导体（CMOS）器件。具体地，每个改进的CMOS器件包括具有位于半导体器件结构中的沟道区的场效应晶体管（FET），其具有沿着第一组等效晶面中的一个取向的顶表面和沿着第二，不同组的等效晶面。这种附加表面可以通过晶体蚀刻容易地形成。此外，具有固有压缩或拉伸应力的一个或多个应力层位于半导体器件结构的附加表面上，并且被布置和构造成将拉应力或压应力施加到FET的沟道区。这种应力层可以通过具有与半导体器件结构不同的晶格常数的半导体材料的假晶生长来形成。

8. 发明申请

US20070166900A1 Device fabrication by anisotropic wet etch 失效
标题翻译：通过各向异性湿法蚀刻的器件制造
公开(公告)号：US20070166900A1
公开(公告)日：2007-07-19
申请号：US11333108
申请日：2006-01-17
申请人： Yujun Li , Kenneth Settlemyer , Jochen Beintner
发明人： Yujun Li , Kenneth Settlemyer , Jochen Beintner
IPC分类号： H01L21/8232 , H01L21/335 , H01L21/84 , H01L21/00
CPC分类号： H01L21/84 , H01L21/30608 , H01L27/1203 , H01L29/045 , H01L29/66772 , H01L29/66818 , H01L29/785
摘要： A method of fabrication and a field effect device structure are presented that reduce source/drain capacitance and allow for device body contact. A Si based material pedestal is produced, the top surface and the sidewalls of which are oriented in a way to be substantially parallel with selected crystallographic planes of the pedestal and of a supporting member. The pedestal is wet etched with an anisotropic solution containing ammonium hydroxide. The sidewalls of the pedestal become faceted forming a segment in the pedestal with a reduced cross section. The dopant concentration in the reduced cross section segment is chosen to be sufficiently high for it to provide for electrical continuity through the pedestal.
摘要翻译：提出了一种制造方法和场效应器件结构，其减少源/漏电容并允许器件接触。制造基于Si的材料基座，其顶表面和其侧壁的取向方向基本上平行于基座和支撑构件的选定结晶平面。用包含氢氧化铵的各向异性溶液湿式蚀刻基座。基座的侧壁变小，在基座上形成截面减小的部分。选择减小的横截面段中的掺杂剂浓度足够高以使其提供穿过基座的电连续性。

9. 发明申请

US20060275974A1 METHOD OF FABRICATING A BOTTLE TRENCH AND A BOTTLE TRENCH CAPACITOR 有权
标题翻译：制造瓶子和透气电容器的方法
公开(公告)号：US20060275974A1
公开(公告)日：2006-12-07
申请号：US11458120
申请日：2006-07-18
申请人： Oh-Jung Kwon , Kenneth Settlemyer , Ravikumar Ramachandran , Min-Soo Kim
发明人： Oh-Jung Kwon , Kenneth Settlemyer , Ravikumar Ramachandran , Min-Soo Kim
IPC分类号： H01L21/8238
CPC分类号： H01L27/1087 , H01L29/66181
摘要： A method of fabricating a bottle trench and a bottle trench capacitor. The method including: providing a substrate; forming a trench in the substrate, the trench having sidewalls and a bottom, the trench having an upper region adjacent to a top surface of the substrate and a lower region adjacent to the bottom of the trench; forming an oxidized layer of the substrate in the bottom region of the trench; and removing the oxidized layer of the substrate from the bottom region of the trench, a cross-sectional area of the lower region of the trench greater than a cross-sectional area of the upper region of the trench.
摘要翻译：制造瓶沟槽和瓶沟电容器的方法。该方法包括：提供衬底; 在所述衬底中形成沟槽，所述沟槽具有侧壁和底部，所述沟槽具有与所述衬底的顶表面相邻的上部区域和与所述沟槽的底部相邻的下部区域; 在沟槽的底部区域形成衬底的氧化层; 并且从沟槽的底部区域去除衬底的氧化层，沟槽的下部区域的横截面面积大于沟槽的上部区域的横截面面积。

10. 发明申请

US20080001182A1 IMPROVED CMOS DEVICES WITH STRESSED CHANNEL REGIONS, AND METHODS FOR FABRICATING THE SAME 有权
标题翻译：改进的具有应力通道区域的CMOS器件及其制造方法
公开(公告)号：US20080001182A1
公开(公告)日：2008-01-03
申请号：US11427495
申请日：2006-06-29
申请人： Xiangdong Chen , Thomas W. Dyer , Kenneth Settlemyer , Haining S. Yang
发明人： Xiangdong Chen , Thomas W. Dyer , Kenneth Settlemyer , Haining S. Yang
IPC分类号： H01L29/76 , H01L27/148
CPC分类号： H01L29/7848 , H01L21/02532 , H01L21/30604 , H01L21/7624 , H01L21/823807 , H01L21/823878 , H01L21/84 , H01L27/092 , H01L27/1203 , H01L29/045 , H01L29/1054 , H01L29/16 , H01L29/161 , H01L29/165 , H01L29/66636 , H01L29/66772 , H01L29/78 , H01L29/78684 , H01L29/78696
摘要： The present invention relates to improved complementary metal-oxide-semiconductor (CMOS) devices with stressed channel regions. Specifically, each improved CMOS device comprises an field effect transistor (FET) having a channel region located in a semiconductor device structure, which has a top surface oriented along one of a first set of equivalent crystal planes and one or more additional surfaces oriented along a second, different set of equivalent crystal planes. Such additional surfaces can be readily formed by crystallographic etching. Further, one or more stressor layers with intrinsic compressive or tensile stress are located over the additional surfaces of the semiconductor device structure and are arranged and constructed to apply tensile or compressive stress to the channel region of the FET. Such stressor layers can be formed by pseudomorphic growth of a semiconductor material having a lattice constant different from the semiconductor device structure.
摘要翻译：本发明涉及具有应力通道区域的改进的互补金属氧化物半导体（CMOS）器件。具体地，每个改进的CMOS器件包括具有位于半导体器件结构中的沟道区的场效应晶体管（FET），其具有沿着第一组等效晶面中的一个取向的顶表面和沿着第二，不同组的等效晶面。这种附加表面可以通过晶体蚀刻容易地形成。此外，具有固有压缩或拉伸应力的一个或多个应力层位于半导体器件结构的附加表面上，并且被布置和构造成将拉应力或压应力施加到FET的沟道区。这样的应力层可以通过具有与半导体器件结构不同的晶格常数的半导体材料的假晶生长来形成。

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