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1. 发明申请

US20050179112A1 Filling high aspect ratio isolation structures with polysilazane based material 审中-公开
标题翻译：用聚硅氮烷基材料填充高纵横比隔离结构
公开(公告)号：US20050179112A1
公开(公告)日：2005-08-18
申请号：US11035392
申请日：2005-01-12
申请人： Michael Belyansky , Rama Divakaruni , Laertis Economikos , Rajarao Jammy , Kenneth Settlemyer , Padraic Shafer
发明人： Michael Belyansky , Rama Divakaruni , Laertis Economikos , Rajarao Jammy , Kenneth Settlemyer , Padraic Shafer
IPC分类号： H01L21/76 , H01L21/762 , H01L21/8242 , H01L27/108
CPC分类号： H01L21/76229
摘要： Isolation trenches and capacitor trenches containing vertical FETs (or any prior levels p-n junctions or dissimilar material interfaces) having an aspect ratio up to 60 are filled with a process comprising: applying a spin-on material based on silazane and having a low molecular weight; pre-baking the applied material in an oxygen ambient at a temperature below about 450 deg C.; converting the stress in the material by heating at an intermediate temperature between 450 deg C. and 800 deg C. in an H20 ambient; and heating again at an elevated temperature in an O2 ambient, resulting in a material that is stable up to 1000 deg C., has a compressive stress that may be tuned by variation of the process parameters, has an etch rate comparable to oxide dielectric formed by HDP techniques, and is durable enough to withstand CMP polishing.
摘要翻译：包含具有高达60的纵横比的垂直FET（或任何先前级别的p-n结或异种材料界面）的隔离沟槽和电容器沟槽被填充了一种方法，其包括：施加基于硅氮烷并且具有低分子量的旋涂材料; 在低于约450℃的温度下在氧环境中预烘烤施加的材料; 通过在H 2 O环境中在450摄氏度和800摄氏度之间的中间温度下加热来转化材料中的应力; 并且在高温下再次在O 2环境中加热，得到稳定至高达1000℃的材料，具有可通过工艺参数变化调节的压缩应力，具有与形成的氧化物电介质相当的蚀刻速率通过HDP技术，并且耐用性足以承受CMP抛光。

2. 发明申请

US20050009267A1 FORMING COLLAR STRUCTURES IN DEEP TRENCH CAPACITORS WITH THERMALLY STABLE FILLER MATERIAL 失效
标题翻译：形成具有热稳定填料的深层电容器中的组合结构
公开(公告)号：US20050009267A1
公开(公告)日：2005-01-13
申请号：US10604255
申请日：2003-07-07
申请人： Michael Belyansky , Rama Divakaruni , Jack Mandelman , Dae-Gyu Park
发明人： Michael Belyansky , Rama Divakaruni , Jack Mandelman , Dae-Gyu Park
IPC分类号： H01L21/20 , H01L21/334 , H01L21/8242 , H01L27/108
CPC分类号： H01L27/1087 , H01L27/10829 , H01L29/66181
摘要： In the course of forming the collar dielectric in a DRAM cell having a deep trench capacitor, a number of filling and stripping steps required in the prior art are eliminated by the use of a spin-on material that can withstand the high temperatures required in front-end processing and also provide satisfactory filling ability and etch resistance. The use of atomic layer deposition for the formation of the collar dielectric reduces the need for a high temperature anneal of the fill material and reduces the amount of outgassing or cracking.
摘要翻译：在具有深沟槽电容器的DRAM单元中形成环形电介质的过程中，现有技术中所需要的许多填充和剥离步骤通过使用可承受前面所需的高温的旋涂材料而消除并且提供令人满意的填充能力和耐蚀刻性。用于形成套环电介质的原子层沉积减少了填充材料的高温退火的需要并减少了除气或开裂的量。

3. 发明申请

US20060289909A1 Self-aligned low-k gate cap 失效
标题翻译：自对准低k门帽
公开(公告)号：US20060289909A1
公开(公告)日：2006-12-28
申请号：US11514605
申请日：2006-09-01
申请人： Oleg Gluschenkov , Jack Mandelman , Michael Belyansky , Bruce Doris
发明人： Oleg Gluschenkov , Jack Mandelman , Michael Belyansky , Bruce Doris
IPC分类号： H01L29/76
CPC分类号： H01L21/76834 , H01L21/28052 , H01L21/76897 , H01L29/6653 , H01L29/6659 , H01L29/7833
摘要： A CMOS structure in which the gate-to-drain/source capacitance is reduced as well as various methods of fabricating such a structure are provided. In accordance with the present invention, it has been discovered that the gate-to-drain/source capacitance can be significantly reduced by forming a CMOS structure in which a low-k dielectric material is self-aligned with the gate conductor. A reduction in capacitance between the gate conductor and the contact via ranging from about 30% to greater than 40% has been seen with the inventive structures. Moreover, the total outer-fringe capacitance (gate to outer diffusion+gate to contact via) is reduced between 10-18%. The inventive CMOS structure includes at least one gate region including a gate conductor located a top a surface of a semiconductor substrate; and a low-k dielectric material that is self-aligned to the gate conductor.
摘要翻译：提供其中栅极 - 漏极/源极电容减小的CMOS结构以及制造这种结构的各种方法。根据本发明，已经发现，通过形成其中低k电介质材料与栅极导体自对准的CMOS结构，可以显着降低栅 - 漏/源电容。本发明的结构已经看到，栅极导体和接触孔之间的电容减小范围为约30％至大于40％。此外，总外部电容（门到外部扩散+接触通孔的栅极）在10-18％之间降低。本发明的CMOS结构包括至少一个栅极区域，其包括位于半导体衬底的表面顶部的栅极导体; 以及与栅极导体自对准的低k电介质材料。

4. 发明申请

US20080020522A1 FIELD EFFECT TRANSISTORS WITH DIELECTRIC SOURCE DRAIN HALO REGIONS AND REDUCED MILLER CAPACITANCE 有权
标题翻译：具有介质源漏极区域的场效应晶体管和减少的MILLER电容
公开(公告)号：US20080020522A1
公开(公告)日：2008-01-24
申请号：US11865313
申请日：2007-10-01
申请人： Michael Belyansky , Dureseti Chidambarrao , Oleg Gluschenkov
发明人： Michael Belyansky , Dureseti Chidambarrao , Oleg Gluschenkov
IPC分类号： H01L21/336
CPC分类号： H01L29/0653 , H01L29/1083 , H01L29/6653 , H01L29/66636 , H01L29/66772 , H01L29/7833 , H01L29/7842 , H01L29/7843 , H01L29/78609 , Y10S438/954
摘要： A field effect transistor (FET) device includes a gate conductor and gate dielectric formed over an active device area of a semiconductor substrate. A drain region is formed in the active device area of the semiconductor substrate, on one side of the gate conductor, and a source region is formed in the active device area of the semiconductor substrate, on an opposite side of the gate conductor. A dielectric halo or plug is formed in the active area of said semiconductor substrate, the dielectric halo or plug disposed in contact between the drain region and a body region, and in contact between the source region and the body region.
摘要翻译：场效应晶体管（FET）器件包括在半导体衬底的有源器件区域上形成的栅极导体和栅极电介质。在半导体衬底的有源器件区域中，在栅极导体的一侧上形成漏极区域，并且在栅极导体的相对侧上在半导体衬底的有源器件区域中形成源极区域。在所述半导体衬底的有源区域中形成介电晕或插塞，所述介电晕或插头设置在所述漏区和体区之间并且在所述源区与所述体区之间接触。

5. 发明申请

US20070092990A1 FIELD EFFECT TRANSISTORS (FETS) WITH INVERTED SOURCE/DRAIN METALLIC CONTACTS, AND METHOD OF FABRICATING SAME 失效
标题翻译：具有反相源/漏电金属接触的场效应晶体管（FET）及其制造方法
公开(公告)号：US20070092990A1
公开(公告)日：2007-04-26
申请号：US11163523
申请日：2005-10-21
申请人： Michael Belyansky , Dureseti Chidambarrao , Lawrence Clevenger , Kaushik Kumar , Carl Radens
发明人： Michael Belyansky , Dureseti Chidambarrao , Lawrence Clevenger , Kaushik Kumar , Carl Radens
IPC分类号： H01L21/00 , H01L29/76
CPC分类号： H01L21/76804 , H01L29/6659 , H01L29/7833 , H01L2924/0002 , H01L2924/00
摘要： The present invention relates to an field effect transistor (FET) comprising an inverted source/drain metallic contact that has a lower portion located in a first, lower dielectric layer and an upper portion located in a second, upper dielectric layer. The lower portion of the inverted source/drain metallic contact has a larger cross-sectional area than the upper portion. Preferably, the lower portion of the inverted source/drain metallic contact has a cross-sectional area ranging from about 0.03 μm2 to about 3.15 μm2, and such an inverted source/drain metallic contact is spaced apart from a gate electrode of the FET by a distance ranging from about 0.001 μm to about 5 μm.
摘要翻译：本发明涉及一种场效应晶体管（FET），其包括反向的源极/漏极金属接触，其具有位于第一下部电介质层中的下部和位于第二上部电介质层中的上部。倒置的源极/漏极金属触点的下部具有比上部更大的横截面面积。优选地，倒置的源极/漏极金属接触件的下部具有约0.03毫米2至约3.15微米的横截面积，并且这样的反相源 /漏极金属触点与FET的栅电极间隔约0.001μm至约5μm的距离。

6. 发明申请

US20060148147A1 Mobility enhanced CMOS devices 有权
公开(公告)号：US20060148147A1
公开(公告)日：2006-07-06
申请号：US11362773
申请日：2006-02-28
申请人： Michael Belyansky , Bruce Doris , Oleg Gluschenkov
发明人： Michael Belyansky , Bruce Doris , Oleg Gluschenkov
IPC分类号： H01L21/338
CPC分类号： H01L29/0653 , H01L29/66636 , H01L29/7848
摘要： Compressive or tensile materials are selectively introduced beneath and in alignment with spacer areas and adjacent to channel areas of a semiconductor substrate to enhance or degrade electron and hole mobility in CMOS circuits. A process entails steps of creating dummy spacers, forming a dielectric mandrel (i.e., mask), removing the dummy spacers, etching recesses into the underlying semiconductor substrate, introducing a compressive or tensile material into a portion of each recess, and filling the remainder of each recess with substrate material.

7. 发明授权

US06890833B2 Trench isolation employing a doped oxide trench fill 失效
标题翻译：使用掺杂氧化物沟槽填充的沟槽隔离
公开(公告)号：US06890833B2
公开(公告)日：2005-05-10
申请号：US10397761
申请日：2003-03-26
申请人： Michael Belyansky , Andreas Knorr , Oleg Gluschenkov , Christopher Parks
发明人： Michael Belyansky , Andreas Knorr , Oleg Gluschenkov , Christopher Parks
IPC分类号： H01L21/762 , H01L21/76
CPC分类号： H01L21/76224
摘要： A trench isolation structure is formed in a substrate. One or more openings are formed in a surface of the substrate, and a liner layer is deposited at least along a bottom and sidewalls of the openings. A layer of doped oxide material is deposited at least in the openings, and the substrate is annealed to reflow the layer of doped oxide material. Only a portion near the surface of the substrate is removed from the layer of doped oxide material in the opening. A cap layer is deposited atop a remaining portion of the layer of doped oxide material in the opening.
摘要翻译：在衬底中形成沟槽隔离结构。在基板的表面中形成一个或多个开口，并且至少沿着开口的底部和侧壁沉积衬垫层。至少在开口中沉积一层掺杂的氧化物材料，并且将衬底退火以回流掺杂的氧化物材料层。仅在基片表面附近的部分从开口中的掺杂氧化物材料层中除去。覆盖层沉积在开口中掺杂氧化物材料层的剩余部分的顶部。

8. 发明申请

US20080042174A1 FIELD EFFECT TRANSISTORS (FETS) WITH INVERTED SOURCE/DRAIN METALLIC CONTACTS, AND METHOD OF FABRICATING SAME 有权
标题翻译：具有反相源/漏电金属接触的场效应晶体管（FET）及其制造方法
公开(公告)号：US20080042174A1
公开(公告)日：2008-02-21
申请号：US11923075
申请日：2007-10-24
申请人： Michael Belyansky , Dureseti Chidambarrao , Lawrence Clevenger , Kaushik Kumar , Carl Radens
发明人： Michael Belyansky , Dureseti Chidambarrao , Lawrence Clevenger , Kaushik Kumar , Carl Radens
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L21/76804 , H01L29/6659 , H01L29/7833 , H01L2924/0002 , H01L2924/00
摘要： The present invention relates to an field effect transistor (FET) comprising an inverted source/drain metallic contact that has a lower portion located in a first, lower dielectric layer and an upper portion located in a second, upper dielectric layer. The lower portion of the inverted source/drain metallic contact has a larger cross-sectional area than the upper portion. Preferably, the lower portion of the inverted source/drain metallic contact has a cross-sectional area ranging from about 0.03 μm2 to about 3.15 μm2, and such an inverted source/drain metallic contact is spaced apart from a gate electrode of the FET by a distance ranging from about 0.001 μm to about 5 μm.
摘要翻译：本发明涉及一种场效应晶体管（FET），其包括反向的源极/漏极金属接触，其具有位于第一下部电介质层中的下部和位于第二上部电介质层中的上部。倒置的源极/漏极金属触点的下部具有比上部更大的横截面面积。优选地，倒置的源极/漏极金属接触件的下部具有约0.03毫米2至约3.15微米的横截面积，并且这样的反相源 /漏极金属触点与FET的栅电极间隔约0.001μm至约5μm的距离。

9. 发明授权

US07273638B2 High density plasma oxidation 失效
标题翻译：高密度等离子体氧化
公开(公告)号：US07273638B2
公开(公告)日：2007-09-25
申请号：US10338254
申请日：2003-01-07
申请人： Michael Belyansky , Oleg Glushenkov , Andreas Knorr
发明人： Michael Belyansky , Oleg Glushenkov , Andreas Knorr
IPC分类号： H05H1/46 , B05D3/06 , B05D3/14 , C23C16/40 , C23C16/505 , H01L21/473 , C23C16/509
CPC分类号： H01L21/31658 , C23C8/36 , H01J37/321 , H01J2237/338 , H01L21/02236 , H01L21/02238 , H01L21/02252 , H01L21/31662
摘要： A method of oxidizing a substrate having area of about 30,000 mm2 or more. The surface is preferably comprised of silicon-containing materials, such as silicon, silicon germanium, silicon carbide, silicon nitride, and metal suicides. A mixture of oxygen-bearing gas and diluent gas normally non-reactive to oxygen, such as Ne, Ar, Kr, Xe, and/or Rn are ionized to create a plasma having an electron density of at least about 1e12 cm−3 and containing ambient electrons having an average temperature greater than about 1 eV. The substrate surface is oxidized with energetic particles, comprising primarily atomic oxygen, created in the plasma to form an oxide film of substantially uniform thickness. The oxidation of the substrate takes place at a temperature below about 700° C., e.g., between about room temperature, 20° C., and about 500° C.
摘要翻译：一种氧化具有约30,000mm 2以上面积的基材的方法。该表面优选由含硅材料，例如硅，硅锗，碳化硅，氮化硅和金属硅化物组成。通常对氧气（例如Ne，Ar，Kr，Xe和/或Rn）通常不与氧反应的含氧气体和稀释气体的混合物被电离以产生电子密度为至少约1e12cm -3，并且包含平均温度大于约1eV的环境电子。衬底表面被能量粒子氧化，主要由等离子体中产生的原子氧组成，形成厚度基本均匀的氧化膜。衬底的氧化在低于约700℃的温度下进行，例如在约室温，20℃和约500℃之间。

10. 发明申请

US20070010070A1 FABRICATION OF STRAINED SEMICONDUCTOR-ON-INSULATOR (SSOI) STRUCTURES BY USING STRAINED INSULATING LAYERS 审中-公开
标题翻译：通过使用应变绝缘层制造应变半导体绝缘体（SSOI）结构
公开(公告)号：US20070010070A1
公开(公告)日：2007-01-11
申请号：US11160668
申请日：2005-07-05
申请人： Michael Belyansky , Meikei Ieong , Haizhou Yin
发明人： Michael Belyansky , Meikei Ieong , Haizhou Yin
IPC分类号： H01L21/20 , H01L21/36
CPC分类号： H01L21/76254
摘要： The present invention relates to a method for forming one or more strained semiconductor-on-insulator structures, by first forming a precursor structure that contains an upper layer of unstrained semiconductor material and a lower layer of strained insulating material supported by a semiconductor substrate, and then patterning the upper layer of unstrained semiconductor material and the lower layer of strained insulating material to form one or more islands that each contain an unstrained semiconductor material layer over a strained insulating material layer. Relaxation of the strained insulating material layers in such islands applies strain to the unstrained semiconductor material layers, thus forming one or more strained semiconductor-on-insulator structures. The method of the present invention uses a strained insulating material layer to apply strain to an unstrained semiconductor material layer, and can therefore completely avoid usage of any additional strain-inducing layer in forming strained semiconductor material.
摘要翻译：本发明涉及一种用于形成一个或多个应变的绝缘体上半导体结构的方法，首先形成一个前体结构，该前体结构含有一个上层的无约束半导体材料和一个由半导体衬底支撑的应变绝缘材料层，然后对未应变半导体材料的上层和应变绝缘材料的下层进行构图，以形成一个或多个岛，每个岛在应变绝缘材料层上都包含未应变的半导体材料层。这种岛中的应变绝缘材料层的松弛对未受约束的半导体材料层施加应变，从而形成一个或多个应变绝缘体上的半导体结构。本发明的方法使用应变绝缘材料层将应变施加到未应变半导体材料层，因此可以完全避免在形成应变半导体材料时使用任何额外的应变诱导层。

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