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1. 发明授权

US06967136B2 Method and structure for improved trench processing 失效
标题翻译：改进沟槽加工的方法和结构
公开(公告)号：US06967136B2
公开(公告)日：2005-11-22
申请号：US10604594
申请日：2003-08-01
申请人： Hiroyuki Akatsu , Kangguo Cheng , Kenneth Settlemyer
发明人： Hiroyuki Akatsu , Kangguo Cheng , Kenneth Settlemyer
IPC分类号： H01L21/20 , H01L21/8242
CPC分类号： H01L27/1087 , H01L27/10864
摘要： A method is provided for making a trench capacitor by forming a trench in a substrate. The trench is then widened and a sacrificial collar is formed on sidewalls of the widened trench. The trench is then vertically deepened to extend below the sidewalls of the sacrificial collar. Subsequently, a capacitor is formed in the trench below the sacrificial collar. An integrated circuit includes a deep trench structure formed in a single-crystal region of a semiconductor substrate including an upper trench portion, the upper trench portion having an opening of rectangular shape. A lower trench portion is formed below the upper trench portion. The lower portion may be widened to have a bottle shape. Alternatively, the upper trench portion may be widened relative to the lower trench portion.
摘要翻译：提供一种通过在衬底中形成沟槽来制造沟槽电容器的方法。然后加宽沟槽，并且在加宽的沟槽的侧壁上形成牺牲套环。然后将沟槽垂直加深以在牺牲套环的侧壁下方延伸。随后，在牺牲套环下方的沟槽中形成电容器。集成电路包括形成在包括上沟槽部分的半导体衬底的单晶区域中的深沟槽结构，上沟槽部分具有矩形形状的开口。下沟槽部分形成在上沟槽部分的下方。下部可以被加宽以具有瓶子形状。或者，上沟槽部分可以相对于下沟槽部分加宽。

2. 发明申请

US20050026382A1 METHOD AND STRUCTURE FOR IMPROVED TRENCH PROCESSING 失效
标题翻译：改进TRENCH加工的方法和结构
公开(公告)号：US20050026382A1
公开(公告)日：2005-02-03
申请号：US10604594
申请日：2003-08-01
申请人： Hiroyuki Akatsu , Kangguo Cheng , Kenneth Settlemyer
发明人： Hiroyuki Akatsu , Kangguo Cheng , Kenneth Settlemyer
IPC分类号： H01L21/20 , H01L21/8242
CPC分类号： H01L27/1087 , H01L27/10864
摘要： A method is provided for making a trench capacitor by forming a trench in a substrate. The trench is then widened and a sacrificial collar is formed on sidewalls of the widened trench. The trench is then vertically deepened to extend below the sidewalls of the sacrificial collar. Subsequently, a capacitor is formed in the trench below the sacrificial collar. An integrated circuit includes a deep trench structure formed in a single-crystal region of a semiconductor substrate including an upper trench portion, the upper trench portion having an opening of rectangular shape. A lower trench portion is formed below the upper trench portion. The lower portion may be widened to have a bottle shape. Alternatively, the upper trench portion may be widened relative to the lower trench portion.
摘要翻译：提供一种通过在衬底中形成沟槽来制造沟槽电容器的方法。然后加宽沟槽，并且在加宽的沟槽的侧壁上形成牺牲套环。然后将沟槽垂直加深以在牺牲套环的侧壁下方延伸。随后，在牺牲套环下方的沟槽中形成电容器。集成电路包括形成在包括上沟槽部分的半导体衬底的单晶区域中的深沟槽结构，上沟槽部分具有矩形形状的开口。下沟槽部分形成在上沟槽部分的下方。下部可以被加宽以具有瓶子形状。或者，上沟槽部分可以相对于下沟槽部分加宽。

3. 发明授权

US06806138B1 Integration scheme for enhancing capacitance of trench capacitors 失效
标题翻译：用于增强沟槽电容器电容的集成方案
公开(公告)号：US06806138B1
公开(公告)日：2004-10-19
申请号：US10707890
申请日：2004-01-21
申请人： Kangguo Cheng , Hiroyuki Akatsu , Rama Divakaruni
发明人： Kangguo Cheng , Hiroyuki Akatsu , Rama Divakaruni
IPC分类号： H01L218242
CPC分类号： H01L27/1087 , H01L29/66181 , H01L29/945
摘要： The capacitance of deep trench capacitors is enhanced by increasing the surface area of the doped region of the trench to be used for one electrode of the capacitor. After formation of the deep trench and a collar on an upper region of the trench, and after optional bottling of the trench, hemispherical silicon grain (HSG) is deposited on a lower region of the trench. The HSG is then oxidized, along with that portion of the silicon substrate not covered by HSG, to form a roughened surface in the trench, thereby enhancing the trench capacitance. Oxidation of the HSG and the substrate occurs simultaneously with formation of the buried plate, and the formed oxide may be stripped along with the collar, thereby providing a simpler and more robust capacitance enhancement scheme.
摘要翻译：通过增加用于电容器的一个电极的沟槽的掺杂区域的表面积来增强深沟槽电容器的电容。在沟槽的上部区域形成深沟槽和套环之后，在沟槽的可选装填之后，半沟球硅晶粒（HSG）沉积在沟槽的下部区域上。然后HSG与不被HSG覆盖的硅衬底的那部分一起氧化，以在沟槽中形成粗糙化表面，从而增强沟槽电容。 HSG和衬底的氧化与掩埋板的形成同时发生，并且所形成的氧化物可以与套环一起剥离，从而提供更简单和更坚固的电容增强方案。

4. 发明申请

US20100332444A1 AUTOMATIC DESIGNING SYSTEM, AUTOMATIC DESIGNING METHOD AND AUTOMATIC DESIGNING PROGRAM FOR AUTOMATICALLY DESIGNING ARCHITECTURE FOR SYSTEM COMPONENTS 失效
标题翻译：自动设计系统，自动设计方法和自动设计系统组件结构自动设计程序
公开(公告)号：US20100332444A1
公开(公告)日：2010-12-30
申请号：US12825830
申请日：2010-06-29
申请人： Hiroyuki Akatsu , Hisashi Miyashita , Hiroaki Nakamura , Takashi Nerome
发明人： Hiroyuki Akatsu , Hisashi Miyashita , Hiroaki Nakamura , Takashi Nerome
IPC分类号： G06N5/02 , G06G7/48
CPC分类号： G06N5/025 , G06F17/5095
摘要： An automatic designing system includes: a rule storage unit storing sets of rewrite rules for rewriting variable nodes of a hierarchically structured graph in a design architecture for the system; a search unit sequentially determining variable nodes as application targets for the rewrite rules by searching the graph, including components in the design architecture for the system to be designed, using a search tree; a judgment unit judging whether the rewrite rule is applicable to the determined variable node; and a rule application unit replacing the determined variable node with a partial graph, including at least one of fixed and variable nodes, according to the rewrite rule, in response to a judgment that the rewrite rule is applicable. The search unit performs the searching until an undefined variable node no longer exists in the graph to be designed, and performs backtracking on condition that no variable node is found.
摘要翻译：自动设计系统包括：规则存储单元，用于存储用于重构用于系统的设计架构中用于重写分层结构化图形的可变节点的重写规则; 搜索单元使用搜索树通过搜索包括要设计的系统的设计架构中的组件的图来顺序地将变量节点确定为重写规则的应用目标; 判断单元判断所述重写规则是否适用于所确定的变量节点; 以及规则应用单元，响应于可重写规则的判断，根据重写规则，用包括固定节点和可变节点中的至少一个的部分图替换确定的变量节点。搜索单元执行搜索，直到要设计的图中不再存在未定义的变量节点，并且在没有找到变量节点的条件下执行回溯。

5. 发明申请

US20080052144A1 SYSTEM AND METHOD FOR MANAGING WORKFLOW 失效
标题翻译：用于管理工作流的系统和方法
公开(公告)号：US20080052144A1
公开(公告)日：2008-02-28
申请号：US11776151
申请日：2007-07-11
申请人： Hiroyuki Akatsu , Kenji Eda , Yo Murai , Teruaki Okano , Yasuharu Yada , Masao Yamada
发明人： Hiroyuki Akatsu , Kenji Eda , Yo Murai , Teruaki Okano , Yasuharu Yada , Masao Yamada
IPC分类号： G06F9/46
CPC分类号： G06Q10/06 , G06Q10/063 , G06Q10/0633
摘要： A system and method for managing a workflow are provided. A system for managing a workflow in accordance with an embodiment of the invention includes: a storage unit for storing, as an access history for each of at least one artifact, identification information of a business process that has accessed the artifact; a request reception unit for receiving an access request to an artifact from a user; a first notification unit for retrieving an access history corresponding to a first artifact from the storage unit on a condition that a first access request received from the user corresponding to a first business process is an update request of the first artifact, and for notifying a user corresponding to the business process that is identified in the retrieved access history that the first artifact is to be updated; and a history adding unit for adding identification information of the first business process to the access history corresponding to the first artifact in response to an accessing of the first artifact based on the first access request.
摘要翻译：提供了一种用于管理工作流的系统和方法。根据本发明的实施例的用于管理工作流的系统包括：存储单元，用于存储已访问所述工件的业务处理的识别信息作为至少一个工件中的每一个的访问历史; 请求接收单元，用于从用户接收对工件的访问请求; 第一通知单元，用于在从与第一业务处理对应的用户接收到的第一访问请求是第一伪像的更新请求的条件下从存储单元检索与第一伪像相对应的访问历史，并且用于通知用户对应于在检索的访问历史中识别出的第一个工件将被更新的业务流程; 以及历史添加单元，用于响应于基于第一访问请求访问第一伪像，将第一业务处理的标识信息添加到与第一伪像相对应的访问历史。

6. 发明授权

US07190046B2 Bipolar transistor having reduced collector-base capacitance 失效
标题翻译：双极晶体管具有降低的集电极 - 基极电容
公开(公告)号：US07190046B2
公开(公告)日：2007-03-13
申请号：US10708860
申请日：2004-03-29
申请人： Hiroyuki Akatsu , Rama Divakaruni , Marwan Khater , Christopher M. Schnabel , William Tonti
发明人： Hiroyuki Akatsu , Rama Divakaruni , Marwan Khater , Christopher M. Schnabel , William Tonti
IPC分类号： H01L27/082 , H01L21/331
CPC分类号： H01L29/66242 , H01L29/0649 , H01L29/0692 , H01L29/0821
摘要： Structure and method are provided for forming a bipolar transistor. As disclosed, an intrinsic base layer is provided overlying a collector layer. A low-capacitance region is disposed laterally adjacent the collector layer. The low-capacitance region includes at least one of a dielectric region and a void disposed in an undercut underlying the intrinsic base layer. An emitter layer overlies the intrinsic base layer, and a raised extrinsic base layer overlies the intrinsic base layer.
摘要翻译：提供了用于形成双极晶体管的结构和方法。如所公开的，提供覆盖在集电极层上的本征基层。低电容区域横向设置在集电极层附近。低电容区域包括设置在本征基层下面的底切中的电介质区域和空穴中的至少一个。发射极层覆盖本征基极层，凸起的非本征基极层覆盖本征基极层。

7. 发明申请

US20050212087A1 STRUCTURE AND METHOD OF MAKING A BIPOLAR TRANSISTOR HAVING REDUCED COLLECTOR-BASED CAPACITANCE 失效
标题翻译：具有减少集电极电容的双极晶体管的结构和方法
公开(公告)号：US20050212087A1
公开(公告)日：2005-09-29
申请号：US10708860
申请日：2004-03-29
申请人： Hiroyuki Akatsu , Rama Divakaruni , Marwan Khater , Christopher Schnabel , William Tonti
发明人： Hiroyuki Akatsu , Rama Divakaruni , Marwan Khater , Christopher Schnabel , William Tonti
IPC分类号： H01L21/331 , H01L27/102 , H01L29/06 , H01L29/08
CPC分类号： H01L29/66242 , H01L29/0649 , H01L29/0692 , H01L29/0821
摘要： Structure and method are provided for forming a bipolar transistor. As disclosed, an intrinsic base layer is provided overlying a collector layer. A low-capacitance region is disposed laterally adjacent the collector layer. The low-capacitance region includes at least one of a dielectric region and a void disposed in an undercut underlying the intrinsic base layer. An emitter layer overlies the intrinsic base layer, and a raised extrinsic base layer overlies the intrinsic base layer.
摘要翻译：提供了用于形成双极晶体管的结构和方法。如所公开的，提供覆盖在集电极层上的本征基层。低电容区域横向设置在集电极层附近。低电容区域包括设置在本征基层下面的底切中的电介质区域和空穴中的至少一个。发射极层覆盖本征基极层，凸起的非本征基极层覆盖本征基极层。

8. 发明授权

US06893938B2 STI formation for vertical and planar transistors 有权
标题翻译：垂直和平面晶体管的STI形成
公开(公告)号：US06893938B2
公开(公告)日：2005-05-17
申请号：US10419588
申请日：2003-04-21
申请人： Munir D. Naeem , Hiroyuki Akatsu , Byeong Kim , Rolf Weis , David Mark Dobuzinksy , Johnathan E. Faltermeier
发明人： Munir D. Naeem , Hiroyuki Akatsu , Byeong Kim , Rolf Weis , David Mark Dobuzinksy , Johnathan E. Faltermeier
IPC分类号： H01L21/308 , H01L21/762 , H01L21/76
CPC分类号： H01L21/76232 , H01L21/3081
摘要： A method for forming shallow trench isolation (STI) for semiconductor devices. A first hard mask is deposited over a semiconductor wafer, and a second hard mask is deposited over the first hard mask. The semiconductor wafer includes a first etching zone and at least a second etching zone disposed beneath the first etching zone. The etch process for the first etching zone and the etch process for the at least one second etching zone are selected such that smooth sidewall surface structures are formed within the semiconductor device. The etch processes for each subsequent etching zone may alternate between non-selective and selective etch processes to preserve at least the first hard mask material.
摘要翻译：一种用于形成用于半导体器件的浅沟槽隔离（STI）的方法。第一硬掩模沉积在半导体晶片上，并且第二硬掩模沉积在第一硬掩模上。半导体晶片包括第一蚀刻区和设置在第一蚀刻区下方的至少第二蚀刻区。选择用于第一蚀刻区域的蚀刻工艺和用于至少一个第二蚀刻区域的蚀刻工艺，使得在半导体器件内形成平滑的侧壁表面结构。每个后续蚀刻区域的蚀刻工艺可以在非选择性和选择性蚀刻工艺之间交替，以至少保留第一硬掩模材料。

9. 发明授权

US06809027B2 Self-aligned borderless contacts 有权
公开(公告)号：US06809027B2
公开(公告)日：2004-10-26
申请号：US10165264
申请日：2002-06-06
申请人： Jay W. Strane , Hiroyuki Akatsu , David M. Dobuzinsky
发明人： Jay W. Strane , Hiroyuki Akatsu , David M. Dobuzinsky
IPC分类号： H01L214763
CPC分类号： H01L21/76897
摘要： A method for forming high-density self-aligned contacts and interconnect structures in a semiconductor device. A dielectric layer thick enough to contain both interconnect and contact structures is formed on a substrate. A patterned hardmask is formed on the dielectric layer to define both the interconnect and contact structures. The openings for interconnect features are first formed by partially etching the dielectric layer selective to the hardmask. A second mask (e.g., a resist) is used to define the contact openings, and the dielectric layer is etched through the second mask, also selective to the hardmask, to expose the diffusion regions to be contacted. The patterned hardmask is used to help define the contact openings. Conductive material is then deposited in the openings which results in contacts and interconnects that are self-aligned. By first forming the openings for both interconnect and contacts, savings in processing steps may be obtained.

10. 发明授权

US5932493A Method to minimize watermarks on silicon substrates 失效
标题翻译：最小化硅衬底上的水印的方法
公开(公告)号：US5932493A
公开(公告)日：1999-08-03
申请号：US929590
申请日：1997-09-15
申请人： Hiroyuki Akatsu , Ronald Hoyer , Ravikumar Ramachandran
发明人： Hiroyuki Akatsu , Ronald Hoyer , Ravikumar Ramachandran
IPC分类号： H01L21/304 , H01L21/306 , H01L21/00
CPC分类号： H01L21/02052
摘要： Formation of watermarks during semiconductor processing can be prevented by rinsing silicon wafers in an organic solvent prior to drying. Water droplets on the silicon wafer surface are taken up by the solvent and film is formed over the wafer surface. Following this rinse, the wafer may be subjected to standard IPA-based drying techniques.
摘要翻译：可以通过在干燥之前冲洗有机溶剂中的硅晶片来防止在半导体加工期间形成水印。硅晶片表面上的水滴被溶剂吸收，并且在晶片表面上形成膜。在该冲洗之后，可以对晶片进行标准的基于IPA的干燥技术。

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