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1. 发明申请

US20130120041A1 Leakage Tolerant Delay Locked Loop Circuit Device 有权
标题翻译：泄漏容限延迟锁定环路电路装置
公开(公告)号：US20130120041A1
公开(公告)日：2013-05-16
申请号：US13295351
申请日：2011-11-14
申请人： Michael A. Sorna , Pradeep Thiagarajan
发明人： Michael A. Sorna , Pradeep Thiagarajan
IPC分类号： H03L7/06
CPC分类号： H03L7/0891 , H03L7/0816
摘要： Leakage tolerant delay locked loop (DLL) circuit devices and methods of locking phases of output phase signals to a phase of a reference signal using a leakage tolerant DLL circuit device are provided. Embodiments include a DLL circuit device comprising: a primary loop and a secondary correction circuit. The primary loop includes a phase detector, an error controller, and a voltage controlled buffer (VCB). The secondary correction circuit is configured to generate and provide secondary error-delay signals to the error controller. The secondary correction circuit includes multiple error generators. Each error generator is configured to generate a secondary error-delay signal in response to detecting a particular edge of an output phase signal from the VCB. The primary loop is configured to control a phase adjustment based on at least one of a first error-delay-increase signal, a first error-delay-decrease signal, and the secondary error-delay signals.
摘要翻译：提供了泄漏容限延迟锁定环（DLL）电路装置以及使用泄漏容限DLL电路装置将输出相位信号的相位锁定到参考信号的相位的方法。实施例包括DLL电路装置，包括：主回路和二次校正电路。主回路包括相位检测器，误差控制器和压控缓冲器（VCB）。二次校正电路被配置为产生并向误差控制器提供二次误差延迟信号。二次校正电路包括多个误差发生器。响应于检测到来自VCB的输出相位信号的特定边缘，每个误差发生器被配置为产生二次误差延迟信号。主回路被配置为基于第一误差延迟增加信号，第一误差延迟降低信号和次级误差延迟信号中的至少一个来控制相位调整。

2. 发明授权

US08410835B1 Leakage tolerant phase locked loop circuit device 有权
标题翻译：泄漏容限锁相环电路器件
公开(公告)号：US08410835B1
公开(公告)日：2013-04-02
申请号：US13342453
申请日：2012-01-03
申请人： Michael A. Sorna , Pradeep Thiagarajan
发明人： Michael A. Sorna , Pradeep Thiagarajan
IPC分类号： H03L7/06
CPC分类号： H03L7/101 , H03L7/0891 , H03L7/093
摘要： Leakage tolerant phase locked loop (PLL) circuit devices and methods of locking phases of output phase signals to a phase of a reference signal using a leakage tolerant PLL circuit device are provided. Embodiments include a PLL circuit device comprising: a primary loop and a secondary correction circuit. The primary loop includes a phase detector, an error controller, a voltage controlled oscillator (VCO), and feedback divider. The secondary correction circuit is configured to generate and provide a secondary error-frequency signal to the error controller. The secondary correction circuit is configured to generate the secondary error-frequency signal in response to detecting a particular edge of a divided VCO output signal. The primary loop is configured to control a frequency adjustment based on at least one of a first error-frequency-increase signal, a first error-frequency-decrease signal, and the secondary error-frequency signal.
摘要翻译：提供了泄漏容限锁相环（PLL）电路装置以及使用泄漏容限PLL电路装置将输出相位信号的相位锁定到参考信号的相位的方法。实施例包括PLL电路装置，其包括：主回路和二次校正电路。主回路包括相位检测器，误差控制器，压控振荡器（VCO）和反馈分压器。二次校正电路被配置为产生并向误差控制器提供次级错误频率信号。二次校正电路被配置为响应于检测到分压的VCO输出信号的特定边缘而产生次级错误频率信号。主回路被配置为基于第一误差频率增大信号，第一误差 - 频率降低信号和次级错误频率信号中的至少一个来控制频率调整。

3. 发明授权

US08493117B2 Leakage tolerant delay locked loop circuit device 有权
标题翻译：漏电延迟锁定环路电路装置
公开(公告)号：US08493117B2
公开(公告)日：2013-07-23
申请号：US13295351
申请日：2011-11-14
申请人： Michael A. Sorna , Pradeep Thiagarajan
发明人： Michael A. Sorna , Pradeep Thiagarajan
IPC分类号： H03L7/06
CPC分类号： H03L7/0891 , H03L7/0816
摘要： Leakage tolerant delay locked loop (DLL) circuit devices and methods of locking phases of output phase signals to a phase of a reference signal using a leakage tolerant DLL circuit device are provided. Embodiments include a DLL circuit device comprising: a primary loop and a secondary correction circuit. The primary loop includes a phase detector, an error controller, and a voltage controlled buffer (VCB). The secondary correction circuit is configured to generate and provide secondary error-delay signals to the error controller. The secondary correction circuit includes multiple error generators. Each error generator is configured to generate a secondary error-delay signal in response to detecting a particular edge of an output phase signal from the VCB. The primary loop is configured to control a phase adjustment based on at least one of a first error-delay-increase signal, a first error-delay-decrease signal, and the secondary error-delay signals.
摘要翻译：提供了泄漏容限延迟锁定环（DLL）电路装置以及使用泄漏容限DLL电路装置将输出相位信号的相位锁定到参考信号的相位的方法。实施例包括DLL电路装置，包括：主回路和二次校正电路。主回路包括相位检测器，误差控制器和压控缓冲器（VCB）。二次校正电路被配置为产生并向误差控制器提供二次误差延迟信号。二次校正电路包括多个误差发生器。响应于检测到来自VCB的输出相位信号的特定边缘，每个误差发生器被配置为产生二次误差延迟信号。主回路被配置为基于第一误差延迟增加信号，第一误差延迟降低信号和次级误差延迟信号中的至少一个来控制相位调整。

4. 发明授权

US09009520B2 Closed-loop multiphase slew rate controller for signal drive in a computer system 有权
标题翻译：用于计算机系统中信号驱动的闭环多相转换速率控制器
公开(公告)号：US09009520B2
公开(公告)日：2015-04-14
申请号：US13219816
申请日：2011-08-29
申请人： Marcel A. Kossel , Daihyun Lim , Pradeep Thiagarajan
发明人： Marcel A. Kossel , Daihyun Lim , Pradeep Thiagarajan
IPC分类号： G06F1/04 , G06F1/24 , G06F11/00
CPC分类号： G06F1/04
摘要： A slew rate controller for a computing system includes a slew rate control module, the slew rate control module further comprising a plurality of sampling modules, each sampling module corresponding to one of a plurality of phase signal inputs, wherein each sampling module receives an input signal, a reference voltage, and the sampling module's respective phase signal input, and wherein each sampling module generates a respective sample of a relationship between the input signal and the reference voltage during a time period indicated by the sampling module's respective phase signal input; and a finite state machine configured to output a slew rate control signal to control a slew rate of the input signal based on the plurality of samples from the sampling modules.
摘要翻译：一种用于计算系统的转换速率控制器包括转换速率控制模块，所述转换速率控制模块还包括多个采样模块，每个采样模块对应于多个相位信号输入中的一个，其中每个采样模块接收输入信号参考电压和采样模块各自的相位信号输入，并且其中每个采样模块在由采样模块的各个相位信号输入指示的时间段期间产生输入信号和参考电压之间的关系的相应采样; 以及有限状态机，被配置为基于来自所述采样模块的所述多个采样来输出转换速率控制信号以控制所述输入信号的转换速率。

5. 发明申请

US20120326760A1 PROGRAMMABLE DUTY CYCLE SELECTION USING INCREMENTAL PULSE WIDTHS 失效
标题翻译：可编程脉冲宽度的可编程周期选择
公开(公告)号：US20120326760A1
公开(公告)日：2012-12-27
申请号：US13166126
申请日：2011-06-22
申请人： Grant P. Kesselring , Pradeep Thiagarajan
发明人： Grant P. Kesselring , Pradeep Thiagarajan
IPC分类号： H03K3/017
CPC分类号： H03K3/017
摘要： A method and device for generating a waveform according to programmable duty cycle control bits from a divided frequency reference signal. The device may include: a timing circuit that inputs a CLOCK signal having a 50% duty cycle to a divider, whose output varies over a plurality of divide-by-n settings; and a waveform generator. The waveform generator may, after a last low clock pulse is counted for a current evaluative cycle and before a beginning of a next evaluative cycle, shift a prior duty cycle waveform by ½ of a CLOCK cycle, to provide an incremented duty cycle for the waveform. Alternatively, the waveform generator may increment a gating signal from an adder, which determines an onset of an inoperative or low portion of the programmed duty cycle.
摘要翻译：一种根据来自分频频率参考信号的可编程占空比控制位产生波形的方法和装置。该装置可以包括：定时电路，其将具有50％占空比的CLOCK信号输入到分频器，分频器的输出在多个分频设置上变化; 和波形发生器。波形发生器可以在当前评估周期的最后一个低时钟脉冲被计数并且在下一个评估周期的开始之前，将先前的占空比波形移位到CLOCK周期的1/2，以提供波形的递增占空比。或者，波形发生器可以增加来自加法器的门控信号，该加法器确定编程的占空比的不工作或低部分的开始。

6. 发明授权

US07681152B2 Design structures comprising voltage translator circuits 失效
标题翻译：包括电压转换器电路的设计结构
公开(公告)号：US07681152B2
公开(公告)日：2010-03-16
申请号：US11778106
申请日：2007-07-16
申请人： Ken Short , Pradeep Thiagarajan
发明人： Ken Short , Pradeep Thiagarajan
IPC分类号： G06F17/50 , H03L5/00 , G05F1/10
CPC分类号： H03K19/018521
摘要： A design structure including a voltage translator circuit and a method for operating the same. The voltage translator circuit includes (a) an input node, an output node, and a ground node; (b) a voltage divider circuit including a first and second resistors coupled in series between the input node and the ground node; (c) a first circuit coupled to a first voltage and to the input node; (d) a second circuit coupled to the output node; and (e) a capacitive circuit having a first and second capacitive nodes. The first capacitive node is coupled to the voltage divider circuit. The second capacitive node is coupled (i) to the first voltage via the first circuit, and (ii) to the output node via the second circuit. In response to the input node changing towards the first voltage, the first circuit may disconnect the second capacitive node from the first voltage.
摘要翻译：包括电压转换器电路的设计结构及其操作方法。电压转换器电路包括（a）输入节点，输出节点和接地节点; （b）分压器电路，包括串联耦合在输入节点和接地节点之间的第一和第二电阻器; （c）耦合到第一电压和输入节点的第一电路; （d）耦合到所述输出节点的第二电路; 和（e）具有第一和第二电容性节点的电容电路。第一电容节点耦合到分压器电路。第二电容性节点经由第一电路耦合到第一电压，以及（ii）经由第二电路耦合到输出节点。响应于输入节点朝向第一电压变化，第一电路可以将第二电容性节点与第一电压断开。

7. 发明申请

US20080191752A1 METHOD FOR DIVIDING A HIGH-FREQUENCY SIGNAL 有权
标题翻译：分配高频信号的方法
公开(公告)号：US20080191752A1
公开(公告)日：2008-08-14
申请号：US12103129
申请日：2008-04-15
申请人： John S. Austin , Ram Kelkar , Pradeep Thiagarajan
发明人： John S. Austin , Ram Kelkar , Pradeep Thiagarajan
IPC分类号： H03K21/00
CPC分类号： H03K23/667 , H03K5/04 , H03K5/05 , H03K5/1565 , H03K21/10 , H03K21/38 , H03K23/44 , H03K23/52
摘要： A method for dividing a high-frequency signal. The method including: generating, from a first clock signal, a second clock signal, the second clock cycle time greater than the first clock cycle time, an off-time of one cycle of the second clock signal being one first clock cycle time less than an on-time of one cycle of the second clock signal; shifting in time the second clock signal by half of a first clock cycle time to generate a third clock signal, the second clock cycle time equal to the third clock cycle time; performing a logical AND of the second clock signal and the third clock signal to generate a fourth clock signal, the third clock cycle time equal to the fourth clock cycle time, an on-time of one cycle of the fourth clock signal equal to an off-time of one cycle of the fourth clock signal.
摘要翻译：一种分频高频信号的方法。该方法包括：从第一时钟信号产生第二时钟信号，第二时钟周期时间大于第一时钟周期时间，第二时钟信号的一个周期的关闭时间是一个第一时钟周期时间小于第二时钟信号的一个周期的导通时间; 将第二时钟信号的时间偏移到第一时钟周期时间的一半以产生第三时钟信号，第二时钟周期时间等于第三时钟周期时间; 执行第二时钟信号和第三时钟信号的逻辑与以产生第四时钟信号，第三时钟周期时间等于第四时钟周期时间，第四时钟信号的一个周期的导通时间等于关 - 第四个时钟信号的一个周期的时间。

8. 发明申请

US20080148204A1 Clock Distribution Network, Structure, And Method For Providing Balanced Loading In Integrated Circuit Clock Trees 失效
公开(公告)号：US20080148204A1
公开(公告)日：2008-06-19
申请号：US11610963
申请日：2006-12-14
申请人： Serafino Bueti , Hayden C. Cranford , Joseph A. Iadanza , Pradeep Thiagarajan , Sebastian T. Ventrone
发明人： Serafino Bueti , Hayden C. Cranford , Joseph A. Iadanza , Pradeep Thiagarajan , Sebastian T. Ventrone
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F2217/62
摘要： A clock distribution network, structure, and method for providing balanced loading is disclosed. In particular, a clock distribution network may be formed of one or more clock fanout distribution levels. Each respective distribution level may include an equal number of buffer circuits and wiring routes that have substantially identical physical and electrical properties. Additionally, a final distribution level may include wiring routes that have substantially identical physical and electrical properties connecting buffer circuits to one or more logic leaf connection nodes.

9. 发明授权

US07362138B1 Flexible multimode logic element for use in a configurable mixed-logic signal distribution path 有权
标题翻译：灵活的多模逻辑元件用于可配置的混合逻辑信号分配路径
公开(公告)号：US07362138B1
公开(公告)日：2008-04-22
申请号：US11613516
申请日：2006-12-20
申请人： Igor Arsovski , Anthony R. Bonaccio , Hayden C. Cranford, Jr. , Joseph A. Iadanza , Pradeep Thiagarajan , Sebastian T. Ventrone
发明人： Igor Arsovski , Anthony R. Bonaccio , Hayden C. Cranford, Jr. , Joseph A. Iadanza , Pradeep Thiagarajan , Sebastian T. Ventrone
IPC分类号： H03K19/0175
CPC分类号： H03K19/018585 , H03K3/35613 , H03K5/133 , H03K19/0016 , H03K2005/00058 , H03K2005/00208 , H03K2005/00228
摘要： A multimode circuit that is configured to operate in one of multiple operating modes is disclosed. In particular, an exemplary multimode circuit may be configured to operating in one of a full-swing mode, a limited-swing mode, a full-swing to limited-swing converter mode, and a limited-swing to full-swing converter mode. The operating modes of the multimode circuit may be dynamically selectable. One or more multimode circuits may be part of a configurable distribution path for controlling the performance of a signal distribution path or tree of an integrated circuit.
摘要翻译：公开了一种被配置为以多种操作模式之一操作的多模电路。特别地，示例性多模电路可以被配置为以全摆动模式，限制摆动模式，全摆幅至限定摆动转换器模式和限定摆动至全摆幅转换器模式之一进行操作。多模电路的工作模式可以动态地选择。一个或多个多模电路可以是用于控制集成电路的信号分配路径或树的性能的可配置分配路径的一部分。

10. 发明授权

US07180973B2 Programmable low-power high-frequency divider 失效
标题翻译：可编程低功耗高分频器
公开(公告)号：US07180973B2
公开(公告)日：2007-02-20
申请号：US11374766
申请日：2006-03-14
申请人： John S. Austin , Ram Kelkar , Pradeep Thiagarajan
发明人： John S. Austin , Ram Kelkar , Pradeep Thiagarajan
IPC分类号： H03K21/00 , H03K23/00
CPC分类号： H03K23/667 , H03K5/04 , H03K5/05 , H03K5/1565 , H03K21/10 , H03K21/38 , H03K23/44 , H03K23/52
摘要： A fast latch including: a NAND stage adapted to receive a clock signal and a data input signal; a clocked inverter stage, a first input of the clocked inverter stage coupled to the output of the NAND stage and a second input of the clocked inverter stage coupled to the clock signal; a first inverter stage, a first input of the first inverter stage coupled to an output of the clocked inverter and a second input of the first inverter stage coupled to a reset signal; and a second inverter stage, having an output, an input of the second inverter stage coupled to an output of the first inverter stage. The fast latch is suitable for use in frequency divider circuits also described. A homologue of frequency dividers using the fast latch, a unique 3/4 divider and a 2 divider not using the fast latch are also disclosed.
摘要翻译：一种快速锁存器，包括：适于接收时钟信号和数据输入信号的NAND级; 时钟反相器级，被连接到NAND级的输出的时钟反相级的第一输入和与时钟信号耦合的时钟反相级的第二输入; 第一反相器级，耦合到所述时钟反相器的输出的第一反相器级的第一输入和耦合到复位信号的第一反相器级的第二输入; 以及第二反相器级，具有输出，所述第二反相器级的输入耦合到所述第一反相器级的输出。快速锁存器适用于还描述的分频器电路。还公开了使用快速锁存器的分频器的同系物，独特的3/4分频器和不使用快速锁存器的2分频器。

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