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1. 发明授权

US09009520B2 Closed-loop multiphase slew rate controller for signal drive in a computer system 有权
标题翻译：用于计算机系统中信号驱动的闭环多相转换速率控制器
公开(公告)号：US09009520B2
公开(公告)日：2015-04-14
申请号：US13219816
申请日：2011-08-29
申请人： Marcel A. Kossel , Daihyun Lim , Pradeep Thiagarajan
发明人： Marcel A. Kossel , Daihyun Lim , Pradeep Thiagarajan
IPC分类号： G06F1/04 , G06F1/24 , G06F11/00
CPC分类号： G06F1/04
摘要： A slew rate controller for a computing system includes a slew rate control module, the slew rate control module further comprising a plurality of sampling modules, each sampling module corresponding to one of a plurality of phase signal inputs, wherein each sampling module receives an input signal, a reference voltage, and the sampling module's respective phase signal input, and wherein each sampling module generates a respective sample of a relationship between the input signal and the reference voltage during a time period indicated by the sampling module's respective phase signal input; and a finite state machine configured to output a slew rate control signal to control a slew rate of the input signal based on the plurality of samples from the sampling modules.
摘要翻译：一种用于计算系统的转换速率控制器包括转换速率控制模块，所述转换速率控制模块还包括多个采样模块，每个采样模块对应于多个相位信号输入中的一个，其中每个采样模块接收输入信号参考电压和采样模块各自的相位信号输入，并且其中每个采样模块在由采样模块的各个相位信号输入指示的时间段期间产生输入信号和参考电压之间的关系的相应采样; 以及有限状态机，被配置为基于来自所述采样模块的所述多个采样来输出转换速率控制信号以控制所述输入信号的转换速率。

2. 发明申请

US20130055006A1 CLOSED-LOOP MULTIPHASE SLEW RATE CONTROLLER 有权
标题翻译：闭环多相速率控制器
公开(公告)号：US20130055006A1
公开(公告)日：2013-02-28
申请号：US13219816
申请日：2011-08-29
申请人： Marcel A. Kossel , Daihyun Lim , Pradeep Thiagarajan
发明人： Marcel A. Kossel , Daihyun Lim , Pradeep Thiagarajan
IPC分类号： G06F1/04
CPC分类号： G06F1/04
摘要： A slew rate controller for a computing system includes a slew rate control module, the slew rate control module further comprising a plurality of sampling modules, each sampling module corresponding to one of a plurality of phase signal inputs, wherein each sampling module receives an input signal, a reference voltage, and the sampling module's respective phase signal input, and wherein each sampling module generates a respective sample of a relationship between the input signal and the reference voltage during a time period indicated by the sampling module's respective phase signal input; and a finite state machine configured to output a slew rate control signal to control a slew rate of the input signal based on the plurality of samples from the sampling modules.
摘要翻译：一种用于计算系统的转换速率控制器包括转换速率控制模块，所述转换速率控制模块还包括多个采样模块，每个采样模块对应于多个相位信号输入中的一个，其中每个采样模块接收输入信号参考电压和采样模块各自的相位信号输入，并且其中每个采样模块在由采样模块的各个相位信号输入指示的时间段期间产生输入信号和参考电压之间的关系的相应采样; 以及有限状态机，被配置为基于来自所述采样模块的所述多个采样来输出转换速率控制信号以控制所述输入信号的转换速率。

3. 发明申请

US20140028363A1 PHASE ROTATOR BASED ON VOLTAGE REFERENCING 有权
标题翻译：基于电压参考的相位旋转器
公开(公告)号：US20140028363A1
公开(公告)日：2014-01-30
申请号：US13556237
申请日：2012-07-24
申请人： Daihyun Lim , Marcel A. Kossel , Pradeep Thiagarajan
发明人： Daihyun Lim , Marcel A. Kossel , Pradeep Thiagarajan
IPC分类号： H03K5/13
CPC分类号： H03K5/13
摘要： A phase rotator based on voltage referencing is disclosed. A voltage signal is generated that is proportional to the phase difference between two input signals. The voltage signal is then used as the upper voltage limit for a digital-to-analog converter (DAC). The DAC is programmable via an input vector to generate a DAC output. The DAC output is used to generate a phase rotated (phase shifted) output, which is at an intermediate phase between the two input signals.
摘要翻译：公开了一种基于电压参考的相位旋转器。产生与两个输入信号之间的相位差成比例的电压信号。然后将电压信号用作数模转换器（DAC）的上限电压。 DAC可通过输入矢量进行编程，以产生DAC输出。 DAC输出用于产生在两个输入信号之间处于中间相位的相位旋转（相移）输出。

4. 发明授权

US08466722B2 Startup and protection circuitry for thin oxide output stage 有权
标题翻译：薄氧化物输出级的启动和保护电路
公开(公告)号：US08466722B2
公开(公告)日：2013-06-18
申请号：US13284265
申请日：2011-10-28
申请人： Marcel A. Kossel , Daihyun Lim , Christian I. Menolfi , Pradeep Thiagarajan
发明人： Marcel A. Kossel , Daihyun Lim , Christian I. Menolfi , Pradeep Thiagarajan
IPC分类号： H03L7/00
CPC分类号： H01L27/0266
摘要： A method for startup and operation of an output stage of a transmitter, the output stage comprising a first protection field effect transistor (FET) and a second protection FET includes enabling a startup circuit; providing a first bias voltage to the first protection FET in the output stage and a second bias voltage to the second protection FET stage in the output stage by the startup circuit; disabling the startup circuit and enabling a protection voltage generator; providing the first bias voltage to the first protection FET in the output stage by the protection voltage generator; and providing the second bias voltage to the second protection FET in the output stage by a second bias voltage power supply.
摘要翻译：一种用于启动和操作发射机的输出级的方法，所述输出级包括第一保护场效应晶体管（FET）和第二保护FET，使能启动电路; 向所述输出级中的所述第一保护FET提供第一偏置电压，以及通过所述启动电路向所述输出级中的所述第二保护FET级提供第二偏置电压; 禁用启动电路并启用保护电压发生器; 通过保护电压发生器向输出级中的第一保护FET提供第一偏置电压; 以及通过第二偏置电压电源在所述输出级中向所述第二保护FET提供所述第二偏置电压。

5. 发明授权

US08686776B2 Phase rotator based on voltage referencing 有权
标题翻译：基于电压参考的相位旋转器
公开(公告)号：US08686776B2
公开(公告)日：2014-04-01
申请号：US13556237
申请日：2012-07-24
申请人： Daihyun Lim , Marcel A. Kossel , Pradeep Thiagarajan
发明人： Daihyun Lim , Marcel A. Kossel , Pradeep Thiagarajan
IPC分类号： H03H11/16
CPC分类号： H03K5/13
摘要： A phase rotator based on voltage referencing is disclosed. A voltage signal is generated that is proportional to the phase difference between two input signals. The voltage signal is then used as the upper voltage limit for a digital-to-analog converter (DAC). The DAC is programmable via an input vector to generate a DAC output. The DAC output is used to generate a phase rotated (phase shifted) output, which is at an intermediate phase between the two input signals.
摘要翻译：公开了一种基于电压参考的相位旋转器。产生与两个输入信号之间的相位差成比例的电压信号。然后将电压信号用作数模转换器（DAC）的上限电压。 DAC可通过输入矢量进行编程，以产生DAC输出。 DAC输出用于产生在两个输入信号之间处于中间相位的相位旋转（相移）输出。

6. 发明申请

US20140035643A1 EQUALIZED RISE AND FALL SLEW RATES FOR A BUFFER 有权
标题翻译：均衡的上升和缓冲器的缓冲率
公开(公告)号：US20140035643A1
公开(公告)日：2014-02-06
申请号：US13567214
申请日：2012-08-06
申请人： Marcel A. Kossel , Daihyun Lim , Pradeep Thiagarajan
发明人： Marcel A. Kossel , Daihyun Lim , Pradeep Thiagarajan
IPC分类号： H03K5/12
CPC分类号： H03K19/00361
摘要： Aspects of the invention provide for equalizing rise and fall slew rates at an output for a buffer. In one embodiment, a method includes: measuring, simultaneously, rise and fall slew rates at an input of the buffer and rise and fall slew rates at the output of the buffer; generating a slew reference based on at least one of the rise slew rate or the fall slew rate at the input of the buffer; comparing the rise slew rate and the fall slew rate at the output of the buffer to the slew reference; and generating at least one of a rise control signal or a fall control signal for adjusting at least one of the rise slew rate or the fall slew rate at the output of the buffer.
摘要翻译：本发明的方面提供了用于平衡缓冲器的输出端的上升和下降转换速率。在一个实施例中，一种方法包括：同时测量缓冲器输入端的上升和下降转换速率以及缓冲器输出端的上升和下降转换速率; 基于所述缓冲器的输入端的上升转换速率或所述下降转换速率中的至少一个产生转换参考; 将缓冲器输出端的上升转换速率与下降转换速率进行比较; 以及生成上升控制信号或下降控制信号中的至少一个，用于调整在缓冲器的输出处的上升转换速率或下降转换速率中的至少一个。

7. 发明授权

US08638149B1 Equalized rise and fall slew rates for a buffer 有权
标题翻译：缓冲器的平均上升和下降转换速率
公开(公告)号：US08638149B1
公开(公告)日：2014-01-28
申请号：US13567214
申请日：2012-08-06
申请人： Marcel A. Kossel , Daihyun Lim , Pradeep Thiagarajan
发明人： Marcel A. Kossel , Daihyun Lim , Pradeep Thiagarajan
IPC分类号： H03K5/12
CPC分类号： H03K19/00361
摘要： Aspects of the invention provide for equalizing rise and fall slew rates at an output for a buffer. In one embodiment, a method includes: measuring, simultaneously, rise and fall slew rates at an input of the buffer and rise and fall slew rates at the output of the buffer; generating a slew reference based on at least one of the rise slew rate or the fall slew rate at the input of the buffer; comparing the rise slew rate and the fall slew rate at the output of the buffer to the slew reference; and generating at least one of a rise control signal or a fall control signal for adjusting at least one of the rise slew rate or the fall slew rate at the output of the buffer.
摘要翻译：本发明的方面提供了用于平衡缓冲器的输出端的上升和下降转换速率。在一个实施例中，一种方法包括：同时测量缓冲器输入端的上升和下降转换速率，以及缓冲器输出端的上升和下降转换速率; 基于所述缓冲器的输入端的上升转换速率或所述下降转换速率中的至少一个产生转换参考; 将缓冲器输出端的上升转换速率与下降转换速率进行比较; 以及生成上升控制信号或下降控制信号中的至少一个，用于调整在缓冲器的输出处的上升转换速率或下降转换速率中的至少一个。

8. 发明授权

US08519761B1 Closed-loop slew-rate control for phase interpolator optimization 有权
标题翻译：用于相位插值器优化的闭环压摆率控制
公开(公告)号：US08519761B1
公开(公告)日：2013-08-27
申请号：US13480573
申请日：2012-05-25
申请人： Marcel A. Kossel , Daihyun Lim , Pradeep Thiagarajan
发明人： Marcel A. Kossel , Daihyun Lim , Pradeep Thiagarajan
IPC分类号： H03K5/12
CPC分类号： H03K5/13 , H03K2005/00052
摘要： A slew rate control circuit generates a slew-rate controlled clock signal from an input clock signal based on a feedback control mechanism. The feedback control mechanism uses the input clock signal duty cycle characteristics as a reference for controlling and maintaining an optimum slew rate for the slew-rate controlled clock signal. By using the input clock signal as a reference, the slew-rate controlled clock signal is dynamically measured and periodically adjusted over each cycle of the input clock signal.
摘要翻译：转换速率控制电路基于反馈控制机构从输入时钟信号生成转换速率控制的时钟信号。反馈控制机构使用输入时钟信号占空比特性作为控制和保持用于转换速率控制的时钟信号的最佳转换速率的参考。通过使用输入时钟信号作为参考，在输入时钟信号的每个周期上动态地测量和定期调整压摆率控制的时钟信号。

9. 发明申请

US20130106474A1 STARTUP AND PROTECTION CIRCUITRY FOR THIN OXIDE OUTPUT STAGE 有权
标题翻译：用于氧化物输出级的启动和保护电路
公开(公告)号：US20130106474A1
公开(公告)日：2013-05-02
申请号：US13284265
申请日：2011-10-28
申请人： Marcel A. Kossel , Daihyun Lim , Christian I. Menolfi , Pradeep Thiagarajan
发明人： Marcel A. Kossel , Daihyun Lim , Christian I. Menolfi , Pradeep Thiagarajan
IPC分类号： H03L7/00
CPC分类号： H01L27/0266
摘要： A method for startup and operation of an output stage of a transmitter, the output stage comprising a first protection field effect transistor (FET) and a second protection FET includes enabling a startup circuit; providing a first bias voltage to the first protection FET in the output stage and a second bias voltage to the second protection FET stage in the output stage by the startup circuit; disabling the startup circuit and enabling a protection voltage generator; providing the first bias voltage to the first protection FET in the output stage by the protection voltage generator; and providing the second bias voltage to the second protection FET in the output stage by a second bias voltage power supply.
摘要翻译：一种用于启动和操作发射机的输出级的方法，所述输出级包括第一保护场效应晶体管（FET）和第二保护FET，使能启动电路; 向所述输出级中的所述第一保护FET提供第一偏置电压，以及通过所述启动电路向所述输出级中的所述第二保护FET级提供第二偏置电压; 禁用启动电路并启用保护电压发生器; 通过保护电压发生器向输出级中的第一保护FET提供第一偏置电压; 以及通过第二偏置电压电源在所述输出级中向所述第二保护FET提供所述第二偏置电压。

10. 发明申请

US20120326760A1 PROGRAMMABLE DUTY CYCLE SELECTION USING INCREMENTAL PULSE WIDTHS 失效
标题翻译：可编程脉冲宽度的可编程周期选择
公开(公告)号：US20120326760A1
公开(公告)日：2012-12-27
申请号：US13166126
申请日：2011-06-22
申请人： Grant P. Kesselring , Pradeep Thiagarajan
发明人： Grant P. Kesselring , Pradeep Thiagarajan
IPC分类号： H03K3/017
CPC分类号： H03K3/017
摘要： A method and device for generating a waveform according to programmable duty cycle control bits from a divided frequency reference signal. The device may include: a timing circuit that inputs a CLOCK signal having a 50% duty cycle to a divider, whose output varies over a plurality of divide-by-n settings; and a waveform generator. The waveform generator may, after a last low clock pulse is counted for a current evaluative cycle and before a beginning of a next evaluative cycle, shift a prior duty cycle waveform by ½ of a CLOCK cycle, to provide an incremented duty cycle for the waveform. Alternatively, the waveform generator may increment a gating signal from an adder, which determines an onset of an inoperative or low portion of the programmed duty cycle.
摘要翻译：一种根据来自分频频率参考信号的可编程占空比控制位产生波形的方法和装置。该装置可以包括：定时电路，其将具有50％占空比的CLOCK信号输入到分频器，分频器的输出在多个分频设置上变化; 和波形发生器。波形发生器可以在当前评估周期的最后一个低时钟脉冲被计数并且在下一个评估周期的开始之前，将先前的占空比波形移位到CLOCK周期的1/2，以提供波形的递增占空比。或者，波形发生器可以增加来自加法器的门控信号，该加法器确定编程的占空比的不工作或低部分的开始。

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