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1. 发明授权

US07545191B2 Method for dividing a high-frequency signal 有权
标题翻译：高频信号分频方法
公开(公告)号：US07545191B2
公开(公告)日：2009-06-09
申请号：US12103129
申请日：2008-04-15
申请人： John S. Austin , Ram Kelkar , Pradeep Thiagarajan
发明人： John S. Austin , Ram Kelkar , Pradeep Thiagarajan
IPC分类号： H03K3/017 , H03K5/04
CPC分类号： H03K23/667 , H03K5/04 , H03K5/05 , H03K5/1565 , H03K21/10 , H03K21/38 , H03K23/44 , H03K23/52
摘要： A method for dividing a high-frequency signal. The method including: generating, from a first clock signal, a second clock signal, the second clock cycle time greater than the first clock cycle time, an off-time of one cycle of the second clock signal being one first clock cycle time less than an on-time of one cycle of the second clock signal; shifting in time the second clock signal by half of a first clock cycle time to generate a third clock signal, the second clock cycle time equal to the third clock cycle time; performing a logical AND of the second clock signal and the third clock signal to generate a fourth clock signal, the third clock cycle time equal to the fourth clock cycle time, an on-time of one cycle of the fourth clock signal equal to an off-time of one cycle of the fourth clock signal.
摘要翻译：一种分频高频信号的方法。该方法包括：从第一时钟信号产生第二时钟信号，第二时钟周期时间大于第一时钟周期时间，第二时钟信号的一个周期的关闭时间是一个第一时钟周期时间小于第二时钟信号的一个周期的导通时间; 将第二时钟信号的时间偏移到第一时钟周期时间的一半以产生第三时钟信号，第二时钟周期时间等于第三时钟周期时间; 执行第二时钟信号和第三时钟信号的逻辑与以产生第四时钟信号，第三时钟周期时间等于第四时钟周期时间，第四时钟信号的一个周期的导通时间等于关 - 第四个时钟信号的一个周期的时间。

2. 发明授权

US07342429B2 Programmable low-power high-frequency divider 有权
标题翻译：可编程低功耗高分频器
公开(公告)号：US07342429B2
公开(公告)日：2008-03-11
申请号：US11325786
申请日：2006-01-05
申请人： John S. Austin , Ram Kelkar , Pradeep Thiagarajan
发明人： John S. Austin , Ram Kelkar , Pradeep Thiagarajan
IPC分类号： H03K3/289
CPC分类号： H03K23/52 , H03K5/04 , H03K5/05 , H03K5/1565 , H03K21/10 , H03K21/38 , H03K23/44 , H03K23/667
摘要： Several latch circuits including a NAND gate stage and combinations of clocked inverter stages and inverter stages are described. A programmable frequency divider including homologue frequency divider circuits using the latch circuits is also described. Also described is a circuit included in the homologue frequency divides and a method for correcting the duty cycle of clock signals generated by the homologue frequency dividers to 50%.
摘要翻译：描述了包括NAND门级和时钟反相器级和反相器级的组合的多个锁存电路。还描述了包括使用锁存电路的同步分频器电路的可编程分频器。还描述了同源分频器中包括的电路和用于校正由同系分频器产生的时钟信号的占空比为50％的方法。

3. 发明申请

US20080191752A1 METHOD FOR DIVIDING A HIGH-FREQUENCY SIGNAL 有权
标题翻译：分配高频信号的方法
公开(公告)号：US20080191752A1
公开(公告)日：2008-08-14
申请号：US12103129
申请日：2008-04-15
申请人： John S. Austin , Ram Kelkar , Pradeep Thiagarajan
发明人： John S. Austin , Ram Kelkar , Pradeep Thiagarajan
IPC分类号： H03K21/00
CPC分类号： H03K23/667 , H03K5/04 , H03K5/05 , H03K5/1565 , H03K21/10 , H03K21/38 , H03K23/44 , H03K23/52
摘要： A method for dividing a high-frequency signal. The method including: generating, from a first clock signal, a second clock signal, the second clock cycle time greater than the first clock cycle time, an off-time of one cycle of the second clock signal being one first clock cycle time less than an on-time of one cycle of the second clock signal; shifting in time the second clock signal by half of a first clock cycle time to generate a third clock signal, the second clock cycle time equal to the third clock cycle time; performing a logical AND of the second clock signal and the third clock signal to generate a fourth clock signal, the third clock cycle time equal to the fourth clock cycle time, an on-time of one cycle of the fourth clock signal equal to an off-time of one cycle of the fourth clock signal.
摘要翻译：一种分频高频信号的方法。该方法包括：从第一时钟信号产生第二时钟信号，第二时钟周期时间大于第一时钟周期时间，第二时钟信号的一个周期的关闭时间是一个第一时钟周期时间小于第二时钟信号的一个周期的导通时间; 将第二时钟信号的时间偏移到第一时钟周期时间的一半以产生第三时钟信号，第二时钟周期时间等于第三时钟周期时间; 执行第二时钟信号和第三时钟信号的逻辑与以产生第四时钟信号，第三时钟周期时间等于第四时钟周期时间，第四时钟信号的一个周期的导通时间等于关 - 第四个时钟信号的一个周期的时间。

4. 发明授权

US07180973B2 Programmable low-power high-frequency divider 失效
标题翻译：可编程低功耗高分频器
公开(公告)号：US07180973B2
公开(公告)日：2007-02-20
申请号：US11374766
申请日：2006-03-14
申请人： John S. Austin , Ram Kelkar , Pradeep Thiagarajan
发明人： John S. Austin , Ram Kelkar , Pradeep Thiagarajan
IPC分类号： H03K21/00 , H03K23/00
CPC分类号： H03K23/667 , H03K5/04 , H03K5/05 , H03K5/1565 , H03K21/10 , H03K21/38 , H03K23/44 , H03K23/52
摘要： A fast latch including: a NAND stage adapted to receive a clock signal and a data input signal; a clocked inverter stage, a first input of the clocked inverter stage coupled to the output of the NAND stage and a second input of the clocked inverter stage coupled to the clock signal; a first inverter stage, a first input of the first inverter stage coupled to an output of the clocked inverter and a second input of the first inverter stage coupled to a reset signal; and a second inverter stage, having an output, an input of the second inverter stage coupled to an output of the first inverter stage. The fast latch is suitable for use in frequency divider circuits also described. A homologue of frequency dividers using the fast latch, a unique 3/4 divider and a 2 divider not using the fast latch are also disclosed.
摘要翻译：一种快速锁存器，包括：适于接收时钟信号和数据输入信号的NAND级; 时钟反相器级，被连接到NAND级的输出的时钟反相级的第一输入和与时钟信号耦合的时钟反相级的第二输入; 第一反相器级，耦合到所述时钟反相器的输出的第一反相器级的第一输入和耦合到复位信号的第一反相器级的第二输入; 以及第二反相器级，具有输出，所述第二反相器级的输入耦合到所述第一反相器级的输出。快速锁存器适用于还描述的分频器电路。还公开了使用快速锁存器的分频器的同系物，独特的3/4分频器和不使用快速锁存器的2分频器。

5. 发明授权

US06917662B2 Programmable low-power high-frequency divider 有权
标题翻译：可编程低功耗高分频器
公开(公告)号：US06917662B2
公开(公告)日：2005-07-12
申请号：US10661050
申请日：2003-09-11
申请人： John S. Austin , Ram Kelkar , Pradeep Thiagarajan
发明人： John S. Austin , Ram Kelkar , Pradeep Thiagarajan
IPC分类号： H03K23/64 , H03K5/156 , H03K21/00 , H03K21/10 , H03K21/38 , H03K23/44 , H03K23/66
CPC分类号： H03K23/667 , H03K5/04 , H03K5/05 , H03K5/1565 , H03K21/10 , H03K21/38 , H03K23/44 , H03K23/52
摘要： A fast latch including: a NAND stage adapted to receive a clock signal and a data input signal; a clocked inverter stage, a first input of the clocked inverter stage coupled to the output of the NAND stage and a second input of the clocked inverter stage coupled to the clock signal; a first inverter stage, a first input of the first inverter stage coupled to an output of the clocked inverter and a second input of the first inverter stage coupled to a reset signal; and a second inverter stage, having an output, an input of the second inverter stage coupled to an output of the first inverter stage. The fast latch is suitable for use in frequency divider circuits also described. A homologue of frequency dividers using the fast latch, a unique 3/4 divider and a 2 divider not using the fast latch are also disclosed.
摘要翻译：一种快速锁存器，包括：适于接收时钟信号和数据输入信号的NAND级; 时钟反相器级，被连接到NAND级的输出的时钟反相级的第一输入和与时钟信号耦合的时钟反相级的第二输入; 第一反相器级，耦合到所述时钟反相器的输出的第一反相器级的第一输入和耦合到复位信号的第一反相器级的第二输入; 以及第二反相器级，具有输出，所述第二反相器级的输入耦合到所述第一反相器级的输出。快速锁存器适用于还描述的分频器电路。还公开了使用快速锁存器的分频器的同系物，独特的3/4分频器和不使用快速锁存器的2分频器。

6. 发明授权

US07378890B2 Programmable low-power high-frequency divider 有权
公开(公告)号：US07378890B2
公开(公告)日：2008-05-27
申请号：US11857632
申请日：2007-09-19
申请人： John S. Austin , Ram Kelkar , Pradeep Thiagarajan
发明人： John S. Austin , Ram Kelkar , Pradeep Thiagarajan
IPC分类号： H03K3/289 , H03K3/356
CPC分类号： H03K23/52 , H03K5/04 , H03K5/05 , H03K5/1565 , H03K21/10 , H03K21/38 , H03K23/44 , H03K23/667
摘要： Several latch circuits including a NAND gate stage and combinations of clocked inverter stages and inverter stages are described. A programmable frequency divider including homologue frequency divider circuits using the latch circuits is also described. Also described is a circuit included in the homologue frequency divides and a method for correcting the duty cycle of clock signals generated by the homologue frequency dividers to 50%.

7. 发明授权

US07075350B2 Programmable low-power high-frequency divider 失效
公开(公告)号：US07075350B2
公开(公告)日：2006-07-11
申请号：US11070730
申请日：2005-03-02
申请人： John S. Austin , Ram Kelkar , Pradeep Thiagarajan
发明人： John S. Austin , Ram Kelkar , Pradeep Thiagarajan
IPC分类号： H03K3/356
CPC分类号： H03K23/667 , H03K5/04 , H03K5/05 , H03K5/1565 , H03K21/10 , H03K21/38 , H03K23/44 , H03K23/52
摘要： A fast latch including: a NAND stage adapted to receive a clock signal and a data input signal; a clocked inverter stage, a first input of the clocked inverter stage coupled to the output of the NAND stage and a second input of the clocked inverter stage coupled to the clock signal; a first inverter stage, a first input of the first inverter stage coupled to an output of the clocked inverter and a second input of the first inverter stage coupled to a reset signal; and a second inverter stage, having an output, an input of the second inverter stage coupled to an output of the first inverter stage. The fast latch is suitable for use in frequency divider circuits also described. A homologue of frequency dividers using the fast latch, a unique 3/4 divider and a 2 divider not using the fast latch are also disclosed.

8. 发明授权

US6057719A Programmable, self-resetting divider 失效
标题翻译：可编程，自复位分频器
公开(公告)号：US6057719A
公开(公告)日：2000-05-02
申请号：US92412
申请日：1998-06-05
申请人： John S. Austin , Ram Kelkar
发明人： John S. Austin , Ram Kelkar
IPC分类号： H03K23/54 , H03K23/66 , H03L7/183 , H03B19/00
CPC分类号： H03K23/54 , H03K23/665 , H03L7/183
摘要： A programmable, self-resetting divider includes a modified Linear Feedback Shift Register (LFSR) counter that starts in an initial state and increments through a count range. The self-resetting divider also includes a reset circuit that detects a pre-selected final state of the modified LFSR counter, provides an output signal in response to the detecting of the final state, and provides a reset signal to the modified LFSR counter in response to the detecting of the final state.
摘要翻译：可编程的自复位分频器包括一个修改后的线性反馈移位寄存器（LFSR）计数器，该计数器以初始状态启动并递增计数范围。自复位分配器还包括复位电路，其检测修改的LFSR计数器的预先选择的最终状态，响应于最终状态的检测提供输出信号，并且响应地向修改的LFSR计数器提供复位信号以检测最终状态。

9. 发明授权

US6009139A Asynchronously programmable frequency divider circuit with a symmetrical output 失效
标题翻译：具有对称输出的异步可编程分频电路
公开(公告)号：US6009139A
公开(公告)日：1999-12-28
申请号：US100541
申请日：1998-06-19
申请人： John S. Austin , Ram Kelkar
发明人： John S. Austin , Ram Kelkar
IPC分类号： H03K23/54 , H03K23/66 , H03K21/00
CPC分类号： H03K23/54 , H03K23/66
摘要： A programmable divider circuit having an adjustable shift register is coupled to a clock and to an output. The shift register receives a clock signal having a clock signal frequency and outputs an output signal with an output frequency corresponding to a user selected divide ratio of the clock signal frequency. Control inputs are coupled to the adjustable shift register to receive control data for adjusting a length of the shift register, the length of the shift register corresponding to the user selected divide ratio.
摘要翻译：具有可调节移位寄存器的可编程分频器电路被耦合到时钟和输出。移位寄存器接收具有时钟信号频率的时钟信号，并输出具有对应于时钟信号频率的用户选择的分频比的输出频率的输出信号。控制输入耦合到可调节移位寄存器，以接收用于调整移位寄存器长度的控制数据，移位寄存器的长度对应于用户选择的分频比。

10. 发明授权

US5151619A CMOS off chip driver circuit 失效
标题翻译： CMOS OFF芯片驱动电路
公开(公告)号：US5151619A
公开(公告)日：1992-09-29
申请号：US595911
申请日：1990-10-11
申请人： John S. Austin , Ronald A. Piro , Douglas W. Stout
发明人： John S. Austin , Ronald A. Piro , Douglas W. Stout
IPC分类号： H01L27/092 , H01L21/8238 , H03K19/003 , H03K19/0185 , H03K19/0948
CPC分类号： H03K19/00315 , H03K19/0948
摘要： A CMOS off-chip driver circuit is provided which includes a P-channel pull up transistor and an N-channel pull down transistor serially arranged between a first voltage source having a supply voltage of a given magnitude and ground with the common point between the transistors forming an output terminal to which is connected a circuit including a second voltage source having a supply voltage of a magnitude significantly greater than that of the given magnitude. A first P-channel field effect transistor is connected between the output terminal and the gate electrode of the pull up transistor. A first input terminal is coupled to the gate electrode of the pull up transistor through a transmission gate including a first N-channel field effect transistor arranged in parallel with a second P-channel field effect transistor, with a gate electrode of the first N-channel transistor being connected to the first voltage source and the gate electrode of the second P-channel transistor being connected to the output terminal.

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