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1. 发明授权

US5987081A Method and apparatus for a testable high frequency synchronizer 失效
标题翻译：用于可测试的高频同步器的方法和装置
公开(公告)号：US5987081A
公开(公告)日：1999-11-16
申请号：US884253
申请日：1997-06-27
申请人： Michael A. Csoppenszky , Kevin B. Normoyle , Prakash Narain
发明人： Michael A. Csoppenszky , Kevin B. Normoyle , Prakash Narain
IPC分类号： G06F5/06 , H04L7/00 , H04L7/02
CPC分类号： G06F5/06 , H04L7/0012 , H04L7/02 , H04L7/0004
摘要： A synchronizer comprised in part of a series of flip-flops is used to deterministically transfer data between clock domains during system test. Flip-flops in the clock domain operating at a higher clock frequency have a clock enable signal. The clock enable signal is defined so as to approximately align the enabled rising clock edges of the faster clock signal with the falling edges of the slower clock signal. This approximate alignment provides a timing window of one half period of the slower clock for the data to stabilize at the input of a flip-flop in the faster clock domain before it is sampled. This ensures deterministic transfer of data. Data flow control circuitry can be used to provide a ready signal to the faster clock domain to indicate that the synchronizer is available to transfer a synchronization signal. After testing is complete, the synchronizer can operate in an application mode wherein one or more of the clock enable signals is set to a continuous high level to minimize latency.
摘要翻译：在系统测试期间，使用包括在一系列触发器中的同步器来确定性地在时钟域之间传送数据。在较高时钟频率下操作的时钟域中的触发器具有时钟使能信号。时钟使能信号被定义为使得较快时钟信号的使能的上升时钟沿与较慢时钟信号的下降沿近似对准。这种近似对准提供了较慢时钟的一个半周期的定时窗口，以便数据在采样之前在更快的时钟域中稳定在触发器的输入端。这确保数据的确定性传输。数据流控制电路可用于向较快的时钟域提供就绪信号，以指示同步器可用于传送同步信号。测试完成后，同步器可以以应用模式工作，其中一个或多个时钟使能信号被设置为连续的高电平以最小化等待时间。

2. 发明授权

US5852608A Structure and method for bi-directional data transfer between asynchronous clock domains 失效
标题翻译：异步时钟域之间双向数据传输的结构和方法
公开(公告)号：US5852608A
公开(公告)日：1998-12-22
申请号：US659729
申请日：1996-06-06
申请人： Michael A. Csoppenszky , Kevin B. Normoyle
发明人： Michael A. Csoppenszky , Kevin B. Normoyle
IPC分类号： G06F5/06 , G06F12/00
CPC分类号： G06F5/065
摘要： Bi-directional data transfers between a first system and a second system, which have asynchronous clock domains, are performed using a single dual-port memory. A direction control circuit, which is connected between the first and second systems, determines the desired direction of data transfer and generates one or more direction signals representative of this direction. A write control circuit is coupled to receive a direction control signal, as well as write control signals from the first and second systems. Similarly, a read control signal is coupled to receive a direction control signal, as well as read control signals from the first and second systems. If data transfer is to proceed from the first system to the second system, the write control circuit gives the first system control over the write port of the dual-port memory, and the read control circuit gives the second system control over the read port of the dual-port memory in response to the direction control signals. Conversely, if data transfer is to proceed from the second system to the first system, the write control circuit gives the second system control over the write port of the dual-port memory, and the read control circuit gives the first system control over the read port of the dual-port memory in response to the direction control signals.
摘要翻译：具有异步时钟域的第一系统和第二系统之间的双向数据传输使用单个双端口存储器执行。连接在第一和第二系统之间的方向控制电路确定期望的数据传送方向，并产生代表该方向的一个或多个方向信号。写入控制电路被耦合以接收方向控制信号，以及来自第一和第二系统的写入控制信号。类似地，读控制信号被耦合以接收方向控制信号，以及从第一和第二系统读取控制信号。如果从第一系统进行数据传输到第二系统，则写入控制电路对双端口存储器的写入端口进行第一系统控制，并且读取控制电路对第二系统的读取端口进行第二系统控制响应方向控制信号的双端口存储器。相反，如果数据传输从第二系统进行到第一系统，则写入控制电路对双端口存储器的写入端口进行第二系统控制，并且读取控制电路对读取的第一系统进行控制端口的双端口存储器响应方向控制信号。

3. 发明授权

US06553435B1 DMA transfer method for a system including a single-chip processor with a processing core and a device interface in different clock domains 有权
标题翻译：包括具有处理核心的单芯片处理器和不同时钟域中的器件接口的系统的DMA传输方法
公开(公告)号：US06553435B1
公开(公告)日：2003-04-22
申请号：US09229013
申请日：1999-01-12
申请人： Kevin B. Normoyle , Michael A. Csoppenszky , Jaybharat Boddu , Jui-Cheng Su , Alex S. Han , Rajasekhar Cherabuddi , Tzungren Tzeng
发明人： Kevin B. Normoyle , Michael A. Csoppenszky , Jaybharat Boddu , Jui-Cheng Su , Alex S. Han , Rajasekhar Cherabuddi , Tzungren Tzeng
IPC分类号： G06F1328
CPC分类号： G06F12/0897 , G06F12/0888 , G06F12/1054 , G06F12/1081 , G06F13/28 , G06F15/7832
摘要： A single-chip central processing unit (CPU) includes a processing core and a complete cache-coherent I/O system that operates asynchronously with the processing core. An internal communications protocol uses synchronizers and data buffers to transfer information between a clock domain of the processing core and a clock domain of the I/O system. The synchronizers transfer control and handshake signal between clock domains, but the data buffer transfers data without input or output synchronization circuitry for data bits. Throughput for the system is high because the processing unit has direct access to I/O system so that no delays are incurred for complex mechanisms which are commonly employed between a CPU and an external I/O chip-set. Throughput is further increased by holding data from one DMA transfer in the data buffer for use in a subsequent DMA transfer. In one embodiment, the integrated I/O system contains a dedicated memory management unit including a translation lookaside buffer which converts I/O addresses to physical addresses for the processing core.
摘要翻译：单芯片中央处理单元（CPU）包括处理核心和与处理核心异步运行的完整高速缓存相干I / O系统。内部通信协议使用同步器和数据缓冲器在处理核心的时钟域和I / O系统的时钟域之间传输信息。同步器在时钟域之间传送控制和握手信号，但是数据缓冲器传输数据，而不需要输入或输出同步电路来进行数据位。系统的吞吐量很高，因为处理单元可以直接访问I / O系统，以便在CPU和外部I / O芯片组之间通常采用的复杂机制不会产生延迟。通过保存来自数据缓冲器中的一个DMA传输的数据以进行后续DMA传输来进一步增加吞吐量。在一个实施例中，集成I / O系统包含专用存储器管理单元，其包括将I / O地址转换为处理核的物理地址的翻译后备缓冲器。

4. 发明授权

US5884100A Low-latency, high-throughput, integrated cache coherent I/O system for a single-chip processor 失效
标题翻译：用于单芯片处理器的低延迟，高吞吐量的集成缓存一致I / O系统
公开(公告)号：US5884100A
公开(公告)日：1999-03-16
申请号：US660026
申请日：1996-06-06
申请人： Kevin B. Normoyle , Michael A. Csoppenszky , Jaybharat Boddu , Jui-Cheng Su , Alex S. Han , Rajasekhar Cherabuddi , Tzungren Tzeng
发明人： Kevin B. Normoyle , Michael A. Csoppenszky , Jaybharat Boddu , Jui-Cheng Su , Alex S. Han , Rajasekhar Cherabuddi , Tzungren Tzeng
IPC分类号： G06F12/08 , G06F12/10 , G06F13/28 , G06F15/78 , G06F13/00
CPC分类号： G06F12/0897 , G06F12/1081 , G06F13/28 , G06F15/7832 , G06F12/0888 , G06F12/1054
摘要： A single-chip central processing unit (CPU) includes a processing core and a complete cache-coherent I/O system that operates asynchronously with the processing core. An internal communications protocol uses synchronizers and data buffers to transfer information between a clock domain of the processing core and a clock domain of the I/O system. The synchronizers transfer control and handshake signal between clock domains, but the data buffer transfers data without input or output synchronization circuitry for data bits. Throughput for the system is high because the processing unit has direct access to I/O system so that no delays are incurred for complex mechanisms which are commonly employed between a CPU and an external I/O chip-set. Throughput is further increased by holding data from one DMA transfer in the data buffer for use in a subsequent DMA transfer. In one embodiment, the integrated I/O system contains a dedicated memory management unit including a translation lookaside buffer which converts I/O addresses to physical addresses for the processing core.
摘要翻译：单芯片中央处理单元（CPU）包括处理核心和与处理核心异步运行的完整高速缓存相干I / O系统。内部通信协议使用同步器和数据缓冲器在处理核心的时钟域和I / O系统的时钟域之间传输信息。同步器在时钟域之间传送控制和握手信号，但是数据缓冲器传输数据，而不需要输入或输出同步电路来进行数据位。系统的吞吐量很高，因为处理单元可以直接访问I / O系统，以便在CPU和外部I / O芯片组之间通常采用的复杂机制不会产生延迟。通过保存来自数据缓冲器中的一个DMA传输的数据以进行后续DMA传输来进一步增加吞吐量。在一个实施例中，集成I / O系统包含专用存储器管理单元，其包括将I / O地址转换为处理核的物理地址的翻译后备缓冲器。

5. 发明申请

US20080235558A1 Subsystem and Method for Encoding 64-bit Data Nibble Error Correct and Cyclic-Redundancy Code (CRC) Address Error Detect for Use in a 76-bit Memory Module 有权
标题翻译：用于编码64位数据半字节错误正确和循环冗余码（CRC）的子系统和方法用于76位内存模块的地址错误检测
公开(公告)号：US20080235558A1
公开(公告)日：2008-09-25
申请号：US12132839
申请日：2008-06-04
申请人： Kevin B. Normoyle , Robert G. Hathaway
发明人： Kevin B. Normoyle , Robert G. Hathaway
IPC分类号： H03M13/05 , G06F11/10
CPC分类号： G06F11/1016 , G11C5/04 , G11C7/1006 , G11C2029/0409
摘要： A memory system provides data error detection and correction and address error detection. A cyclical-redundancy-check (CRC) code generates address check bits. A 32-bit address is compressed to 6 address check bits using the CRC code. The 6 address check bits are concatenated with 64 data bits and 2 flag bits to generate a 72-bit check word. The 72-bit check word is input to an error-correction code (ECC) generator that generates 12 check bits that are stored in memory with the 64 data bits. A 76-bit memory module can store the 64 data and 12 check bits. Nibble errors can be corrected, and all nibble+1 bit errors can be detected. Also, a 6-bit error in a sequence of bits can be detected. This allows all errors in the 6-bit CRC of the address to be detected. The CRC code and ECC are ideal for detecting double-bit errors common with multiplexed-address DRAMs.
摘要翻译：存储器系统提供数据错误检测和校正以及地址错误检测。循环冗余校验（CRC）代码生成地址校验位。使用CRC代码将32位地址压缩为6个地址校验位。 6个地址校验位连接64个数据位和2个标志位，以产生72位校验字。 72位检查字被输入到纠错码（ECC）发生器中，该纠错码产生12个校验位，存储在64位数据位的存储器中。 76位存储器模块可以存储64个数据和12个校验位。可以纠正半字节错误，并且可以检测到所有的半字节+ 1位错误。此外，可以检测位序列中的6位错误。这允许检测地址的6位CRC中的所有错误。 CRC码和ECC是检测复用地址DRAM共同的双位错误的理想选择。

6. 发明授权

US07398449B1 Encoding 64-bit data nibble error correct and cyclic-redundancy code (CRC) address error detect for use on a 76-bit memory module 有权
标题翻译：编码64位数据半字节错误纠错和循环冗余码（CRC）地址错误检测用于76位内存模块
公开(公告)号：US07398449B1
公开(公告)日：2008-07-08
申请号：US11161042
申请日：2005-07-20
申请人： Kevin B. Normoyle , Robert G. Hathaway
发明人： Kevin B. Normoyle , Robert G. Hathaway
IPC分类号： H03M13/00
CPC分类号： G06F11/1016 , G11C5/04 , G11C7/1006 , G11C2029/0409
摘要： A memory system provides data error detection and correction and address error detection. A cyclical-redundancy-check (CRC) code generates address check bits. A 32-bit address is compressed to 6 address check bits using the CRC code. The 6 address check bits are concatenated with 64 data bits and 2 flag bits to generate a 72-bit check word. The 72-bit check word is input to an error-correction code (ECC) generator that generates 12 check bits that are stored in memory with the 64 data bits. A 76-bit memory module can store the 64 data and 12 check bits. Nibble errors can be corrected, and all nibble+1 bit errors can be detected. Also, a 6-bit error in a sequence of bits can be detected. This allows all errors in the 6-bit CRC of the address to be detected. The CRC code and ECC are ideal for detecting double-bit errors common with multiplexed-address DRAMs.
摘要翻译：存储器系统提供数据错误检测和校正以及地址错误检测。循环冗余校验（CRC）代码生成地址校验位。使用CRC代码将32位地址压缩为6个地址校验位。 6个地址校验位连接64个数据位和2个标志位，以产生72位校验字。 72位检查字被输入到纠错码（ECC）发生器中，该纠错码产生12个校验位，存储在64位数据位的存储器中。 76位存储器模块可以存储64个数据和12个校验位。可以纠正半字节错误，并且可以检测到所有的半字节+ 1位错误。此外，可以检测位序列中的6位错误。这允许检测地址的6位CRC中的所有错误。 CRC码和ECC是检测复用地址DRAM共同的双位错误的理想选择。

7. 发明授权

US5070475A Floating point unit interface 失效
标题翻译：浮点单元接口
公开(公告)号：US5070475A
公开(公告)日：1991-12-03
申请号：US797856
申请日：1985-11-14
申请人： Kevin B. Normoyle , James M. Guyer , Rainer Vogt , Anthony S. Fong
发明人： Kevin B. Normoyle , James M. Guyer , Rainer Vogt , Anthony S. Fong
IPC分类号： G06F9/28 , G06F9/22 , G06F9/38
CPC分类号： G06F9/3877 , G06F9/3885
摘要： A data processing system which includes a floating point computation unit (FPU) which interfaces with a central processing unit (CPU) in which the CPU supplies a dispatch control signal to inform the FPU that it is about to execute a floating point macroinstruction and supplies a dispatch address which includes the starting address of the floating point microinstructions therefor during the same operating cycle that the dispatch control signal is supplied. A buffer memory is provided in the FPU to store the starting address of one decoded macroinstruction while a sequence of microinstructions for a previously decoded macroinstruction is being executed by the FPU. When the buffer already has a starting address resident in its buffer the FPU supplies a control signal to prevent the CPU from supplying a further dispatch address until the buffer is empty. Other control signals for synchronizing the CPU and FPU operations and data transfers are also provided.
摘要翻译：一种数据处理系统，包括与中央处理单元（CPU）连接的浮点计算单元（FPU），其中CPU提供调度控制信号以通知FPU它即将执行浮点宏指令，并提供调度地址，其在提供调度控制信号的相同操作周期期间包括其浮点微指令的起始地址。在FPU中提供缓冲存储器以存储一个解码的宏指令的起始地址，而FPU正在执行先前解码的宏指令的微指令序列。当缓冲区已经存在驻留在其缓冲器中的起始地址时，FPU提供控制信号，以防止CPU提供进一步的调度地址，直到缓冲区为空。还提供了用于同步CPU和FPU操作和数据传输的其他控制信号。

8. 发明授权

US5907485A Method and apparatus for flow control in packet-switched computer system 失效
标题翻译：分组交换计算机系统中流控制的方法和装置
公开(公告)号：US5907485A
公开(公告)日：1999-05-25
申请号：US414875
申请日：1995-03-31
申请人： William C. Van Loo , Zahir Ebrahim , Satyanarayana Nishtala , Kevin B. Normoyle , Leslie Kohn , Louis F. Coffin, III
发明人： William C. Van Loo , Zahir Ebrahim , Satyanarayana Nishtala , Kevin B. Normoyle , Leslie Kohn , Louis F. Coffin, III
IPC分类号： G06F9/46 , G06F13/24 , G05B15/00
CPC分类号： G06F9/546 , G06F13/24
摘要： This invention describes a link-by-link flow control method for packet-switched uniprocessor and multiprocessor computer systems that maximizes system resource utilization and throughput, and minimizes system latency. The computer system comprises one or more master interfaces, one or more slave interfaces, and an interconnect system controller which provides dedicated transaction request queues for each master interface and controls the forwarding of transactions to each slave interface. The master interface keeps track of the number of requests in the dedicated queue in the system controller, and the system controller keeps track of the number of requests in each slave interface queue. Both the master interface, and system controller know the maximum capacity of the queue immediately downstream from it, and does not issue more transaction requests than what the downstream queue can accommodate. An acknowledgment from the downstream queue indicates to the sender that there is space in it for another transaction. Thus no system resources are wasted trying to send a request to a queue that is already full.
摘要翻译：本发明描述了一种用于分组交换单处理器和多处理器计算机系统的链路链路流控制方法，其使系统资源利用率和吞吐量最大化，并最小化系统等待时间。计算机系统包括一个或多个主接口，一个或多个从接口和互连系统控制器，其为每个主接口提供专用事务请求队列，并且控制事务到每个从接口的转发。主接口跟踪系统控制器中专用队列中的请求数，系统控制器跟踪每个从接口队列中的请求数。主接口和系统控制器都知道其下游队列的最大容量，并且不会比下游队列可以容纳更多的事务请求。来自下游队列的确认向发送方指示在其中存在另一个事务的空间。因此，尝试将请求发送到已满的队列时，不会浪费任何系统资源。

9. 发明授权

US07332929B1 Wide-scan on-chip logic analyzer with global trigger and interleaved SRAM capture buffers 有权
标题翻译：具有全局触发和交错SRAM捕获缓冲器的宽扫描片上逻辑分析仪
公开(公告)号：US07332929B1
公开(公告)日：2008-02-19
申请号：US11308048
申请日：2006-03-03
申请人： Kevin B. Normoyle , Sreenivas Reddy , John Phillips
发明人： Kevin B. Normoyle , Sreenivas Reddy , John Phillips
IPC分类号： G06F11/00 , G01R31/28
CPC分类号： G01R31/318533 , G01R31/3177 , G11C29/16 , G11C2029/1208
摘要： A system chip has many local blocks including processor cores, caches, and memory controllers. Each local block has a local sample-select mux that is controlled by a local selection control register. The mux selects from among hundreds of internal sample nodes in the local block, and can also pass through samples output by an upstream local block. The selected samples from local blocks are sent to a central on-chip logic analyzer that compares the samples to a maskable trigger value. When the trigger value is matched, a trigger state machine advances, and samples are stored into a central capture buffer. A user debugging the chip can later read out the central capture buffer at a slower speed. Thousands of internal nodes from local blocks can be selected for sampling, triggering, and debugging. Local blocks include valid bits in 64-bit-wide samples. Only valid samples are written to the capture buffer.
摘要翻译：系统芯片具有许多本地块，包括处理器核心，高速缓存和存储器控制器。每个本地块具有由本地选择控制寄存器控制的本地采样选择多路复用器。多路复用器从本地块中的数百个内部采样节点中进行选择，并且还可以通过上游本地块输出的采样。来自本地块的所选样本被发送到中央片上逻辑分析仪，将样本与可屏蔽触发值进行比较。当触发值匹配时，触发状态机将前进，并将样本存储到中央捕获缓冲区中。调试芯片的用户可以稍后以较慢的速度读出中央捕获缓冲区。可以选择来自本地块的数千个内部节点进行采样，触发和调试。本地块包括64位宽的采样中的有效位。只有有效的样本被写入捕获缓冲区。

10. 发明授权

US06496917B1 Method to reduce memory latencies by performing two levels of speculation 有权
标题翻译：通过执行两级投机来减少内存延迟的方法
公开(公告)号：US06496917B1
公开(公告)日：2002-12-17
申请号：US09499264
申请日：2000-02-07
申请人： Rajasekhar Cherabuddi , Kevin B. Normoyle , Brian J. McGee , Meera Kasinathan , Anup Sharma , Sutikshan Bhutani
发明人： Rajasekhar Cherabuddi , Kevin B. Normoyle , Brian J. McGee , Meera Kasinathan , Anup Sharma , Sutikshan Bhutani
IPC分类号： G06F1200
CPC分类号： G06F12/0831 , G06F2212/2542 , G06F2212/507
摘要： A multiprocessor system includes a plurality of central processing units (CPUs) connected to one another by a system bus. Each CPU includes a cache controller to communicate with its cache, and a primary memory controller to communicate with its primary memory. When there is a cache miss in a CPU, the cache controller routes an address request for primary memory directly to the primary memory via the CPU as a speculative request without access the system bus, and also issues the address request to the system bus to facilitate data coherency. The speculative request is queued in the primary memory controller, which in turn retrieves speculative data from a specified primary memory address. The CPU monitors the system bus for a subsequent transaction that requests the specified data in the primary memory. If the subsequent transaction requesting the specified data is a read transaction that corresponds to the speculative address request, the speculative request is validated and becomes non-speculative. If, on the other hand, the subsequent transaction requesting the specified data is a write transaction, the speculative request is canceled.
摘要翻译：多处理器系统包括通过系统总线相互连接的多个中央处理单元（CPU）。每个CPU包括与其高速缓存通信的高速缓存控制器以及与其主存储器通信的主存储器控制器。当CPU中存在高速缓存未命中时，缓存控制器将主存储器的地址请求直接通过CPU作为推测请求直接发送到主存储器，而无需访问系统总线，并且还向系统总线发出地址请求以方便数据一致性。推测请求在主存储器控制器中排队，主存储器控制器又从指定的主存储器地址检索推测数据。 CPU监视系统总线以用于请求主存储器中指定数据的后续事务。如果请求指定数据的后续事务是与推测地址请求相对应的读事务，则推测请求将被验证并变为非推测性。另一方面，如果请求指定数据的后续事务是写事务，则推测请求被取消。

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