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    • 4. 发明授权
    • Floating point unit interface
    • 浮点单元接口
    • US5070475A
    • 1991-12-03
    • US797856
    • 1985-11-14
    • Kevin B. NormoyleJames M. GuyerRainer VogtAnthony S. Fong
    • Kevin B. NormoyleJames M. GuyerRainer VogtAnthony S. Fong
    • G06F9/28G06F9/22G06F9/38
    • G06F9/3877G06F9/3885
    • A data processing system which includes a floating point computation unit (FPU) which interfaces with a central processing unit (CPU) in which the CPU supplies a dispatch control signal to inform the FPU that it is about to execute a floating point macroinstruction and supplies a dispatch address which includes the starting address of the floating point microinstructions therefor during the same operating cycle that the dispatch control signal is supplied. A buffer memory is provided in the FPU to store the starting address of one decoded macroinstruction while a sequence of microinstructions for a previously decoded macroinstruction is being executed by the FPU. When the buffer already has a starting address resident in its buffer the FPU supplies a control signal to prevent the CPU from supplying a further dispatch address until the buffer is empty. Other control signals for synchronizing the CPU and FPU operations and data transfers are also provided.
    • 一种数据处理系统,包括与中央处理单元(CPU)连接的浮点计算单元(FPU),其中CPU提供调度控制信号以通知FPU它即将执行浮点宏指令,并提供 调度地址,其在提供调度控制信号的相同操作周期期间包括其浮点微指令的起始地址。 在FPU中提供缓冲存储器以存储一个解码的宏指令的起始地址,而FPU正在执行先前解码的宏指令的微指令序列。 当缓冲区已经存在驻留在其缓冲器中的起始地址时,FPU提供控制信号,以防止CPU提供进一步的调度地址,直到缓冲区为空。 还提供了用于同步CPU和FPU操作和数据传输的其他控制信号。
    • 9. 发明授权
    • Encachement apparatus
    • 包装装置
    • US4471431A
    • 1984-09-11
    • US425033
    • 1982-09-27
    • Rainer Vogt
    • Rainer Vogt
    • G06F12/10G06F13/00
    • G06F12/1036
    • Encachement apparatus consisting of a first cache, a second cache connected to the first cache, registers for storing data, an adder receiving inputs from a first multiplexer connected to the first cache and a second multiplexer connected to the second cache and to the registers, and control apparatus connected to the first cache, the first multiplexer, and the second multiplexer. The first cache outputs a cache entry in response to a key. The cache entry contains a first displacement value, a base specifier specifying either one of the registers or the second cache, and in the case of entries specifying the second cache, a second displacement value. The first displacement value is output to the first multiplexer, the base specifier is output to the control apparatus, and the second displacement, if present, is output to the second cache. The control apparatus responds to the base specifier by causing the first multiplexer to select the displacement value output by the cache and causing the second multiplexer to select one of the values contained in the registers or the value output by the second cache in response to the second displacement. The adder then adds the value selected by the first multiplexer to the value selected by the second multiplexer and outputs the result.
    • 由第一高速缓存,连接到第一高速缓存的第二高速缓存,用于存储数据的寄存器,接收来自连接到第一高速缓存的第一多路复用器的输入的加法器和连接到第二高速缓存的第二多路复用器和寄存器组成的加密设备,以及 连接到第一高速缓存的控制装置,第一多路复用器和第二多路复用器。 第一个缓存响应于一个密钥输出缓存条目。 高速缓存条目包含第一位移值,指定寄存器或第二高速缓存之一的基本指定符,以及在指定第二高速缓存的条目的情况下,存在第二位移值。 第一位移值被输出到第一多路复用器,基本说明符被输出到控制装置,并且第二位移(如果存在)被输出到第二高速缓存。 控制装置通过使第一多路复用器选择高速缓存输出的位移值并使第二多路复用器响应于第二多路复用器选择寄存器中包含的值之一或由第二高速缓存输出的值 移位。 然后,加法器将由第一多路复用器选择的值添加到由第二多路复用器选择的值,并输出结果。