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1. 发明申请

US20090184423A1 LOW RESISTANCE AND INDUCTANCE BACKSIDE THROUGH VIAS AND METHODS OF FABRICATING SAME 有权
标题翻译：通过VIAS的低电阻和电感及其制造方法
公开(公告)号：US20090184423A1
公开(公告)日：2009-07-23
申请号：US12410728
申请日：2009-03-25
申请人： Mete Erturk , Robert A. Groves , Jeffrey Bowman Johnson , Alvin Jose Joseph , Qizhi Liu , Edmund Juris Sprogis , Anthony Kendall Stamper
发明人： Mete Erturk , Robert A. Groves , Jeffrey Bowman Johnson , Alvin Jose Joseph , Qizhi Liu , Edmund Juris Sprogis , Anthony Kendall Stamper
IPC分类号： H01L23/48 , H01L21/30
CPC分类号： H01L21/76898 , H01L23/481 , H01L2924/0002 , H01L2924/00
摘要： A backside contact structure and method of fabricating the structure. The method includes: forming a dielectric isolation in a substrate, the substrate having a frontside and an opposing backside; forming a first dielectric layer on the frontside of the substrate; forming a trench in the first dielectric layer, the trench aligned over and within a perimeter of the dielectric isolation and extending to the dielectric isolation; extending the trench formed in the first dielectric layer through the dielectric isolation and into the substrate to a depth less than a thickness of the substrate; filling the trench and co-planarizing a top surface of the trench with a top surface of the first dielectric layer to form an electrically conductive through via; and thinning the substrate from a backside of the substrate to expose the through via.
摘要翻译：背面接触结构及其制造方法。该方法包括：在衬底中形成电介质隔离，所述衬底具有前侧和相对的背面; 在所述基板的前侧形成第一电介质层; 在所述第一电介质层中形成沟槽，所述沟槽在所述电介质隔离的周边内并且在所述介电隔离的周边内对准并且延伸到所述电介质隔将形成在第一电介质层中的沟槽通过电介质隔离延伸到衬底中至小于衬底厚度的深度; 填充沟槽并将沟槽的顶表面与第一介电层的顶表面共平面化以形成导电通孔; 并从衬底的背面稀释衬底以露出通孔。

2. 发明授权

US07851923B2 Low resistance and inductance backside through vias and methods of fabricating same 有权
标题翻译：低电阻和电感背面穿过通孔及其制造方法
公开(公告)号：US07851923B2
公开(公告)日：2010-12-14
申请号：US12410728
申请日：2009-03-25
申请人： Mete Erturk , Robert A. Groves , Jeffrey Bowman Johnson , Alvin Jose Joseph , Qizhi Liu , Edmund Juris Sprogis , Anthony Kendall Stamper
发明人： Mete Erturk , Robert A. Groves , Jeffrey Bowman Johnson , Alvin Jose Joseph , Qizhi Liu , Edmund Juris Sprogis , Anthony Kendall Stamper
IPC分类号： H01L23/48
CPC分类号： H01L21/76898 , H01L23/481 , H01L2924/0002 , H01L2924/00
摘要： A backside contact structure and method of fabricating the structure. The method includes: forming a dielectric isolation in a substrate, the substrate having a frontside and an opposing backside; forming a first dielectric layer on the frontside of the substrate; forming a trench in the first dielectric layer, the trench aligned over and within a perimeter of the dielectric isolation and extending to the dielectric isolation; extending the trench formed in the first dielectric layer through the dielectric isolation and into the substrate to a depth less than a thickness of the substrate; filling the trench and co-planarizing a top surface of the trench with a top surface of the first dielectric layer to form an electrically conductive through via; and thinning the substrate from a backside of the substrate to expose the through via.
摘要翻译：背面接触结构及其制造方法。该方法包括：在衬底中形成电介质隔离，所述衬底具有前侧和相对的背面; 在所述基板的前侧形成第一电介质层; 在所述第一电介质层中形成沟槽，所述沟槽在所述电介质隔离的周边内并且在所述介电隔离的周边内对准并且延伸到所述电介质隔将形成在第一电介质层中的沟槽通过电介质隔离延伸到衬底中至小于衬底厚度的深度; 填充沟槽并将沟槽的顶表面与第一介电层的顶表面共平面化以形成导电通孔; 并从衬底的背面稀释衬底以露出通孔。

3. 发明授权

US07563714B2 Low resistance and inductance backside through vias and methods of fabricating same 有权
标题翻译：低电阻和电感背面穿过通孔及其制造方法
公开(公告)号：US07563714B2
公开(公告)日：2009-07-21
申请号：US11275542
申请日：2006-01-13
申请人： Mete Erturk , Robert A. Groves , Jeffrey Bowman Johnson , Alvin Jose Joseph , Qizhi Liu , Edmund Juris Sprogis , Anthony Kendall Stamper
发明人： Mete Erturk , Robert A. Groves , Jeffrey Bowman Johnson , Alvin Jose Joseph , Qizhi Liu , Edmund Juris Sprogis , Anthony Kendall Stamper
IPC分类号： H01L21/44
CPC分类号： H01L21/76898 , H01L23/481 , H01L2924/0002 , H01L2924/00
摘要： A backside contact structure and method of fabricating the structure. The method includes: forming a dielectric isolation in a substrate, the substrate having a frontside and an opposing backside; forming a first dielectric layer on the frontside of the substrate; forming a trench in the first dielectric layer, the trench aligned over and within a perimeter Of the dielectric isolation and extending to the dielectric isolation; extending the trench formed in the first dielectric layer through the dielectric isolation and into the substrate to a depth less than a thickness of the substrate; filling the trench and co-planarizing a top surface of the trench with a top surface of the first dielectric layer to form an electrically conductive through via; and thinning the substrate from a backside of the substrate to expose the through via.
摘要翻译：背面接触结构及其制造方法。该方法包括：在衬底中形成电介质隔离，所述衬底具有前侧和相对的背面; 在所述基板的前侧形成第一电介质层; 在所述第一电介质层中形成沟槽，所述沟槽在所述电介质隔离的周边内并且在所述介质隔离的周边内对准并且延伸到所述电介质隔离; 将形成在第一电介质层中的沟槽通过电介质隔离延伸到衬底中至小于衬底厚度的深度; 填充沟槽并将沟槽的顶表面与第一介电层的顶表面共平面化以形成导电通孔; 并从衬底的背面稀释衬底以露出通孔。

4. 发明申请

US20070190692A1 LOW RESISTANCE AND INDUCTANCE BACKSIDE THROUGH VIAS AND METHODS OF FABRICATING SAME 有权
标题翻译：通过VIAS的低电阻和电感及其制造方法
公开(公告)号：US20070190692A1
公开(公告)日：2007-08-16
申请号：US11275542
申请日：2006-01-13
申请人： Mete Erturk , Robert Groves , Jeffrey Johnson , Alvin Joseph , Qizhi Liu , Edmund Sprogis , Anthony Stamper
发明人： Mete Erturk , Robert Groves , Jeffrey Johnson , Alvin Joseph , Qizhi Liu , Edmund Sprogis , Anthony Stamper
IPC分类号： H01L21/50
CPC分类号： H01L21/76898 , H01L23/481 , H01L2924/0002 , H01L2924/00
摘要： A backside contact structure and method of fabricating the structure. The method includes: forming a dielectric isolation in a substrate, the substrate having a frontside and an opposing backside; forming a first dielectric layer on the frontside of the substrate; forming a trench in the first dielectric layer, the trench aligned over and within a perimeter of the dielectric isolation and extending to the dielectric isolation; extending the trench formed in the first dielectric layer through the dielectric isolation and into the substrate to a depth less than a thickness of the substrate; filling the trench and co-planarizing a top surface of the trench with a top surface of the first dielectric layer to form an electrically conductive through via; and thinning the substrate from a backside of the substrate to expose the through via.
摘要翻译：背面接触结构及其制造方法。该方法包括：在衬底中形成电介质隔离，所述衬底具有前侧和相对的背面; 在所述基板的前侧形成第一电介质层; 在所述第一电介质层中形成沟槽，所述沟槽在所述电介质隔离的周边内并且在所述介电隔离的周边内对准并且延伸到所述电介质隔离; 将形成在第一电介质层中的沟槽通过电介质隔离延伸到衬底中至小于衬底厚度的深度; 填充沟槽并将沟槽的顶表面与第一介电层的顶表面共平面化以形成导电通孔; 并从衬底的背面稀释衬底以露出通孔。

5. 发明授权

US07521327B2 High fT and fmax bipolar transistor and method of making same 失效
标题翻译：高fT和fmax双极晶体管及其制造方法
公开(公告)号：US07521327B2
公开(公告)日：2009-04-21
申请号：US11378927
申请日：2006-03-17
申请人： Alvin Jose Joseph , Qizhi Liu
发明人： Alvin Jose Joseph , Qizhi Liu
IPC分类号： H01L21/331
CPC分类号： H01L29/66287 , H01L21/8249 , H01L27/0623 , H01L29/1004 , H01L29/732
摘要： A high fT and fmax bipolar transistor includes an emitter, a base, and a collector. The emitter has a lower portion and an upper portion that extends beyond the lower portion. The base includes an intrinsic base and an extrinsic base. The intrinsic base is located between the lower portion of the emitter and the collector. The extrinsic base extends from the lower portion of the emitter beyond the upper portion of the emitter and includes a continuous conductor that extends from underneath the upper portion of the emitter and out from underneath the upper portion of the emitter. The continuous conductor provides a low electrical resistance path from a base contact (not shown) to the intrinsic base. The transistor may include a second conductor that does not extend underneath the upper portion of the emitter, but which further reduces the electrical resistance through the extrinsic base.
摘要翻译：高fT和fmax双极晶体管包括发射极，基极和集电极。发射器具有延伸超出下部的下部和上部。基础包括内在基础和外在碱基。本征基极位于发射极的下部和集电极之间。外部基极从发射器的下部延伸超过发射器的上部，并且包括从发射器的上部下方延伸并从发射器的上部下方延伸的连续导体。连续导体提供从底部触点（未示出）到本征基极的低电阻路径。晶体管可以包括不延伸在发射极的上部下方的第二导体，但是通过外部基极进一步降低电阻。

6. 发明授权

US07038298B2 High fT and fmax bipolar transistor and method of making same 有权
标题翻译：高fT和fmax双极晶体管及其制造方法
公开(公告)号：US07038298B2
公开(公告)日：2006-05-02
申请号：US10604045
申请日：2003-06-24
申请人： Alvin Jose Joseph , Qizhi Liu
发明人： Alvin Jose Joseph , Qizhi Liu
IPC分类号： H01L27/082
CPC分类号： H01L29/66287 , H01L21/8249 , H01L27/0623 , H01L29/1004 , H01L29/732
摘要： A high fT and fmax bipolar transistor (100) includes an emitter (104), a base (120), and a collector (116). The emitter has a lower portion (108) and an upper portion (112) that extends beyond the lower portion. The base includes an intrinsic base (14) and an extrinsic base (144). The intrinsic base is located between the lower portion of the emitter and the collector. The extrinsic base extends from the lower portion of the emitter beyond the upper portion of the emitter and includes a continuous conductor (148) that extends from underneath the upper portion of the emitter and out from underneath the upper portion of the emitter. The continuous conductor provides a low electrical resistance path from a base contact (not shown) to the intrinsic base. The transistor may include a second conductor (152) that does not extend underneath the upper portion of the emitter, but which further reduces the electrical resistance through the extrinsic base.
摘要翻译：高电平和高压双极晶体管（100）包括发射极（104），基极（120）和集电极（116）。发射器具有延伸超出下部的下部（108）和上部（112）。基部包括内在基极（14）和外部基极（144）。本征基极位于发射极的下部和集电极之间。外部基极从发射器的下部延伸超过发射器的上部，并且包括从发射器的上部下方延伸并从发射器的上部下方延伸的连续导体（148）。连续导体提供从底部触点（未示出）到本征基极的低电阻路径。晶体管可以包括第二导体（152），其不延伸在发射极的上部下方，但是通过外部基极进一步减小电阻。

7. 发明授权

US06936910B2 BiCMOS technology on SOI substrates 有权
标题翻译： BiCMOS技术在SOI衬底上
公开(公告)号：US06936910B2
公开(公告)日：2005-08-30
申请号：US10708743
申请日：2004-03-23
申请人： John Joseph Ellis-Monaghan , Alvin Jose Joseph , Qizhi Liu , Kirk David Peterson
发明人： John Joseph Ellis-Monaghan , Alvin Jose Joseph , Qizhi Liu , Kirk David Peterson
IPC分类号： H01L21/331 , H01L27/01 , H01L27/06 , H01L27/12 , H01L29/00 , H01L31/0328
CPC分类号： H01L27/1203 , H01L21/76264 , H01L27/0623 , H01L29/0653 , H01L29/66242 , H01L29/66265 , H01L29/7371
摘要： A method and a BICMOS structure are provided. The BiCMOS structure includes an SOI substrate having a bottom Si-containing layer, a buried insulating layer located atop the bottom Si-containing layer, a top Si-containing layer atop the buried insulating layer and a sub-collector which is located in an upper surface of the bottom Si-containing layer. The sub-collector is in contact with a bottom surface of the buried insulating layer. The structure also includes an extrinsic base heterojunction bipolar transistor located in an opening provided in a bipolar device area of the SOI substrate in which a base region of the bipolar transistor is located directly atop the sub-collector
摘要翻译：提供了一种方法和BICMOS结构。 BiCMOS结构包括具有底部含Si层的SOI衬底，位于底部含Si层顶部的掩埋绝缘层，位于掩埋绝缘层顶部的含Si层，以及位于上层的子集电极底层含Si层的表面。副集电体与埋层绝缘层的底面接触。该结构还包括位于SOI衬底的双极器件区域中的开口中的外部基极异质结双极晶体管，其中双极晶体管的基极区域直接位于子集电极的顶部

8. 发明授权

US08415763B2 Tunable semiconductor device 有权
标题翻译：可调谐半导体器件
公开(公告)号：US08415763B2
公开(公告)日：2013-04-09
申请号：US13076781
申请日：2011-03-31
申请人： David Louis Harame , Alvin Jose Joseph , Qizhi Liu , Ramana Murty Malladi
发明人： David Louis Harame , Alvin Jose Joseph , Qizhi Liu , Ramana Murty Malladi
IPC分类号： H01L29/66
CPC分类号： H01L29/73 , H01L29/0821 , H01L29/66272 , H01L29/732
摘要： Embodiments of the invention include a method for forming a tunable semiconductor device and the resulting structure. The invention comprises forming a semiconductor substrate. Next, pattern a first mask over the semiconductor substrate. Dope regions of the semiconductor substrate not protected by the first mask to form a first discontinuous subcollector. Remove the first mask. Pattern a second mask over the semiconductor substrate. Dope regions of the semiconductor substrate not protected by the second mask and on top of the first discontinuous subcollector to form a second discontinuous subcollector. Remove the second mask and form a collector above the second discontinuous subcollector. Breakdown voltage of the device may be tuned by varying the gaps separating doped regions within the first and second discontinuous subcollectors. Doped regions of the first and second discontinuous subcollectors may be formed in a mesh pattern.
摘要翻译：本发明的实施例包括形成可调谐半导体器件的方法和所得到的结构。本发明包括形成半导体衬底。接下来，在半导体衬底上形成第一掩模。半导体衬底的掺杂区域不被第一掩模保护以形成第一不连续子集电极。删除第一个面具。在半导体衬底上形成第二掩模。半导体衬底的掺杂区域不被第二掩模保护，并且在第一不连续子集电极的顶部上形成第二不连续子集电极。取下第二个掩模，并在第二个不连续的子集电极上形成集电极。可以通过改变分离第一和第二不连续子集电极内的掺杂区域的间隙来调谐器件的击穿电压。可以以网格图案形成第一和第二不连续子集电极的掺杂区域。

9. 发明申请

US20120248573A1 TUNABLE SEMICONDUCTOR DEVICE 有权
标题翻译：可控半导体器件
公开(公告)号：US20120248573A1
公开(公告)日：2012-10-04
申请号：US13076781
申请日：2011-03-31
申请人： David Louis Harame , Alvin Jose Joseph , Qizhi Liu , Ramana Murty Malladi
发明人： David Louis Harame , Alvin Jose Joseph , Qizhi Liu , Ramana Murty Malladi
IPC分类号： H01L29/70
CPC分类号： H01L29/73 , H01L29/0821 , H01L29/66272 , H01L29/732
摘要： Embodiments of the invention include a method for forming a tunable semiconductor device and the resulting structure. The invention comprises forming a semiconductor substrate. Next, pattern a first mask over the semiconductor substrate. Dope regions of the semiconductor substrate not protected by the first mask to form a first discontinuous subcollector. Remove the first mask. Pattern a second mask over the semiconductor substrate. Dope regions of the semiconductor substrate not protected by the second mask and on top of the first discontinuous subcollector to form a second discontinuous subcollector. Remove the second mask and form a collector above the second discontinuous subcollector. Breakdown voltage of the device may be tuned by varying the gaps separating doped regions within the first and second discontinuous subcollectors. Doped regions of the first and second discontinuous subcollectors may be formed in a mesh pattern.
摘要翻译：本发明的实施例包括形成可调谐半导体器件的方法和所得到的结构。本发明包括形成半导体衬底。接下来，在半导体衬底上形成第一掩模。半导体衬底的掺杂区域不被第一掩模保护以形成第一不连续子集电极。删除第一个面具。在半导体衬底上形成第二掩模。半导体衬底的掺杂区域不被第二掩模保护，并且在第一不连续子集电极的顶部上形成第二不连续子集电极。取下第二个掩模，并在第二个不连续的子集电极上形成集电极。可以通过改变分离第一和第二不连续子集电极内的掺杂区域的间隙来调谐器件的击穿电压。可以以网格图案形成第一和第二不连续子集电极的掺杂区域。

10. 发明授权

US09053939B2 Heterojunction bipolar transistor with epitaxial emitter stack to improve vertical scaling 有权
标题翻译：具有外延发射极堆叠的异质结双极晶体管，以改善垂直刻度
公开(公告)号：US09053939B2
公开(公告)日：2015-06-09
申请号：US13303248
申请日：2011-11-23
申请人： Thomas N. Adam , David L. Harame , Qizhi Liu , Alexander Reznicek
发明人： Thomas N. Adam , David L. Harame , Qizhi Liu , Alexander Reznicek
IPC分类号： H01L29/737 , H01L21/02 , H01L29/66 , H01L29/08 , H01L29/417 , H01L29/10
CPC分类号： H01L21/0262 , H01L21/02381 , H01L21/02439 , H01L21/02447 , H01L21/0245 , H01L21/02521 , H01L21/02529 , H01L21/02532 , H01L21/02576 , H01L21/02579 , H01L29/0817 , H01L29/1004 , H01L29/41708 , H01L29/66242 , H01L29/7371
摘要： A heterojunction bipolar transistor (HBT) may include an n-type doped crystalline collector formed in an upper portion of a crystalline silicon substrate layer; a p-type doped crystalline p+Si1-xGex layer, formed above the n-type doped collector, that forms a p-type doped internal base of the HBT; a crystalline silicon cap formed on the p-type doped crystalline p+Si1-xGex layer, in which the crystalline silicon cap includes an n-type impurity and forms an n-type doped emitter of the HBT; and an n-type doped crystalline silicon emitter stack formed within an opening through an insulating layer to an upper surface of the crystalline silicon cap.
摘要翻译：异质结双极晶体管（HBT）可以包括在晶体硅衬底层的上部形成的n型掺杂晶体集电极; 形成在n型掺杂集电极上方的p型掺杂晶体p + Si1-xGex层，其形成HBT的p型掺杂内部基极; 形成在p型掺杂结晶p + Si1-xGex层上的晶体硅帽，其中晶体硅帽包括n型杂质并形成HBT的n型掺杂发射极; 以及形成在通过绝缘层的开口内的晶体硅帽的上表面的n型掺杂晶体硅发射极堆叠。

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