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1. 发明授权

US06259148B1 Modular high frequency integrated circuit structure 失效
标题翻译：模块化高频集成电路结构
公开(公告)号：US06259148B1
公开(公告)日：2001-07-10
申请号：US09330614
申请日：1999-06-11
申请人： Thomas Adam Bartush , David Louis Harame , John Chester Malinowski , Dawn Tudryn Piciacchio , Christopher Lee Tessler , Richard Paul Volant
发明人： Thomas Adam Bartush , David Louis Harame , John Chester Malinowski , Dawn Tudryn Piciacchio , Christopher Lee Tessler , Richard Paul Volant
IPC分类号： H01L2348
CPC分类号： H01L21/76804 , H01L23/5329 , H01L23/66 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： Disclosed is a manufacturable silicon-based modular integrated circuit structure having performance characteristics comparable to high frequency GaAs-based integrated circuit structures, comprising materials and made in process steps which are compatible with existing low cost silicon-based integrated circuit processing.
摘要翻译：公开了一种可制造的基于硅的模块化集成电路结构，其具有与高频GaAs基集成电路结构相当的性能特征，其包括与现有的低成本硅基集成电路处理兼容的材料和制造工艺步骤。

2. 发明授权

US5926359A Metal-insulator-metal capacitor 失效
公开(公告)号：US5926359A
公开(公告)日：1999-07-20
申请号：US626310
申请日：1996-04-01
申请人： Nancy Anne Greco , David Louis Harame , Gary Robert Hueckel , Joseph Thomas Kocis , Dominique Nguyen Ngoc , Kenneth Jay Stein
发明人： Nancy Anne Greco , David Louis Harame , Gary Robert Hueckel , Joseph Thomas Kocis , Dominique Nguyen Ngoc , Kenneth Jay Stein
IPC分类号： H01L27/04 , H01L21/02 , H01L21/768 , H01L21/822 , H01L23/522 , H01G4/06
CPC分类号： H01L23/5223 , H01L28/40 , H01L2924/0002
摘要： An interconnection wiring system incorporating two levels of interconnection wiring separated by a first dielectric, a capacitor formed by a second dielectric, a bottom electrode of the lower interconnection wiring or a via and a top electrode of the upper interconnection wiring or a separate metal layer. The invention overcomes the problem of leakage current and of substrate stray capacitance by positioning the capacitor between two levels of interconnection wiring.

3. 发明授权

US08415763B2 Tunable semiconductor device 有权
标题翻译：可调谐半导体器件
公开(公告)号：US08415763B2
公开(公告)日：2013-04-09
申请号：US13076781
申请日：2011-03-31
申请人： David Louis Harame , Alvin Jose Joseph , Qizhi Liu , Ramana Murty Malladi
发明人： David Louis Harame , Alvin Jose Joseph , Qizhi Liu , Ramana Murty Malladi
IPC分类号： H01L29/66
CPC分类号： H01L29/73 , H01L29/0821 , H01L29/66272 , H01L29/732
摘要： Embodiments of the invention include a method for forming a tunable semiconductor device and the resulting structure. The invention comprises forming a semiconductor substrate. Next, pattern a first mask over the semiconductor substrate. Dope regions of the semiconductor substrate not protected by the first mask to form a first discontinuous subcollector. Remove the first mask. Pattern a second mask over the semiconductor substrate. Dope regions of the semiconductor substrate not protected by the second mask and on top of the first discontinuous subcollector to form a second discontinuous subcollector. Remove the second mask and form a collector above the second discontinuous subcollector. Breakdown voltage of the device may be tuned by varying the gaps separating doped regions within the first and second discontinuous subcollectors. Doped regions of the first and second discontinuous subcollectors may be formed in a mesh pattern.
摘要翻译：本发明的实施例包括形成可调谐半导体器件的方法和所得到的结构。本发明包括形成半导体衬底。接下来，在半导体衬底上形成第一掩模。半导体衬底的掺杂区域不被第一掩模保护以形成第一不连续子集电极。删除第一个面具。在半导体衬底上形成第二掩模。半导体衬底的掺杂区域不被第二掩模保护，并且在第一不连续子集电极的顶部上形成第二不连续子集电极。取下第二个掩模，并在第二个不连续的子集电极上形成集电极。可以通过改变分离第一和第二不连续子集电极内的掺杂区域的间隙来调谐器件的击穿电压。可以以网格图案形成第一和第二不连续子集电极的掺杂区域。

4. 发明申请

US20120248573A1 TUNABLE SEMICONDUCTOR DEVICE 有权
标题翻译：可控半导体器件
公开(公告)号：US20120248573A1
公开(公告)日：2012-10-04
申请号：US13076781
申请日：2011-03-31
申请人： David Louis Harame , Alvin Jose Joseph , Qizhi Liu , Ramana Murty Malladi
发明人： David Louis Harame , Alvin Jose Joseph , Qizhi Liu , Ramana Murty Malladi
IPC分类号： H01L29/70
CPC分类号： H01L29/73 , H01L29/0821 , H01L29/66272 , H01L29/732
摘要： Embodiments of the invention include a method for forming a tunable semiconductor device and the resulting structure. The invention comprises forming a semiconductor substrate. Next, pattern a first mask over the semiconductor substrate. Dope regions of the semiconductor substrate not protected by the first mask to form a first discontinuous subcollector. Remove the first mask. Pattern a second mask over the semiconductor substrate. Dope regions of the semiconductor substrate not protected by the second mask and on top of the first discontinuous subcollector to form a second discontinuous subcollector. Remove the second mask and form a collector above the second discontinuous subcollector. Breakdown voltage of the device may be tuned by varying the gaps separating doped regions within the first and second discontinuous subcollectors. Doped regions of the first and second discontinuous subcollectors may be formed in a mesh pattern.
摘要翻译：本发明的实施例包括形成可调谐半导体器件的方法和所得到的结构。本发明包括形成半导体衬底。接下来，在半导体衬底上形成第一掩模。半导体衬底的掺杂区域不被第一掩模保护以形成第一不连续子集电极。删除第一个面具。在半导体衬底上形成第二掩模。半导体衬底的掺杂区域不被第二掩模保护，并且在第一不连续子集电极的顶部上形成第二不连续子集电极。取下第二个掩模，并在第二个不连续的子集电极上形成集电极。可以通过改变分离第一和第二不连续子集电极内的掺杂区域的间隙来调谐器件的击穿电压。可以以网格图案形成第一和第二不连续子集电极的掺杂区域。

5. 发明授权

US06635527B1 Metal-insulator-metal capacitor 有权
标题翻译：金属绝缘体金属电容器
公开(公告)号：US06635527B1
公开(公告)日：2003-10-21
申请号：US09318867
申请日：1999-05-26
申请人： Nancy Anne Greco , David Louis Harame , Gary Robert Hueckel , Joseph Thomas Kocis , Dominique Nguyen Ngoc , Kenneth Jay Stein
发明人： Nancy Anne Greco , David Louis Harame , Gary Robert Hueckel , Joseph Thomas Kocis , Dominique Nguyen Ngoc , Kenneth Jay Stein
IPC分类号： H01L218242
CPC分类号： H01L23/5223 , H01L28/40 , H01L2924/0002 , H01L2924/00
摘要： An interconnection wiring system incorporating two levels of interconnection wiring separated by a first dielectric, a capacitor formed by a second dielectric, a bottom electrode of the lower interconnection wiring or a via and a top electrode of the upper interconnection wiring or a separate metal layer. The invention overcomes the problem of leakage current and of substrate stray capacitance by positioning the capacitor between two levels of interconnection wiring.
摘要翻译：一种互连布线系统，包括由第一介质隔离的两层互连布线，由第二介质形成的电容器，下互连布线的底电极或通孔，以及上互连布线的顶电极或单独的金属层。本发明通过将电容器放置在两层互连布线之间来克服漏电流和衬底杂散电容的问题。

6. 发明授权

US06927440B2 Metal-insulator-metal capacitor 失效
公开(公告)号：US06927440B2
公开(公告)日：2005-08-09
申请号：US10658036
申请日：2003-09-09
申请人： Nancy Anne Greco , David Louis Harame , Gary Robert Hueckel , Joseph Thomas Kocis , Dominique Nguyen Ngoc , Kenneth Jay Stein
发明人： Nancy Anne Greco , David Louis Harame , Gary Robert Hueckel , Joseph Thomas Kocis , Dominique Nguyen Ngoc , Kenneth Jay Stein
IPC分类号： H01L27/04 , H01L21/02 , H01L21/768 , H01L21/822 , H01L23/522 , H01L27/108 , H01L29/41
CPC分类号： H01L23/5223 , H01L28/40 , H01L2924/0002 , H01L2924/00
摘要： An interconnection wiring system incorporating two levels of interconnection wiring separated by a first dielectric, a capacitor formed by a second dielectric, a bottom electrode of the lower interconnection wiring or a via and a top electrode of the upper interconnection wiring or a separate metal layer. The invention overcomes the problem of leakage current and of substrate stray capacitance by positioning the capacitor between two levels of interconnection wiring.

7. 发明授权

US06413868B1 Modular high frequency integrated circuit structure 失效
标题翻译：模块化高频集成电路结构
公开(公告)号：US06413868B1
公开(公告)日：2002-07-02
申请号：US09735309
申请日：2001-01-04
申请人： Thomas Adam Bartush , David Louis Harame , John Chester Malinowski , Dawn Tudryn Piciacchio , Christopher Lee Tessler , Richard Paul Volant
发明人： Thomas Adam Bartush , David Louis Harame , John Chester Malinowski , Dawn Tudryn Piciacchio , Christopher Lee Tessler , Richard Paul Volant
IPC分类号： H01L2100
CPC分类号： H01L21/76804 , H01L23/5329 , H01L23/66 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： Disclosed is a manufacturable silicon-based modular integrated circuit structure having performance characteristics comparable to high frequency GaAs-based integrated circuit structures, comprising materials and made in process steps which are compatible with existing low cost silicon-based integrated circuit processing.
摘要翻译：公开了一种可制造的基于硅的模块化集成电路结构，其具有与高频GaAs基集成电路结构相当的性能特征，其包括与现有的低成本硅基集成电路处理兼容的材料并且制造在工艺步骤中。

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