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1. 发明授权

US06754879B1 Method and apparatus for providing modularity to a behavioral description of a circuit design 失效
标题翻译：用于向电路设计的行为描述提供模块化的方法和装置
公开(公告)号：US06754879B1
公开(公告)日：2004-06-22
申请号：US08789702
申请日：1997-01-27
申请人： Merwin H. Alferness , Mark D. Aubel , Frederick H. Hathaway
发明人： Merwin H. Alferness , Mark D. Aubel , Frederick H. Hathaway
IPC分类号： G06F1750
CPC分类号： G06F17/5045 , G06F17/5072
摘要： A method and apparatus for selectively providing modularity and/or hierarchy to a behavioral description of a circuit design. This is accomplished by providing a template call in the behavioral description of the circuit design. The template call provides a reference to a corresponding template behavioral description. The behavioral description of the circuit design is expanded using an expander preprocessor, wherein a command line switch is used to selectively provide modularity and/or hierarchy to the resulting behavioral description.
摘要翻译：一种用于选择性地向电路设计的行为描述提供模块化和/或层级的方法和装置。这通过在电路设计的行为描述中提供模板调用来实现。模板调用提供了对相应模板行为描述的引用。使用扩展器预处理器来扩展电路设计的行为描述，其中使用命令行开关来选择性地向结果行为描述提供模块化和/或层次结构。

2. 发明授权

US06684376B1 Method and apparatus for selecting components within a circuit design database 失效
标题翻译：用于在电路设计数据库中选择组件的方法和装置
公开(公告)号：US06684376B1
公开(公告)日：2004-01-27
申请号：US08789026
申请日：1997-01-27
申请人： Joseph P. Kerzman , James E. Rezek , Mark D. Aubel , Merwin H. Alferness
发明人： Joseph P. Kerzman , James E. Rezek , Mark D. Aubel , Merwin H. Alferness
IPC分类号： G06F1750
CPC分类号： G06F17/5072
摘要： A method and apparatus for efficiently selecting cells within a circuit design database. The invention includes four primary features for selecting cells including (1) selecting only those cells that are in a pre-identified region and within a pre-identified selection area; (2) maneuvering through the circuit design hierarchy and selecting cells or regions at selected levels of hierarchy by using predetermined up and down hot-keys; (3) sorting selected cells by instance name, and manually selecting a desired cell or region from the resulting sorted list; and (4) sorting selected cells by a corresponding net name, and manually selecting a desired cell or region from the resulting sorted list.
摘要翻译：一种用于有效地选择电路设计数据库内的单元的方法和装置。本发明包括用于选择单元的四个主要特征，包括：（1）仅选择在预先识别的区域内和预先识别的选择区域内的那些单元; （2）通过电路设计层次来操纵，并通过使用预定的上下热键选择所选层级的单元或区域; （3）按实例名称对所选择的单元进行排序，并从所得到的排序列表中手动选择所需单元格或区域; 和（4）通过相应的网络名称对所选择的单元格进行排序，并从所得到的排序列表中手动选择所需的单元格或区域。

3. 发明授权

US6029205A System architecture for improved message passing and process synchronization between concurrently executing processes 失效
标题翻译：用于改进同时执行的进程之间的消息传递和进程同步的系统架构
公开(公告)号：US6029205A
公开(公告)日：2000-02-22
申请号：US800344
申请日：1997-02-14
申请人： Merwin H. Alferness , Mark D. Aubel , Charles R. Caldarale , James W. Douglas , David C. Johnson , David R. Johnson , Joseph P. Kerzman , James R. McBreen , Hans C. Mikkelsen , Donna J. Plunkett , Richard M. Shelton , Francis A. Stephens , Wayne D. Ward
发明人： Merwin H. Alferness , Mark D. Aubel , Charles R. Caldarale , James W. Douglas , David C. Johnson , David R. Johnson , Joseph P. Kerzman , James R. McBreen , Hans C. Mikkelsen , Donna J. Plunkett , Richard M. Shelton , Francis A. Stephens , Wayne D. Ward
IPC分类号： G06F9/46 , G06F15/163
CPC分类号： G06F9/546
摘要： A system and method for interprocess communication between concurrently executing, cooperating sequential processes in a digital computer system uses a shared memory queue as a mechanism for message passing and process synchronization. Data to be transferred from a sending process to a receiving process is stored in a queue entry which is visible in the virtual address space of the first process. The queue entry is added to a queue by the sending process directing the processor to execute an enqueue instruction. The receiving process removes the queue entry from the queue by directing the processor to execute a dequeue instruction. The receiving process then has direct access and visibility to the contents of the queue entry without having to copy the data into its virtual address space. Instead of sending data in a queue entry, a sending process may send an event indicator and no data. The receiving process may then wait on an empty queue until an event notification is received in a queue entry enqueued to the queue. Protection is provided by the system to prevent unauthorized access to the queue by other processes active in the system.
摘要翻译：用于数字计算机系统中的并行执行，协作顺序处理之间的进程间通信的系统和方法使用共享存储器队列作为消息传递和过程同步的机制。要从发送进程传送到接收进程的数据存储在第一进程的虚拟地址空间中可见的队列条目中。发送进程将队列条目添加到队列中，该进程指示处理器执行入队指令。接收进程通过指示处理器执行出队指令来从队列中移除队列条目。然后，接收过程对队列条目的内容具有直接访问和可见性，而不必将数据复制到其虚拟地址空间中。发送进程可以发送一个事件指示符而不是数据，而不是在队列条目中发送数据。然后，接收进程可以等待一个空队列，直到在排入队列的队列中接收到一个事件通知。系统提供保护，以防止系统中其他进程未经授权的访问队列。

4. 发明授权

US5701316A Method for generating an internet protocol suite checksum in a single macro instruction 失效
标题翻译：在单个宏指令中生成互联网协议套件校验和的方法
公开(公告)号：US5701316A
公开(公告)日：1997-12-23
申请号：US521695
申请日：1995-08-31
申请人： Merwin H. Alferness , Peter Bradley Criswell , David Randal Johnson , James R. McBreen
发明人： Merwin H. Alferness , Peter Bradley Criswell , David Randal Johnson , James R. McBreen
IPC分类号： G06F11/10 , H04L1/00 , H04L29/06 , H04L29/08
CPC分类号： H04L1/0057 , G06F11/10 , H04L29/06 , H04L69/12 , H04L69/324
摘要： An Internet checksum for use by TCP/IP is generated in a single macro-instruction called a Block Add Octets instruction. Extraneous overhead of macro-instruction looping and bit masking is eliminated by combining checksum operations into a single macro-instruction using a block add approach. The programmer specifies the address in memory and the number of double-words of message data to be added together within a single instance of the Block Add Octets instruction so that looping and jump/branch instructions are not needed. The Block Add Octets instruction fetches all octets (8-bit data segments) contained in full double words from memory and adds them into the checksum. The method handles partial double words of data, full double words, and odd numbers of double words, whereby a double word consists of four octets. The checksum is calculated using one's complement arithmetic rather than two's complement, thereby increasing the speed of checksum calculation because the "end around carry" is eliminated. The number of octets that can be added to the checksum per processor cycle is greatly increased, thereby significantly improving overall TCP/IP performance.
摘要翻译：在一个名为Block Add Octets指令的宏指令中生成TCP / IP使用的Internet校验和。通过使用块添加方法将校验和操作组合到单个宏指令中，消除了宏指令循环和位掩码的外部开销。程序员在Block Add Octets指令的单个实例中指定内存中的地址和要添加在一起的消息数据的双字数，以便不需要循环和跳转/分支指令。块添加八位字节指令从内存中获取包含在全双字中的所有八位字节（8位数据段），并将它们添加到校验和中。该方法处理部分双字数据，全双字和奇数双字，由此双字由四个字节组成。使用补码算术而不是二进制补码来计算校验和，从而增加校验和计算的速度，因为“结束执行”被消除。每个处理器周期可以添加到校验和的八位字节数量大大增加，从而显着提高整体TCP / IP性能。

5. 发明授权

US5555396A Hierarchical queuing in a system architecture for improved message passing and process synchronization 失效
标题翻译：在系统架构中进行分层排队，以改进消息传递和进程同步
公开(公告)号：US5555396A
公开(公告)日：1996-09-10
申请号：US362034
申请日：1994-12-22
申请人： Merwin H. Alferness , Charles R. Caldarale , David R. Johnson , Joseph P. Kerzman , James R. McBreen
发明人： Merwin H. Alferness , Charles R. Caldarale , David R. Johnson , Joseph P. Kerzman , James R. McBreen
IPC分类号： G06F9/46 , G06F12/00 , G06F12/08
CPC分类号： G06F9/546
摘要： A system and method for interprocess communication between concurrently executing, cooperating sequential processes in a digital computer system uses a shared memory queue as a mechanism for message passing and process synchronization. Data to be transferred from a sending process to a receiving process is stored in a queue entry on the shared memory queue. Hierarchical queuing allows a sending process to collect multiple message segments as entries in a local sub-queue, which is enqueued as a single entity to the shared memory queue when all message segments are present. The receiving process dequeues the sub-queue in one operation, thereby increasing the efficiency of message transfer while preventing the erroneous dequeuing of message segments when multiple receiving processes are waiting on the same shared memory queue. In this manner, the logical maximum size of a message being passed between processes is expanded.
摘要翻译：用于数字计算机系统中的并行执行，协作顺序处理之间的进程间通信的系统和方法使用共享存储器队列作为消息传递和过程同步的机制。要从发送进程转移到接收进程的数据存储在共享内存队列中的队列条目中。分层排队允许发送过程收集多个消息段作为本地子队列中的条目，当存在所有消息段时，本地子队列作为单个实体入队到共享存储器队列。接收处理在一个操作中出现子队列，从而提高消息传输的效率，同时防止当多个接收进程在相同的共享存储器队列上等待时消息段的错误出队。以这种方式，扩展了在进程之间传递的消息的逻辑最大大小。

6. 发明授权

US5379392A Method of and apparatus for rapidly loading addressing registers 失效
标题翻译：快速加载寻址寄存器的方法和装置
公开(公告)号：US5379392A
公开(公告)日：1995-01-03
申请号：US809386
申请日：1991-12-17
申请人： Merwin H. Alferness , John Z. Nguyen
发明人： Merwin H. Alferness , John Z. Nguyen
IPC分类号： G06F12/02 , G06F12/06 , G06F9/35
CPC分类号： G06F12/0284
摘要： An apparatus for and method of loading the user addressing base register of a large scale multiprogrammed instruction processor. The base register is normally loaded to permit a user application program to access a different data segment. Providing a base register addressing environment for user application programs permits the software to be developed using virtual addressing. The addressing environment is specified by a stack of base registers. These are loaded from a data store specifying a virtual address for each data segment. During the loading process, an absolute address corresponding to the virtual address is loaded into each base register. To load a base register, a determination is made whether the future value differs from the previous value by a differential offset. If yes, the base register is loaded with an absolute address corresponding to the sum of the previous bank descriptor and the new offset. If no, the new base register value is computed by accessing a bank description table.
摘要翻译：一种用于加载大规模多编程指令处理器的用户寻址基址寄存器的装置和方法。基本寄存器通常被加载以允许用户应用程序访问不同的数据段。为用户应用程序提供基址寄存器寻址环境允许使用虚拟寻址来开发软件。寻址环境由一组基址寄存器指定。这些从数据存储器加载，指定每个数据段的虚拟地址。在加载过程中，将与虚拟地址对应的绝对地址加载到每个基址寄存器中。要加载基址寄存器，确定未来值是否与先前值差异偏移。如果是，基址寄存器将加载与前一个存储区描述符和新偏移量之和相对应的绝对地址。如果否，则通过访问存储区描述表来计算新的基址寄存器值。

7. 发明授权

US08769164B2 Methods and apparatus for allocating bandwidth for a network processor 有权
标题翻译：为网络处理器分配带宽的方法和装置
公开(公告)号：US08769164B2
公开(公告)日：2014-07-01
申请号：US10667029
申请日：2003-09-18
申请人： Merwin H. Alferness , William J. Goetzinger , Kent H. Haselhorst , Lonny Lambrecht , Joshua W. Rensch
发明人： Merwin H. Alferness , William J. Goetzinger , Kent H. Haselhorst , Lonny Lambrecht , Joshua W. Rensch
IPC分类号： G06F13/00 , G06F3/00
CPC分类号： H04L47/522 , H04L47/50 , H04L49/90
摘要： In a first aspect, a first method is provided for self-adjusting allocation of memory bandwidth in a network processor system. The first method includes the steps of (1) determining an amount of memory bandwidth of a network processor used by each of a plurality of data types; and (2) dynamically adjusting the amount of memory bandwidth allocated to at least one of the plurality of data types based on the determination. Numerous other aspects are provided.
摘要翻译：在第一方面，提供了一种用于在网络处理器系统中自调整存储器带宽分配的方法。第一种方法包括以下步骤：（1）确定由多种数据类型中的每一种使用的网络处理器的存储器带宽量; 以及（2）基于所述确定动态地调整分配给所述多个数据类型中的至少一个的存储器带宽的量。提供了许多其他方面。

8. 发明授权

US5602998A Dequeue instruction in a system architecture for improved message passing and process synchronization 失效
标题翻译：系统架构中的出队指令，用于改进消息传递和进程同步
公开(公告)号：US5602998A
公开(公告)日：1997-02-11
申请号：US362638
申请日：1994-12-22
申请人： Merwin H. Alferness , Charles R. Caldarale , David C. Johnson , David R. Johnson , James R. McBreen , Wayne D. Ward
发明人： Merwin H. Alferness , Charles R. Caldarale , David C. Johnson , David R. Johnson , James R. McBreen , Wayne D. Ward
IPC分类号： G06F9/46
CPC分类号： G06F9/544 , G06F9/546
摘要： A system and method for removing a queue entry containing message data from a queue shared by communicating, sequential processes includes dequeue (DEQ) and dequeue or wait (DEQW) instructions. The dequeue instruction removes a queue entry from the head of the shared queue, thereby providing access to the message data contained in the queue entry to the dequeuing process. The dequeue or wait instruction removes a queue entry from the shared queue if there is one, otherwise it suspends the execution of the dequeuing process until an entry is enqueued to the queue. If an event is selected by the dequeuing process, the dequeuing process is suspended until notification of the event is detected in the shared queue. Execution of the dequeue and dequeue or wait instructions include blocking access to the queue by other processes, updating queue linkages, deactivating processes waiting on entries or events being made to the queue, monitoring interrupts, and validating the appropriate queue data structures.
摘要翻译：用于从通过通信的顺序进程共享的队列中去除包含消息数据的队列条目的系统和方法包括出队（DEQ）和出队或等待（DEQW）指令。出队指令从共享队列的头部移除队列条目，从而提供对包含在队列进入出队进程的消息数据的访问。如果有一个，出队或等待指令将从共享队列中移除一个队列条目，否则将暂停执行出队进程，直到一个条目排入队列。如果由出队进程选择了一个事件，则在共享队列中检测到事件的通知之前暂停出队进程。执行出队和出队或等待指令包括阻止其他进程对队列的访问，更新队列链接，停用等待队列进入的进程，监视中断和验证适当的队列数据结构。

9. 发明授权

US5363490A Apparatus for and method of conditionally aborting an instruction within a pipelined architecture 失效
标题翻译：用于有条件地中止流水线架构内的指令的装置和方法
公开(公告)号：US5363490A
公开(公告)日：1994-11-08
申请号：US829697
申请日：1992-02-03
申请人： Merwin H. Alferness , Eric Collins
发明人： Merwin H. Alferness , Eric Collins
IPC分类号： G06F9/28 , G06F9/38
CPC分类号： G06F9/28 , G06F9/3842
摘要： An apparatus for and method of aborting the remainder of a microinstruction if a branch by that microinstruction or a subsequent microinstruction renders the results of said microinstruction to be invalid. Within an instruction processor having the capability for pipelined operation, the sensitivity of an operation of a microinstruction to the branch condition may be indicated by one or more abort bits. If an abort bit is set and the corresponding branch condition occurs, the remainder of the microinstruction is aborted. By thus indicating the sensitivity to a branch, the microinstruction can proceed under full pipeline operation until such time as a branch condition actually occurs.
摘要翻译：如果通过该微指令或随后的微指令的分支使得所述微指令的结果无效，则终止微指令的其余部分的装置和方法。在具有流水线操作能力的指令处理器中，微指令对分支状态的操作的灵敏度可以由一个或多个中止位指示。如果设置中止位并发生相应的分支条件，则微指令的其余部分将中止。通过这样指示对分支的灵敏度，微指令可以在完全流水线运行之前进行，直到分支状态实际发生。

10. 发明授权

US5611065A Address prediction for relative-to-absolute addressing 失效
标题翻译：相对绝对寻址的地址预测
公开(公告)号：US5611065A
公开(公告)日：1997-03-11
申请号：US306085
申请日：1994-09-14
申请人： Merwin H. Alferness , Joseph P. Kerzman , John Z. Nguyen
发明人： Merwin H. Alferness , Joseph P. Kerzman , John Z. Nguyen
IPC分类号： G06F9/355 , G06F9/38 , G06F12/00 , G06F9/26 , G06F9/34 , G06F12/02
CPC分类号： G06F9/342 , G06F9/383 , G06F9/3832
摘要： A base address prediction system for predicting one of a plurality of base addresses to be added to a known relative address in order to generate an absolute address. An actual base address determined from the relative address is also generated. The actual base address determination takes longer to generate than the predicted base address determination, and therefore the predicted base address is used to select a base address as long as the prediction is correct. Circuitry exists to compare the predicted base address with the actual base address, and if not equal, the predicted base address will be nullified, and the actual base address will be used. Prediction modes are dependent on whether the relative address indicates an instruction fetch or an operand fetch. Where the relative address indicates an instruction fetch, the prediction will be based on the last base address used, on the assumption that instructions will be contiguous in a single block of memory. Where the relative address indicates an operand fetch, the prediction will only change upon the occurrence of two consecutive incorrect predictions, and the actual base address will be used during incorrect prediction periods. Staged latching circuitry and comparison circuitry provides a method of determining whether two consecutive predictions were incorrect.
摘要翻译：一种基地址预测系统，用于预测要添加到已知相对地址的多个基地址之一以产生绝对地址。也会生成从相对地址确定的实际基址。实际的基地址确定比预测的基地址确定需要更长的时间，因此只要预测是正确的，就使用预测的基地址来选择基地址。存在电路以将预测的基地址与实际基地址进行比较，如果不相等，则预测的基地址将被取消，并且将使用实际的基地址。预测模式取决于相对地址是指示提取还是操作数提取。在相对地址指示取指的地方，预测将基于所使用的最后基地址，假设指令在单个存储器块中是连续的。在相对地址指示操作数提取的情况下，预测将仅在两次连续不正确预测的发生时发生变化，并且在不正确的预测期间将使用实际基地址。分段闭锁电路和比较电路提供了一种确定两个连续预测是否不正确的方法。

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