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1. 发明授权

US6029205A System architecture for improved message passing and process synchronization between concurrently executing processes 失效
标题翻译：用于改进同时执行的进程之间的消息传递和进程同步的系统架构
公开(公告)号：US6029205A
公开(公告)日：2000-02-22
申请号：US800344
申请日：1997-02-14
申请人： Merwin H. Alferness , Mark D. Aubel , Charles R. Caldarale , James W. Douglas , David C. Johnson , David R. Johnson , Joseph P. Kerzman , James R. McBreen , Hans C. Mikkelsen , Donna J. Plunkett , Richard M. Shelton , Francis A. Stephens , Wayne D. Ward
发明人： Merwin H. Alferness , Mark D. Aubel , Charles R. Caldarale , James W. Douglas , David C. Johnson , David R. Johnson , Joseph P. Kerzman , James R. McBreen , Hans C. Mikkelsen , Donna J. Plunkett , Richard M. Shelton , Francis A. Stephens , Wayne D. Ward
IPC分类号： G06F9/46 , G06F15/163
CPC分类号： G06F9/546
摘要： A system and method for interprocess communication between concurrently executing, cooperating sequential processes in a digital computer system uses a shared memory queue as a mechanism for message passing and process synchronization. Data to be transferred from a sending process to a receiving process is stored in a queue entry which is visible in the virtual address space of the first process. The queue entry is added to a queue by the sending process directing the processor to execute an enqueue instruction. The receiving process removes the queue entry from the queue by directing the processor to execute a dequeue instruction. The receiving process then has direct access and visibility to the contents of the queue entry without having to copy the data into its virtual address space. Instead of sending data in a queue entry, a sending process may send an event indicator and no data. The receiving process may then wait on an empty queue until an event notification is received in a queue entry enqueued to the queue. Protection is provided by the system to prevent unauthorized access to the queue by other processes active in the system.
摘要翻译：用于数字计算机系统中的并行执行，协作顺序处理之间的进程间通信的系统和方法使用共享存储器队列作为消息传递和过程同步的机制。要从发送进程传送到接收进程的数据存储在第一进程的虚拟地址空间中可见的队列条目中。发送进程将队列条目添加到队列中，该进程指示处理器执行入队指令。接收进程通过指示处理器执行出队指令来从队列中移除队列条目。然后，接收过程对队列条目的内容具有直接访问和可见性，而不必将数据复制到其虚拟地址空间中。发送进程可以发送一个事件指示符而不是数据，而不是在队列条目中发送数据。然后，接收进程可以等待一个空队列，直到在排入队列的队列中接收到一个事件通知。系统提供保护，以防止系统中其他进程未经授权的访问队列。

2. 发明授权

US5555396A Hierarchical queuing in a system architecture for improved message passing and process synchronization 失效
标题翻译：在系统架构中进行分层排队，以改进消息传递和进程同步
公开(公告)号：US5555396A
公开(公告)日：1996-09-10
申请号：US362034
申请日：1994-12-22
申请人： Merwin H. Alferness , Charles R. Caldarale , David R. Johnson , Joseph P. Kerzman , James R. McBreen
发明人： Merwin H. Alferness , Charles R. Caldarale , David R. Johnson , Joseph P. Kerzman , James R. McBreen
IPC分类号： G06F9/46 , G06F12/00 , G06F12/08
CPC分类号： G06F9/546
摘要： A system and method for interprocess communication between concurrently executing, cooperating sequential processes in a digital computer system uses a shared memory queue as a mechanism for message passing and process synchronization. Data to be transferred from a sending process to a receiving process is stored in a queue entry on the shared memory queue. Hierarchical queuing allows a sending process to collect multiple message segments as entries in a local sub-queue, which is enqueued as a single entity to the shared memory queue when all message segments are present. The receiving process dequeues the sub-queue in one operation, thereby increasing the efficiency of message transfer while preventing the erroneous dequeuing of message segments when multiple receiving processes are waiting on the same shared memory queue. In this manner, the logical maximum size of a message being passed between processes is expanded.
摘要翻译：用于数字计算机系统中的并行执行，协作顺序处理之间的进程间通信的系统和方法使用共享存储器队列作为消息传递和过程同步的机制。要从发送进程转移到接收进程的数据存储在共享内存队列中的队列条目中。分层排队允许发送过程收集多个消息段作为本地子队列中的条目，当存在所有消息段时，本地子队列作为单个实体入队到共享存储器队列。接收处理在一个操作中出现子队列，从而提高消息传输的效率，同时防止当多个接收进程在相同的共享存储器队列上等待时消息段的错误出队。以这种方式，扩展了在进程之间传递的消息的逻辑最大大小。

3. 发明授权

US06684376B1 Method and apparatus for selecting components within a circuit design database 失效
标题翻译：用于在电路设计数据库中选择组件的方法和装置
公开(公告)号：US06684376B1
公开(公告)日：2004-01-27
申请号：US08789026
申请日：1997-01-27
申请人： Joseph P. Kerzman , James E. Rezek , Mark D. Aubel , Merwin H. Alferness
发明人： Joseph P. Kerzman , James E. Rezek , Mark D. Aubel , Merwin H. Alferness
IPC分类号： G06F1750
CPC分类号： G06F17/5072
摘要： A method and apparatus for efficiently selecting cells within a circuit design database. The invention includes four primary features for selecting cells including (1) selecting only those cells that are in a pre-identified region and within a pre-identified selection area; (2) maneuvering through the circuit design hierarchy and selecting cells or regions at selected levels of hierarchy by using predetermined up and down hot-keys; (3) sorting selected cells by instance name, and manually selecting a desired cell or region from the resulting sorted list; and (4) sorting selected cells by a corresponding net name, and manually selecting a desired cell or region from the resulting sorted list.
摘要翻译：一种用于有效地选择电路设计数据库内的单元的方法和装置。本发明包括用于选择单元的四个主要特征，包括：（1）仅选择在预先识别的区域内和预先识别的选择区域内的那些单元; （2）通过电路设计层次来操纵，并通过使用预定的上下热键选择所选层级的单元或区域; （3）按实例名称对所选择的单元进行排序，并从所得到的排序列表中手动选择所需单元格或区域; 和（4）通过相应的网络名称对所选择的单元格进行排序，并从所得到的排序列表中手动选择所需的单元格或区域。

4. 发明授权

US5611065A Address prediction for relative-to-absolute addressing 失效
标题翻译：相对绝对寻址的地址预测
公开(公告)号：US5611065A
公开(公告)日：1997-03-11
申请号：US306085
申请日：1994-09-14
申请人： Merwin H. Alferness , Joseph P. Kerzman , John Z. Nguyen
发明人： Merwin H. Alferness , Joseph P. Kerzman , John Z. Nguyen
IPC分类号： G06F9/355 , G06F9/38 , G06F12/00 , G06F9/26 , G06F9/34 , G06F12/02
CPC分类号： G06F9/342 , G06F9/383 , G06F9/3832
摘要： A base address prediction system for predicting one of a plurality of base addresses to be added to a known relative address in order to generate an absolute address. An actual base address determined from the relative address is also generated. The actual base address determination takes longer to generate than the predicted base address determination, and therefore the predicted base address is used to select a base address as long as the prediction is correct. Circuitry exists to compare the predicted base address with the actual base address, and if not equal, the predicted base address will be nullified, and the actual base address will be used. Prediction modes are dependent on whether the relative address indicates an instruction fetch or an operand fetch. Where the relative address indicates an instruction fetch, the prediction will be based on the last base address used, on the assumption that instructions will be contiguous in a single block of memory. Where the relative address indicates an operand fetch, the prediction will only change upon the occurrence of two consecutive incorrect predictions, and the actual base address will be used during incorrect prediction periods. Staged latching circuitry and comparison circuitry provides a method of determining whether two consecutive predictions were incorrect.
摘要翻译：一种基地址预测系统，用于预测要添加到已知相对地址的多个基地址之一以产生绝对地址。也会生成从相对地址确定的实际基址。实际的基地址确定比预测的基地址确定需要更长的时间，因此只要预测是正确的，就使用预测的基地址来选择基地址。存在电路以将预测的基地址与实际基地址进行比较，如果不相等，则预测的基地址将被取消，并且将使用实际的基地址。预测模式取决于相对地址是指示提取还是操作数提取。在相对地址指示取指的地方，预测将基于所使用的最后基地址，假设指令在单个存储器块中是连续的。在相对地址指示操作数提取的情况下，预测将仅在两次连续不正确预测的发生时发生变化，并且在不正确的预测期间将使用实际基地址。分段闭锁电路和比较电路提供了一种确定两个连续预测是否不正确的方法。

5. 发明授权

US5577259A Instruction processor control system using separate hardware and microcode control signals to control the pipelined execution of multiple classes of machine instructions 失效
标题翻译：指令处理器控制系统使用单独的硬件和微码控制信号来控制多类机器指令的流水线执行
公开(公告)号：US5577259A
公开(公告)日：1996-11-19
申请号：US288651
申请日：1994-08-09
申请人： Merwin H. Alferness , John S. Kuslak , Mark A. Vasquez , Joseph P. Kerzman , Eric S. Collins
发明人： Merwin H. Alferness , John S. Kuslak , Mark A. Vasquez , Joseph P. Kerzman , Eric S. Collins
IPC分类号： G06F9/318 , G06F9/38 , G06F9/72
CPC分类号： G06F9/3017 , G06F9/28 , G06F9/3867
摘要： A digital instruction processor control system for an instruction processor having a multiple stage instruction execution pipeline capable of executing binary instructions in fixed predetermined stages. The control system includes a hardware controller to generate control signals for execution of all pipeline stages of standard instructions and for the first stage of extended cycle instructions and provides a main microcode controller to provide programmed control signals for controlling all subsequent stages of execution of extended cycle instructions. The control system also utilizes a separate sequence microcode controller for execution of certain instructions of a predetermined type including decimal instruction execution, during which time the main microcode controller is under control of the separate sequence controller.
摘要翻译：一种用于具有能够以固定预定阶段执行二进制指令的多级指令执行流水线的指令处理器的数字指令处理器控制系统。控制系统包括一个硬件控制器，用于产生用于执行标准指令的所有流水线阶段的控制信号，并且用于扩展周期指令的第一阶段，并且提供主微代码控制器以提供编程的控制信号，用于控制延伸周期的所有后续执行阶段说明。控制系统还使用单独的序列微代码控制器来执行包括十进制指令执行的预定类型的某些指令，在此期间主微码控制器处于单独的序列控制器的控制之下。

6. 发明授权

US5696693A Method for placing logic functions and cells in a logic design using floor planning by analogy 失效
标题翻译：将逻辑功能和单元格放置在使用楼层规划的逻辑设计中的方法
公开(公告)号：US5696693A
公开(公告)日：1997-12-09
申请号：US414881
申请日：1995-03-31
申请人： Mark D. Aubel , Arthur F. Boehm , Joseph P. Kerzman , James E. Rezek , John T. Rusterholz , Richard F. Paul
发明人： Mark D. Aubel , Arthur F. Boehm , Joseph P. Kerzman , James E. Rezek , John T. Rusterholz , Richard F. Paul
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： A method used by a computer-aided design system for placing logic functions and cells in a floor plan of a very large scale integrated circuit chip. The structure of a set of selected logic functions and cells to be placed is compared to a set of selected logic functions and cells which have previously been placed in the floor plan. If the number of cells and the structure of the sets are analogous, the selected logic functions and cells to be placed are automatically assigned physical positions in the floor plan based on the physical position and structure of the selected logic functions and cells that have already been placed, and on an orientation mode. The orientation mode provides for the reflection of the placement of the selected logic functions and cells about the horizontal axis, the vertical axis, or both the horizontal and vertical axes. The size of the sets of selected logic functions and cells may be arbitrarily large, thereby providing advantages over simple manual placement of logic functions and cells in a floor plan.
摘要翻译：计算机辅助设计系统用于将逻辑功能和单元放置在大规模集成电路芯片的平面图中的方法。一组选定的逻辑功能和要放置的单元的结构与先前已经放置在平面图中的一组选定的逻辑功能和单元进行比较。如果单元的数量和组的结构是类似的，则所选择的逻辑功能和要放置的单元基于所选择的逻辑功能和已经被存储的单元的物理位置和结构自动地在平面图中分配物理位置放置，并在定向模式。取向模式提供了所选逻辑功能和单元格围绕水平轴，垂直轴或水平轴和垂直轴的位置的反射。所选择的逻辑功能和单元组的大小可以是任意大的，从而提供了优于在平面图中简单地手动放置逻辑功能和单元的优点。

7. 发明授权

US06516456B1 Method and apparatus for selectively viewing nets within a database editor tool 失效
标题翻译：用于在数据库编辑器工具内选择性地查看网络的方法和装置
公开(公告)号：US06516456B1
公开(公告)日：2003-02-04
申请号：US08789027
申请日：1997-01-27
申请人： Robert E. Garnett , Joseph P. Kerzman , James E. Rezek , Mark D. Aubel
发明人： Robert E. Garnett , Joseph P. Kerzman , James E. Rezek , Mark D. Aubel
IPC分类号： G06F1750
CPC分类号： G06F17/5072 , G06F17/5022 , G06F17/5045
摘要： A method and apparatus for selectively viewing nets within a database editor tool. The present invention provides four primary features for selectively viewing nets. First, the present invention contemplates selecting a number of objects, and viewing only those nets that are either driven from or received by the selected objects. In a preferred embodiment, the number of objects are placed objects within a placement tool. Second, for those nets that are selected, and that are also coupled to un-placed cells, the present invention contemplate providing fly-wires from the corresponding selected objects to a predetermined location representative of an approximate expected location for the un-placed cells. Third, the present invention contemplate providing a vector filter which may permit only vectored nets with a selected bus width range to be viewed. Finally, the fourth feature of the present invention contemplates providing a means for selectively viewing only those nets that cross a predetermined hierarchical boundary within the circuit design database.
摘要翻译：一种用于在数据库编辑器工具内选择性地查看网络的方法和装置。本发明提供了用于选择性地观察网络的四个主要特征。首先，本发明考虑了选择多个对象，并且仅查看那些从所选择的对象中驱动或接收的网络。在优选实施例中，物体的数量被放置在放置工具内。第二，对于所选择的并且还耦合到未放置的单元的网络，本发明考虑将来自相应的所选对象的飞线提供到表示未放置的单元的近似预期位置的预定位置。第三，本发明考虑提供一种矢量滤波器，其可以仅允许观看具有所选总线宽度范围的矢量网。最后，本发明的第四特征设想提供一种用于仅选择性地观察跨越电路设计数据库内的预定分层边界的那些网络的装置。

8. 发明授权

US06910200B1 Method and apparatus for associating selected circuit instances and for performing a group operation thereon 失效
标题翻译：用于关联所选择的电路实例并用于在其上执行组操作的方法和装置
公开(公告)号：US06910200B1
公开(公告)日：2005-06-21
申请号：US08789028
申请日：1997-01-27
申请人： Mark D. Aubel , Joseph P. Kerzman , James M. Nead , James E. Rezek
发明人： Mark D. Aubel , Joseph P. Kerzman , James M. Nead , James E. Rezek
IPC分类号： G06F9/45 , G06F9/455 , G06F17/50
CPC分类号： G06F17/505
摘要： A method and apparatus for associating selected circuit instances, and for allowing a later group manipulation thereof. Prior to entering a database editor tool, selected instances may be associated with one another, and the association may be recorded in the circuit design database. The database editor tool may then read the circuit design database and identify the selected instances and the association therebetween. The associated instances may be called a group, or preferably a stack. The database editor tool may then perform a group operation on the instances associated with the stack.
摘要翻译：一种用于关联所选择的电路实例并且用于允许稍后的组操作的方法和装置。在输入数据库编辑器工具之前，所选择的实例可以彼此关联，并且关联可以被记录在电路设计数据库中。然后，数据库编辑器工具可以读取电路设计数据库并识别所选择的实例及其间的关联。相关联的实例可以被称为组，或者优选地称为堆栈。然后，数据库编辑器工具可以对与堆栈相关联的实例执行组操作。

9. 发明授权

US06701289B1 Method and apparatus for using a placement tool to manipulate cell substitution lists 失效
标题翻译：使用放置工具来操纵细胞置换列表的方法和装置
公开(公告)号：US06701289B1
公开(公告)日：2004-03-02
申请号：US08789029
申请日：1997-01-27
申请人： Robert E. Garnett , Joseph P. Kerzman , James E. Rezek , Mark D. Aubel
发明人： Robert E. Garnett , Joseph P. Kerzman , James E. Rezek , Mark D. Aubel
IPC分类号： G06F1750
CPC分类号： G06F17/5068 , G06F17/505
摘要： A placement tool that may import and export cell substitution and/or cell selection lists. The cell substitution and/or cell selection lists may be used by the placement tool to substitute and/or modify the placement design database, rather than the original schematic or behavioral database. This may eliminate the need to re-synthesize the circuit design during each design iteration. The present invention further contemplates providing a reset feature which may reset the circuit design database to a previous state, if desired.
摘要翻译：可以导入和导出单元格替换和/或单元格选择列表的布局工具。细胞替换和/或细胞选择列表可以被放置工具用于替代和/或修改放置设计数据库，而不是原始原理图或行为数据库。这可能会消除在每次设计迭代期间重新合成电路设计的需要。本发明还考虑提供复位特征，如果需要，可以将电路设计数据库重置为先前状态。

10. 发明授权

US5726903A Method and apparatus for resolving conflicts between cell substitution recommendations provided by a drive strength adjust tool 失效
标题翻译：用于解决由驱动强度调整工具提供的电池替换建议之间的冲突的方法和装置
公开(公告)号：US5726903A
公开(公告)日：1998-03-10
申请号：US597931
申请日：1996-02-07
申请人： Joseph P. Kerzman , Douglas A. Fuller
发明人： Joseph P. Kerzman , Douglas A. Fuller
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： A method and apparatus for efficiently identifying and resolving conflicts between conflicting cell substitution recommendations. Unlike the prior art, the present invention provides a resolving means within a data processing system to identify and resolve conflicting cell substitution recommendations. The resolving means may categorize the cell substitutions in accordance with a number of predetermined cell substitution types, wherein each of the cell substitution type may be assign a predetermined priority value. Thereafter, the resolving means may identify conflicting cell substitution recommendations, and resolve the conflicts in accordance with the predetermined priority scheme.
摘要翻译：一种用于有效地识别和解决冲突的细胞替代建议之间的冲突的方法和装置。与现有技术不同，本发明提供了一种数据处理系统内的解析装置，用于识别和解决冲突的小区替换建议。分解装置可以根据预定的小区替换类型的数目对小区替换进行分类，其中每个小区替换类型可以分配预定的优先级值。此后，解析装置可以识别冲突的小区替换建议，并且根据预定优先级方案来解决冲突。

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