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1. 发明申请

US20080079061A1 Flash memory cell structure for increased program speed and erase speed 审中-公开
标题翻译：闪存单元结构，提高程序速度和擦除速度
公开(公告)号：US20080079061A1
公开(公告)日：2008-04-03
申请号：US11529166
申请日：2006-09-28
申请人： Meng Ding , Amol Joshi , Takashi Orimoto , Jayendra Bhakta , Lei Xue , Satoshi Torii , Robert Bertram Ogle
发明人： Meng Ding , Amol Joshi , Takashi Orimoto , Jayendra Bhakta , Lei Xue , Satoshi Torii , Robert Bertram Ogle
IPC分类号： H01L29/792 , H01L21/336
CPC分类号： H01L29/792 , H01L29/40117 , H01L29/4234
摘要： According to one exemplary embodiment, a structure, for example a flash memory cell, comprises a transistor gate dielectric stack situated on a semiconductor substrate. The transistor gate dielectric stack includes a bottom oxide layer, a silicon-rich nitride layer situated on the bottom oxide layer, a low silicon-rich nitride layer situated on the silicon-rich nitride layer, and a top oxide layer situated on the low silicon-rich nitride layer. This embodiment results in a nitride based flash memory cell having improved program speed and retention while maintaining a high erase speed. In another embodiment, a flash memory cell may further comprise a high-K dielectric layer situated on the transistor gate dielectric stack.
摘要翻译：根据一个示例性实施例，诸如闪存单元的结构包括位于半导体衬底上的晶体管栅极电介质堆叠。晶体管栅极电介质堆叠包括底部氧化物层，位于底部氧化物层上的富含硅的氮化物层，位于富硅氮化物层上的低富硅氮化物层和位于低硅上的顶部氧化物层富含氮化物层。该实施例导致基于氮化物的闪存单元具有改善的编程速度和保持，同时保持高的擦除速度。在另一个实施例中，快闪存储器单元还可以包括位于晶体管栅极电介质叠层上的高K电介质层。

2. 发明申请

US20080083946A1 MEMORY CELL SYSTEM WITH CHARGE TRAP 有权
标题翻译：带有电荷捕获的存储单元系统
公开(公告)号：US20080083946A1
公开(公告)日：2008-04-10
申请号：US11539984
申请日：2006-10-10
申请人： Shenqing Fang , Rinji Sugino , Jayendra Bhakta , Takashi Orimoto , Hiroyuki Nansei , Yukio Hayakawa , Takayuki Maruyama , Hidehiko Shiraiwa , Kuo-Tung Chang , Lei Xue , Meng Ding , Amol Ramesh Joshi , YouSeok Suh , Harpreet Sachar
发明人： Shenqing Fang , Rinji Sugino , Jayendra Bhakta , Takashi Orimoto , Hiroyuki Nansei , Yukio Hayakawa , Takayuki Maruyama , Hidehiko Shiraiwa , Kuo-Tung Chang , Lei Xue , Meng Ding , Amol Ramesh Joshi , YouSeok Suh , Harpreet Sachar
IPC分类号： H01L29/792 , H01L21/8238
CPC分类号： H01L29/792 , H01L21/28273 , H01L27/115 , H01L27/11568
摘要： A memory cell system is provided including forming a first insulator layer over a semiconductor substrate, forming a charge trap layer over the first insulator layer, and slot plane antenna plasma oxidizing the charge trap layer for forming a second insulator layer.
摘要翻译：提供了一种存储单元系统，包括在半导体衬底上形成第一绝缘体层，在第一绝缘体层上形成电荷陷阱层，以及缝隙平面天线等离子体氧化用于形成第二绝缘体层的电荷陷阱层。

3. 发明授权

US08143661B2 Memory cell system with charge trap 有权
标题翻译：带电荷陷阱的记忆体系统
公开(公告)号：US08143661B2
公开(公告)日：2012-03-27
申请号：US11539984
申请日：2006-10-10
申请人： Shenqing Fang , Rinji Sugino , Jayendra Bhakta , Takashi Orimoto , Hiroyuki Nansei , Yukio Hayakawa , Takayuki Maruyama , Hidehiko Shiraiwa , Kuo-Tung Chang , Lei Xue , Meng Ding , Amol Ramesh Joshi , YouSeok Suh , Harpreet Sachar
发明人： Shenqing Fang , Rinji Sugino , Jayendra Bhakta , Takashi Orimoto , Hiroyuki Nansei , Yukio Hayakawa , Takayuki Maruyama , Hidehiko Shiraiwa , Kuo-Tung Chang , Lei Xue , Meng Ding , Amol Ramesh Joshi , YouSeok Suh , Harpreet Sachar
IPC分类号： H01L29/792
CPC分类号： H01L29/792 , H01L21/28273 , H01L27/115 , H01L27/11568
摘要： A memory cell system is provided including a first insulator layer over a semiconductor substrate, a charge trap layer over the first insulator layer, and slot where the charge trap layer includes a second insulator layer having the characteristic of being grown.
摘要翻译：提供一种存储单元系统，包括半导体衬底上的第一绝缘体层，第一绝缘体层上的电荷陷阱层和电荷陷阱层包括具有生长特性的第二绝缘体层的槽。

4. 发明申请

US20080142874A1 INTEGRATED CIRCUIT SYSTEM WITH IMPLANT OXIDE 审中-公开
标题翻译：具有氧化铟的集成电路系统
公开(公告)号：US20080142874A1
公开(公告)日：2008-06-19
申请号：US11611860
申请日：2006-12-16
申请人： Shenqing Fang , Rinji Sugino , Jayendra Bhakta , Takashi Orimoto , Hiroyuki Nansei , Yukio Hayakawa , Hidehiko Shiraiwa , Takayuki Maruyama , Kuo-Tung Chang , YouSeok Suh , Amol Ramesh Joshi , Harpreet Sachar , Simon Siu-Sing Chan
发明人： Shenqing Fang , Rinji Sugino , Jayendra Bhakta , Takashi Orimoto , Hiroyuki Nansei , Yukio Hayakawa , Hidehiko Shiraiwa , Takayuki Maruyama , Kuo-Tung Chang , YouSeok Suh , Amol Ramesh Joshi , Harpreet Sachar , Simon Siu-Sing Chan
IPC分类号： H01L29/792 , H01L21/3205
CPC分类号： H01L29/792 , H01L29/66833
摘要： A method for forming an integrated circuit system is provided including forming a substrate; forming a stack over the substrate, the stack having a sidewall and formed from a charge trap layer and a semi-conducting layer; and slot plane antenna oxidizing the stack for forming a protection enclosure having a protection layer along the sidewall.
摘要翻译：提供一种用于形成集成电路系统的方法，包括：形成衬底; 在衬底上形成堆叠，所述堆叠具有侧壁并由电荷陷阱层和半导体层形成; 以及缝隙平面天线，用于氧化该叠层以形成具有沿该侧壁的保护层的保护罩。

5. 发明授权

US06333218B1 Method of etching contacts with reduced oxide stress 有权
标题翻译：蚀刻氧化应力减小接触的方法
公开(公告)号：US06333218B1
公开(公告)日：2001-12-25
申请号：US09501995
申请日：2000-02-11
申请人： Minh Van Ngo , Jayendra Bhakta , Paul Besser
发明人： Minh Van Ngo , Jayendra Bhakta , Paul Besser
IPC分类号： H01L218238
CPC分类号： H01L21/02164 , H01L21/02211 , H01L21/02274 , H01L21/02337 , H01L21/31612 , H01L21/76224
摘要： A method for manufacturing a semiconductor device forms a trench of a trench isolation region in a portion of a top surface of a semiconductor substrates. Oxide is deposited as a trench liner in the trench using high temperature high density plasma (HDP) deposition. As the high temperature HDP oxide deposition is a stress neutral process, stress defects in an interface between the silicon substrate and the oxide layer are avoided, so that subsequent etching steps in a local interconnect process are less likely to overreach at the interface. This reduces the possibility of junction leakage when the local interconnect is formed.
摘要翻译：半导体器件的制造方法在半导体衬底的顶表面的一部分中形成沟槽隔离区的沟槽。使用高温高密度等离子体（HDP）沉积，氧化物作为沟槽衬垫沉积在沟槽中。由于高温HDP氧化物沉积是应力中性过程，因此避免了硅衬底和氧化物层之间的界面处的应力缺陷，使得局部互连工艺中的后续蚀刻步骤不太可能在界面处超范围。当局部互连形成时，这减少了结漏电的可能性。

6. 发明授权

US06458212B1 Mesh filter design for LPCVD TEOS exhaust system 失效
标题翻译： LPCVD TEOS排气系统的滤网设计
公开(公告)号：US06458212B1
公开(公告)日：2002-10-01
申请号：US09539393
申请日：2000-03-31
申请人： Fuodoor Gologhlan , David Chi , Kent Kuohua Chang , Hector Serrato , Jayendra Bhakta
发明人： Fuodoor Gologhlan , David Chi , Kent Kuohua Chang , Hector Serrato , Jayendra Bhakta
IPC分类号： C23C1600
CPC分类号： C23C16/4412 , Y10S55/30
摘要： One aspect of the present invention relates to a tetraethylorthosilicate chemical vapor deposition method, involving the steps of forming a film on a substrate using tetraethylorthosilicate in a chemical vapor deposition chamber; and removing tetraethylorthosilicate byproducts from the chemical vapor deposition chamber via a pump system and an exhaust line connected to the chemical vapor deposition chamber, the exhaust line comprising a mesh filter having a conical shape. Another aspect of the present invention relates to an exhaust system for removing tetraethylorthosilicate byproducts from a chemical vapor deposition chamber, containing an exhaust line connected to the chemical vapor deposition chamber, the exhaust line comprising a mesh filter having a conical shape via a pump system; and a pump system connected to the exhaust line for removing tetraethylorthosilicate byproducts from the processing chamber.
摘要翻译：本发明的一个方面涉及一种四乙基原硅酸盐化学气相沉积方法，包括以下步骤：在化学气相沉积室中使用原硅酸四乙酯在基底上形成膜; 以及经由泵系统和连接到化学气相沉积室的排气管线从化学气相沉积室除去原硅酸四乙酯副产物，排气管线包括具有圆锥形状的网状过滤器。本发明的另一方面涉及一种用于从化学气相沉积室除去原硅酸四乙酯副产物的排气系统，该排气系统包含连接到化学气相沉积室的排气管线，该排气管线包括经由泵系统具有锥形形状的网状过滤器; 以及与排气管连接以从处理室除去原硅酸四乙酯副产物的泵系统。

7. 发明授权

US06258697B1 Method of etching contacts with reduced oxide stress 有权
标题翻译：蚀刻氧化应力减小接触的方法
公开(公告)号：US06258697B1
公开(公告)日：2001-07-10
申请号：US09502333
申请日：2000-02-11
申请人： Jayendra Bhakta , Paul Besser , Minh Van Ngo
发明人： Jayendra Bhakta , Paul Besser , Minh Van Ngo
IPC分类号： H01L2176
CPC分类号： H01L21/02164 , H01L21/02211 , H01L21/02271 , H01L21/02337 , H01L21/31612 , H01L21/76224
摘要： A method for manufacturing a semiconductor device forms a trench of a trench isolation region in a portion of a top surface of a semiconductor substrate. Oxide is deposited as a trench liner in the trench using low pressure chemical vapor deposition (LPCVD) high temperature oxidation (HTO). As LPCVD is a stress neutral process, stress defects in an interface between the silicon substrate and the oxide layer are avoided, so that subsequent etching steps in a local interconnect process are less likely to overetch at the interface. This reduces the possibility of junction leakage when the local interconnect is formed.
摘要翻译：半导体器件的制造方法在半导体衬底的顶表面的一部分中形成沟槽隔离区的沟槽。使用低压化学气相沉积（LPCVD）高温氧化（HTO）将氧化物作为沟槽衬垫沉积在沟槽中。由于LPCVD是应力中性过程，因此避免了硅衬底和氧化物层之间的界面中的应力缺陷，使得局部互连工艺中的后续蚀刻步骤不太可能在界面处过蚀刻。当局部互连形成时，这减少了结漏电的可能性。

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