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1. 发明授权

US06258697B1 Method of etching contacts with reduced oxide stress 有权
标题翻译：蚀刻氧化应力减小接触的方法
公开(公告)号：US06258697B1
公开(公告)日：2001-07-10
申请号：US09502333
申请日：2000-02-11
申请人： Jayendra Bhakta , Paul Besser , Minh Van Ngo
发明人： Jayendra Bhakta , Paul Besser , Minh Van Ngo
IPC分类号： H01L2176
CPC分类号： H01L21/02164 , H01L21/02211 , H01L21/02271 , H01L21/02337 , H01L21/31612 , H01L21/76224
摘要： A method for manufacturing a semiconductor device forms a trench of a trench isolation region in a portion of a top surface of a semiconductor substrate. Oxide is deposited as a trench liner in the trench using low pressure chemical vapor deposition (LPCVD) high temperature oxidation (HTO). As LPCVD is a stress neutral process, stress defects in an interface between the silicon substrate and the oxide layer are avoided, so that subsequent etching steps in a local interconnect process are less likely to overetch at the interface. This reduces the possibility of junction leakage when the local interconnect is formed.
摘要翻译：半导体器件的制造方法在半导体衬底的顶表面的一部分中形成沟槽隔离区的沟槽。使用低压化学气相沉积（LPCVD）高温氧化（HTO）将氧化物作为沟槽衬垫沉积在沟槽中。由于LPCVD是应力中性过程，因此避免了硅衬底和氧化物层之间的界面中的应力缺陷，使得局部互连工艺中的后续蚀刻步骤不太可能在界面处过蚀刻。当局部互连形成时，这减少了结漏电的可能性。

2. 发明授权

US06333218B1 Method of etching contacts with reduced oxide stress 有权
标题翻译：蚀刻氧化应力减小接触的方法
公开(公告)号：US06333218B1
公开(公告)日：2001-12-25
申请号：US09501995
申请日：2000-02-11
申请人： Minh Van Ngo , Jayendra Bhakta , Paul Besser
发明人： Minh Van Ngo , Jayendra Bhakta , Paul Besser
IPC分类号： H01L218238
CPC分类号： H01L21/02164 , H01L21/02211 , H01L21/02274 , H01L21/02337 , H01L21/31612 , H01L21/76224
摘要： A method for manufacturing a semiconductor device forms a trench of a trench isolation region in a portion of a top surface of a semiconductor substrates. Oxide is deposited as a trench liner in the trench using high temperature high density plasma (HDP) deposition. As the high temperature HDP oxide deposition is a stress neutral process, stress defects in an interface between the silicon substrate and the oxide layer are avoided, so that subsequent etching steps in a local interconnect process are less likely to overreach at the interface. This reduces the possibility of junction leakage when the local interconnect is formed.
摘要翻译：半导体器件的制造方法在半导体衬底的顶表面的一部分中形成沟槽隔离区的沟槽。使用高温高密度等离子体（HDP）沉积，氧化物作为沟槽衬垫沉积在沟槽中。由于高温HDP氧化物沉积是应力中性过程，因此避免了硅衬底和氧化物层之间的界面处的应力缺陷，使得局部互连工艺中的后续蚀刻步骤不太可能在界面处超范围。当局部互连形成时，这减少了结漏电的可能性。

3. 发明授权

US06483153B1 Method to improve LDD corner control with an in-situ film for local interconnect processing 失效
标题翻译：用于局部互连处理的用于改善LDD角部控制的方法
公开(公告)号：US06483153B1
公开(公告)日：2002-11-19
申请号：US09418316
申请日：1999-10-14
申请人： Angela Hui , Paul Besser , Minh-Van Ngo
发明人： Angela Hui , Paul Besser , Minh-Van Ngo
IPC分类号： H01L2976
CPC分类号： H01L21/76897 , H01L21/76895
摘要： A method to improve LDD corner control during a local interconnect trench oxide etch on a semiconductor device by providing a first etch stop layer over the gate and active regions in the substrate and further providing thereon a second etch stop layer made of polysilicon and having of a different composition than that of the first etch stop layer. By forming a second etch stop layer of polysilicon the present invention improves the selectivity of the local interconnect trench oxide etch, thereby improving the ability of the first and second etch stop layers to stop the etch process at the critical interfaces.
摘要翻译：一种在半导体器件上的局部互连沟槽氧化物蚀刻期间，通过在衬底上的栅极和有源区上提供第一蚀刻停止层并且还在其上提供由多晶硅制成的第二蚀刻停止层来改善LDD拐角控制的方法，不同于第一蚀刻停止层的组成。通过形成多晶硅的第二蚀刻停止层，本发明改善了局部互连沟槽氧化物蚀刻的选择性，从而提高了第一和第二蚀刻停止层在关键界面处停止蚀刻工艺的能力。

4. 发明授权

US06297148B1 Method of forming a silicon bottom anti-reflective coating with reduced junction leakage during salicidation 有权
标题翻译：形成硅底部抗反射涂层的方法，其在硫化过程中具有减少的结渗漏
公开(公告)号：US06297148B1
公开(公告)日：2001-10-02
申请号：US09477808
申请日：2000-01-05
申请人： Paul Besser , Minh Van Ngo , Yowjuang Bill Liu
发明人： Paul Besser , Minh Van Ngo , Yowjuang Bill Liu
IPC分类号： H01L214763
CPC分类号： H01L21/28518
摘要： A method of performing ultra-shallow junctions in a semiconductor wafer uses a silicon layer to achieve ultra-low silicon consumption during a salicide formation process. A refractory metal layer, such as a cobalt layer, is deposited over the gate and source/drain junctions of the semiconductor device. After a rapid thermal annealing is performed to form the high-ohmic phase of the salicide, a silicon layer is deposited at a low temperature over the semiconductor device. The silicon layer provides a source of silicon for consumption during a second thermal annealing step, reducing the amount of silicon of the source/drain junctions that is consumed. The second thermal annealing step is performed in a nitrogen and oxygen atmosphere so at the silicon layer is transformed into a silicon oxynitride bottom anti-reflective coating layer.
摘要翻译：在半导体晶片中进行超浅结的方法使用硅层，以在自对准硅化物形成工艺期间实现超低硅消耗。诸如钴层的难熔金属层沉积在半导体器件的栅极和源极/漏极结上。在进行快速热退火以形成硅化物的高欧姆相后，在低温下在半导体器件上沉积硅层。硅层在第二热退火步骤期间提供用于消耗的硅源，减少消耗的源极/漏极结的硅的量。第二热退火步骤在氮和氧气氛中进行，因此在硅层转变为氮氧化硅底部抗反射涂层。

5. 发明授权

US07071086B2 Method of forming a metal gate structure with tuning of work function by silicon incorporation 有权
标题翻译：通过硅掺入调整功函数形成金属栅结构的方法
公开(公告)号：US07071086B2
公开(公告)日：2006-07-04
申请号：US10420721
申请日：2003-04-23
申请人： Christy Woo , Paul Besser , Minh van Ngo , James Pan , Jinsong Yin
发明人： Christy Woo , Paul Besser , Minh van Ngo , James Pan , Jinsong Yin
IPC分类号： H01L21/3205
CPC分类号： H01L29/66545 , H01L21/28079 , H01L21/28088 , H01L21/3215 , H01L29/495 , H01L29/4966 , H01L29/78
摘要： A method for forming a semiconductor structure having a metal gate with a controlled work function includes the step of forming a precursor having a substrate with active regions separated by a channel, a temporary gate over the channel and within a dielectric layer. The temporary gate is removed to form a recess with a bottom and sidewalls in the dielectric layer. A non-silicon containing metal layer is deposited in the recess. Silicon is incorporated into the metal layer and a metal is deposited on the metal layer. The incorporation of the silicon is achieved by silane treatments that are performed before, after or both before and after the depositing of the metal layer. The amount of silicon incorporated into the metal layer controls the work function of the metal gate that is formed.
摘要翻译：用于形成具有受控功函数的金属栅极的半导体结构的方法包括形成具有基板的前体的步骤，该基板具有被沟道分隔的有源区，在该沟道上的介电层内的临时栅极。移除临时栅极以形成具有介电层中的底部和侧壁的凹部。在凹槽中沉积非硅的金属层。将硅结合到金属层中，并且在金属层上沉积金属。通过在沉积金属层之前，之后或之后进行的硅烷处理来实现硅的引入。结合到金属层中的硅的量控制形成的金属栅的功函数。

6. 发明授权

US06830998B1 Gate dielectric quality for replacement metal gate transistors 失效
标题翻译：更换金属栅极晶体管的栅极介电质量得到改善
公开(公告)号：US06830998B1
公开(公告)日：2004-12-14
申请号：US10462667
申请日：2003-06-17
申请人： James Pan , Paul Besser , Christy Mei-Chu Woo , Minh Van Ngo , Jinsong Yin
发明人： James Pan , Paul Besser , Christy Mei-Chu Woo , Minh Van Ngo , Jinsong Yin
IPC分类号： H01L213205
CPC分类号： H01L29/66606 , H01L21/28088 , H01L29/4966 , H01L29/66545
摘要： Gate dielectric degradation due to plasma damage during replacement metal gate processing is cured and prevented from further plasma degradation by treatment of the gate dielectric after removing the polysilicon gate. Embodiments include low temperature vacuum annealing after metal deposition and CMP, annealing in oxygen and argon, ozone or a forming gas before metal deposition, or heat soaking in silane or disilane, before metal deposition.
摘要翻译：在更换金属栅极处理期间由于等离子体损坏引起的栅极介质劣化被固化并且通过在去除多晶硅栅极之后处理栅极电介质来防止进一步的等离子体劣化。实施例包括在金属沉积之前的金属沉积和CMP之后的低温真空退火，在氧气和氩气中的退火，在金属沉积之前的臭氧或形成气体，或者在金属沉积之前的硅烷或乙硅烷中的热浸渍。

7. 发明申请

US20060267107A1 Ultra-uniform silicide system in integrated circuit technology 有权
标题翻译：集成电路技术中超均匀的硅化物系统
公开(公告)号：US20060267107A1
公开(公告)日：2006-11-30
申请号：US11252493
申请日：2005-10-17
申请人： Robert Chiu , Jeffrey Patton , Paul Besser , Minh Ngo
发明人： Robert Chiu , Jeffrey Patton , Paul Besser , Minh Ngo
IPC分类号： H01L29/76 , H01L21/336
CPC分类号： H01L21/28518
摘要： A structure of an integrated circuit is provided. A gate dielectric is formed on a semiconductor substrate, and a gate is formed over a gate dielectric on the semiconductor substrate. Source/drain junctions are formed in the semiconductor substrate. Ultra-uniform suicides are formed on the source/drain junctions, and a dielectric layer is deposited above the semiconductor substrate. Contacts are then formed in the dielectric layer to the ultra-uniform silicides.
摘要翻译：提供集成电路的结构。在半导体衬底上形成栅极电介质，并且在半导体衬底上的栅极电介质上形成栅极。在半导体衬底中形成源极/漏极结。在源极/漏极结上形成超均匀的硅化物，并且在半导体衬底上沉积电介质层。然后在电介质层中形成与超均匀硅化物的接触。

8. 发明申请

US20050085073A1 Method of using an adhesion precursor layer for chemical vapor deposition (CVD) copper deposition 失效
标题翻译：使用化学气相沉积（CVD）铜沉积的粘附前体层的方法
公开(公告)号：US20050085073A1
公开(公告)日：2005-04-21
申请号：US10687186
申请日：2003-10-16
申请人： Sergey Lopatin , Paul Besser , Alline Myers , Jeremias Romero , Minh Tran , Lu You , Connie Wang
发明人： Sergey Lopatin , Paul Besser , Alline Myers , Jeremias Romero , Minh Tran , Lu You , Connie Wang
IPC分类号： H01L21/44 , H01L21/4763 , H01L21/768
CPC分类号： H01L21/76846 , H01L21/76877
摘要： An exemplary embodiment is related to a method of using an adhesion precursor in an integrated circuit fabrication process. The method includes providing a gas of material over a dielectric material and providing a copper layer over an adhesion precursor layer. The adhesion precursor layer is formed by the gas, and the dielectric material includes an aperture.
摘要翻译：示例性实施例涉及在集成电路制造工艺中使用粘附前体的方法。该方法包括在介电材料上提供材料的气体并在粘附前体层上提供铜层。粘附前体层由气体形成，电介质材料包括孔。

9. 发明授权

US06461951B1 Method of forming a sidewall spacer to prevent gouging of device junctions during interlayer dielectric etching including silicide growth over gate spacers 有权
标题翻译：形成侧壁间隔物的方法，以防止包括在栅极间隔物上的硅化物生长的层间电介质蚀刻期间器件结的气蚀
公开(公告)号：US06461951B1
公开(公告)日：2002-10-08
申请号：US09280662
申请日：1999-03-29
申请人： Paul Besser , Angela Hui , Yowjuang W. Liu
发明人： Paul Besser , Angela Hui , Yowjuang W. Liu
IPC分类号： H01L213205
CPC分类号： H01L21/76897 , H01L21/76895 , H01L29/665 , H01L29/6656
摘要： A method and arrangement for forming a recessed spacer to prevent the gouging of device junctions during a contact etch or local interconnect etch process deliberately overetches the spacer material layer during the formation of sidewall spacers on the sidewalls of a gate. The exposed portions of the gate sidewalls are then covered by silicide formed during a silicidation process. The formation of the suicide on the gate sidewalls prevents the sidewall spacers from being preferentially attacked during a local interconnect etch or contact etch.
摘要翻译：用于形成凹陷间隔物以防止在接触蚀刻或局部互连蚀刻工艺期间器件结的气蚀在形成栅极侧壁上的侧壁间隔物期间故意破坏间隔物材料层的方法和装置。然后，在硅化过程中形成的硅化物覆盖栅极侧壁的暴露部分。在栅极侧壁上形成硅化物防止在局部互连蚀刻或接触蚀刻期间侧壁间隔物被优先攻击。

10. 发明授权

US06365516B1 Advanced cobalt silicidation with in-situ hydrogen plasma clean 有权
标题翻译：先进的钴硅化物与原位氢等离子体清洁
公开(公告)号：US06365516B1
公开(公告)日：2002-04-02
申请号：US09483081
申请日：2000-01-14
申请人： Austin Frenkel , Akif Sultan , Paul Besser
发明人： Austin Frenkel , Akif Sultan , Paul Besser
IPC分类号： H01L2144
CPC分类号： H01L21/0206 , H01L21/28518
摘要： Various methods of fabricating a silicide structure are provided. In one aspect, a method of fabricating a circuit structure on a silicon surface is provided that includes exposing the silicon surface to a plasma ambient containing hydrogen and an inert gas, and depositing a metallic material capable of forming silicide on the silicon surface. The metallic material is heated to form a metal silicide on the silicon surface. The method provides for low sheet resistance silicide structures by eliminating native oxide films without the risk of spacer material backsputtering.
摘要翻译：提供了制造硅化物结构的各种方法。一方面，提供一种在硅表面上制造电路结构的方法，其包括将硅表面暴露于含有氢气和惰性气体的等离子体环境中，以及在硅表面上沉积能够形成硅化物的金属材料。金属材料被加热以在硅表面上形成金属硅化物。该方法通过消除天然氧化物膜而不会产生间隔材料反溅镀的风险，从而提供低电阻硅化物结构。

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