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1. 发明授权

US06451701B1 Method for making low-resistance silicide contacts between closely spaced electrically conducting lines for field effect transistors 有权
标题翻译：用于场效应晶体管的紧密间隔的导电线之间制造低电阻硅化物接触的方法
公开(公告)号：US06451701B1
公开(公告)日：2002-09-17
申请号：US09993068
申请日：2001-11-14
申请人： Mei-Yun Wang , Shwangming Jeng , Shau-Lin Shue
发明人： Mei-Yun Wang , Shwangming Jeng , Shau-Lin Shue
IPC分类号： H01L21425
CPC分类号： H01L29/665 , H01L21/28518 , H01L21/31155
摘要： A method for making reliable low-resistance contacts between closely spaced FET gate electrodes having high-aspect-ratio spacings. Polysilicon gate electrodes are formed. A conformal insulating layer is deposited and anisotropically etched back to form sidewall spacers on the gate electrodes. During conventional etch-back, the etch rate of the insulating layer between the closely spaced gate electrodes is slower resulting in a residual oxide that prevents the formation of reliable low-resistance contacts. This residual oxide requires an overetch in a hydrofluoric acid solution prior to forming silicide contacts. The wet overetch results in device degradation. A nitrogen or germanium implant is used to amorphize the oxide and to increase the wet etch rate of the residual oxide. Using this amorphization the wet etch that is commonly used as a pre-clean prior to forming silicide contacts can be used to remove the residual silicon oxide without overetching. The implant also results in a smoother interface between the silicide and the silicon substrate, which results in lower sheet resistance.
摘要翻译：一种用于在具有高纵横比间隔的紧密间隔的FET栅电极之间进行可靠的低电阻接触的方法。形成多晶硅栅电极。沉积保形绝缘层并各向异性地回蚀以在栅电极上形成侧壁间隔物。在传统的回蚀期间，绝缘层在紧密间隔的栅电极之间的蚀刻速率较慢，导致残留的氧化物阻止形成可靠的低电阻触点。在形成硅化物接触之前，该残余氧化物需要在氢氟酸溶液中进行过蚀刻。湿过滤会导致设备退化。氮或锗植入物用于使氧化物非晶化并增加残余氧化物的湿蚀刻速率。使用这种非晶化，通常在形成硅化物接触之前通常用作预清洁的湿法蚀刻可以用于除去剩余的氧化硅而不进行过蚀刻。该植入物还导致硅化物和硅衬底之间更平滑的界面，这导致较低的薄层电阻。

2. 发明授权

US06268294B1 Method of protecting a low-K dielectric material 有权
标题翻译：保护低K电介质材料的方法
公开(公告)号：US06268294B1
公开(公告)日：2001-07-31
申请号：US09542807
申请日：2000-04-04
申请人： Syun-Ming Jang , Shwangming Jeng , Weng Chang
发明人： Syun-Ming Jang , Shwangming Jeng , Weng Chang
IPC分类号： H01L2146
CPC分类号： H01L21/76831 , H01L21/0212 , H01L21/02126 , H01L21/02134 , H01L21/0214 , H01L21/022 , H01L21/02274 , H01L21/0276 , H01L21/3122 , H01L21/3124 , H01L21/31633 , H01L21/76807 , H01L21/76826
摘要： A method for forming a dual damascene conductor interconnection layer within an inter-level metal dielectric (IMD) layer formed upon a substrate employed within a microelectronics fabrication. There is provided a substrate employed within a microelectronics fabrication. There is then formed over the substrate a series of conductor lines. There is then formed over the substrate a dielectric layer. There is then formed over the dielectric layer an intermediate second dielectric layer. There is then formed over the substrate a patterned photoresist etch mask layer. There is then etched the pattern of the photoresist etch mask-layer into and through the dielectric layers, followed by stripping the photoresist layer. There is then treated the exposed dielectric layer surface to a reactive gas to form a reacted surface layer. There may then be formed over the substrate additional patterned photoresist etch mask layers, with attenuated degradation of the dielectric layers due to the organic materials and methods for cleaning and stripping same.
摘要翻译：在用于微电子制造的基板上形成的层间金属电介质（IMD）层内形成双镶嵌导体互连层的方法。提供了在微电子制造中使用的衬底。然后在衬底上形成一系列导体线。然后在衬底上形成介电层。然后在电介质层上形成中间第二电介质层。然后在衬底上形成图案化的光致抗蚀剂蚀刻掩模层。然后将光致抗蚀剂蚀刻掩模层的图案蚀刻到介电层中并通过电介质层，随后剥离光致抗蚀剂层。然后将暴露的介电层表面处理成反应气体以形成反应的表面层。然后可以在衬底上形成附加的图案化的光致抗蚀剂蚀刻掩模层，由于有机材料和用于清洁和剥离的方法，电介质层的衰减降低。

3. 发明授权

US06457477B1 Method of cleaning a copper/porous low-k dual damascene etch 有权
标题翻译：清洗铜/多孔低k双镶嵌蚀刻的方法
公开(公告)号：US06457477B1
公开(公告)日：2002-10-01
申请号：US09624020
申请日：2000-07-24
申请人： Bao-Ru Young , Li-Chih Chao , Shwangming Jeng , Chi-Shiung Tsai
发明人： Bao-Ru Young , Li-Chih Chao , Shwangming Jeng , Chi-Shiung Tsai
IPC分类号： H01L21302
CPC分类号： H01L21/76814 , H01L21/76807 , Y10S134/902 , Y10S438/906 , Y10S438/963
摘要： A method of cleaning a low-k material etched opening, comprising the following steps. A semiconductor structure having an exposed device therein is provided. An etch stop layer is formed over the semiconductor structure and the exposed device. A layer of low-k material is formed over the etch stop layer semiconductor structure and device. A patterned layer of photoresist is formed over the low-k material layer. The patterned photoresist layer is used as a mask to etch low-k material layer is etched to form an opening exposing at least a portion of the etch stop layer over the device. The patterned photoresist layer is removed by a low temperature ashing process at a temperature from about 23 to 27° C., and more preferably about 25° C. (room temperature). The exposed portion of the etch stop layer over the device is removed to expose the underlying device by a low pressure, low bias etching process at a pressure from about 8 to 12 milli-Torr and a bias power from about 25 to 35 W. The exposed underlying device and the opening are cleaned by removing any remaining low pressure, low bias etch polymer and etch residue by a fully dry-type cleaning process using an H2He gas.
摘要翻译：一种清洁低k材料蚀刻开口的方法，包括以下步骤。提供其中具有暴露设备的半导体结构。在半导体结构和暴露的器件上形成蚀刻停止层。在蚀刻停止层半导体结构和器件上形成一层低k材料。在低k材料层上形成图案化的光致抗蚀剂层。图案化的光致抗蚀剂层用作掩模以蚀刻低k材料层被蚀刻以形成暴露在该器件上的蚀刻停止层的至少一部分的开口。通过低温灰化过程在约23至27℃，更优选约25℃（室温）的温度下除去图案化的光致抗蚀剂层。去除器件上的蚀刻停止层的暴露部分，通过低压，低偏压蚀刻工艺在约8至12毫乇的压力和约25至35瓦的偏压功率下暴露下层器件。通过使用H2He气体通过完全干式清洁方法除去任何剩余的低压，低偏压蚀刻聚合物和蚀刻残留物来清洁露出的下部器件和开口。

4. 发明授权

US06277658B1 Method for monitoring alignment mark shielding 有权
标题翻译：监控对准标记屏蔽的方法
公开(公告)号：US06277658B1
公开(公告)日：2001-08-21
申请号：US09282059
申请日：1999-03-29
申请人： Shwangming Jeng , Jeng-Horng Chen , Chen-Hua Yu
发明人： Shwangming Jeng , Jeng-Horng Chen , Chen-Hua Yu
IPC分类号： H01L2166
CPC分类号： H01L23/544 , H01L2223/5442 , H01L2223/54493 , H01L2924/0002 , H01L2924/00
摘要： A method of using a monitor wafer to monitor the shielding of alignment marks during material deposition steps. The alignment marks are shielded using shielding tabs attached to the clamp ring used to clamp the wafer during deposition of a layer of material. An oxide monitor wafer, having the same size and shape of product wafers, has monitor marks formed thereon. The center of the monitor marks has the same location on the monitor wafer as the alignment marks have on the product wafers. The monitor wafer is subjected to the same processing steps as the product wafers through the step of material deposition. The clamp ring is removed from the monitor wafer and the distance from the center of the monitor marks and the edge of the deposited material is determined. The monitor marks are formed so that the distance from the center of the monitor marks and the edge of the deposited material can be determined by direct observation of the monitor marks. The monitor wafers are processed after adjustments to or maintenance on equipment or after a fixed number of product wafers are processed.
摘要翻译：在材料沉积步骤期间使用监测晶片监测对准标记的屏蔽的方法。使用在用于在沉积材料层期间夹紧晶片的夹紧环附近的屏蔽突片来对准对准标记。具有相同尺寸和形状的产品晶片的氧化物监视器晶片具有形成在其上的监视标记。显示器标记的中心在显示器晶片上具有与对准标记在产品晶片上的位置相同的位置。通过材料沉积步骤对显示器晶片进行与产品晶片相同的处理步骤。夹持环从监视器晶片上移除，并且确定与监视器标记的中心和沉积材料的边缘的距离。监视标记形成为能够通过监视标记的直接观察来确定与监视标记的中心和沉积材料的边缘的距离。在对设备进行调整或维护之后或在固定数量的产品晶片被处理之后处理监视器晶片。

5. 发明授权

US06328815B1 Multiple chamber vacuum processing system configuration for improving the stability of mark shielding process 有权
标题翻译：多室真空处理系统配置，提高标记屏蔽过程的稳定性
公开(公告)号：US06328815B1
公开(公告)日：2001-12-11
申请号：US09253292
申请日：1999-02-19
申请人： Shwangming Jeng , Chen-Fang Chung
发明人： Shwangming Jeng , Chen-Fang Chung
IPC分类号： B08B102
CPC分类号： H01L21/67167 , H01L21/67184 , H01L21/67745 , Y10S134/902 , Y10S438/908
摘要： A new configuration of a basic concatenatable integrated modular multiple chamber vacuum processing system for wafer manufacturing vacuum processes is disclosed. The basic system includes at least one multiple ported transfer vacuum chamber, an R-&thgr; transfer means contained within each chamber, a multiplicity of ports adaptable for appending a variety of vacuum process chambers as well as forming entrance/exit ports with at least one dual port pass through chamber attached to one entrance/exit port. Each pass through chamber contains a wafer alignment and/or orientation means for aligning or orienting the wafer as necessary in any of the appended process chambers. The configuration minimizes alignment or orientation errors due to inherent instability of the concatenated transfer means operations.
摘要翻译：公开了一种用于晶片制造真空工艺的基本可连接的集成模块化多室真空处理系统的新配置。基本系统包括至少一个多端口转移真空室，每个室内包含的R-θ转移装置，适用于附加各种真空处理室的多个端口，以及形成具有至少一个双重端口的入口/出口端口港口通过一个入口/出口连接室。每个通过室包含用于在任何附加的处理室中根据需要对准或定向晶片的晶片对准和/或取向装置。由于连接的传送装置操作的固有不稳定性，该配置使对准或取向误差最小化。

6. 发明授权

US06207483B1 Method for smoothing polysilicon gate structures in CMOS devices 有权
标题翻译： CMOS器件中多晶硅栅极结构平滑化的方法
公开(公告)号：US06207483B1
公开(公告)日：2001-03-27
申请号：US09527183
申请日：2000-03-17
申请人： Chu-Yun Fu , Chung-Long Chang , Syun-Ming Jang , Shwangming Jeng
发明人： Chu-Yun Fu , Chung-Long Chang , Syun-Ming Jang , Shwangming Jeng
IPC分类号： H01L218238
CPC分类号： H01L21/823828 , H01L21/28035 , H01L21/32115
摘要： There is provided a method for smoothing the surface of undoped polysilicon regions of a CMOS structure, primarily gate regions. A direct HPD-CVD argon sputter is used improve the surface roughness by a factor of more than 50%. The argon plasma sputter may be used either alone or in conjunction with a thin capping layer of oxide, nitride or oxynitride. The devices manufactured using the process exhibit excellent electrical characteristics and improved reliability compared to devices made using conventional manufacturing processes.
摘要翻译：提供了一种用于平滑CMOS结构的未掺杂多晶硅区域的表面的方法，主要是栅极区域。使用直接HPD-CVD氩溅射将表面粗糙度提高了50％以上。氩等离子体溅射可以单独使用或与氧化物，氮化物或氮氧化物的薄覆盖层结合使用。与使用常规制造工艺制造的器件相比，使用该工艺制造的器件表现出优异的电气特性和改进的可靠性。

7. 发明授权

US6080638A Formation of thin spacer at corner of shallow trench isolation (STI) 有权
标题翻译：在浅沟槽隔离角（STI）处形成薄间隔物
公开(公告)号：US6080638A
公开(公告)日：2000-06-27
申请号：US244880
申请日：1999-02-05
申请人： Chung-Te Lin , Shwangming Jeng , Yuan-Horng Chiu , Kong-Beng Thei
发明人： Chung-Te Lin , Shwangming Jeng , Yuan-Horng Chiu , Kong-Beng Thei
IPC分类号： H01L21/762 , H01L21/76
CPC分类号： H01L21/76224
摘要： A method to reduce to reduce DRAM capacitor STI junction leakage current. A Shallow Trench Isolation opening is formed, within this opening Field Oxide is deposited. The top surface of the FOX is etched down and a second layer of oxide is deposited over the FOX and the adjacent active regions. This second layer of oxide is etched bringing the top surface down to below the level of the top surface of the surrounding active areas but leaving spacers where the top surface of the FOX intersects with the active areas.
摘要翻译：一种降低DRAM电容器STI结的漏电流的方法。形成浅沟槽隔离开口，在该开口中形成场氧化物。 FOX的顶表面被蚀刻并且在FOX和相邻的活性区上沉积第二层氧化物。该第二层氧化物被蚀刻，使顶部表面向下降到低于周围有效区域的顶表面的水平面，但留下FOX的顶部表面与活性区域相交的间隔物。

8. 发明授权

US06251777B1 Thermal annealing method for forming metal silicide layer 有权
标题翻译：用于形成金属硅化物层的热退火方法
公开(公告)号：US06251777B1
公开(公告)日：2001-06-26
申请号：US09261994
申请日：1999-03-05
申请人： Shwangming Jeng , Chen-Hua Yu
发明人： Shwangming Jeng , Chen-Hua Yu
IPC分类号： H01L2144
CPC分类号： H01L29/665 , H01L21/28052 , H01L21/28518 , H01L21/28525
摘要： A method for forming a metal silicide layer. There is first provided a substrate. There is then formed over the substrate a silicon layer, where the silicon layer has other than an amorphous silicon surface. There is then annealed thermally the silicon layer at a temperature greater than a silicidation temperature for forming a metal silicide layer upon the silicon layer to thus form from the silicon layer a thermally annealed silicon layer. Finally, there is then deposited upon the thermally annealed silicon layer a metal silicide forming metal while employing a metal deposition method such that upon contact with the thermally annealed silicon layer the metal silicide forming metal reacts in-situ to form a metal silicide layer upon a partially consumed thermally annealed silicon layer formed from the thermally annealed silicon layer.
摘要翻译：一种形成金属硅化物层的方法。首先提供基板。然后在衬底上形成硅层，其中硅层具有不同于非晶硅表面的硅层。然后在大于硅化温度的温度下对硅层进行热处理，以在硅层上形成金属硅化物层，从而从硅层形成热退火的硅层。最后，然后在采用金属沉积方法的同时，在热退火的硅层上沉积金属硅化物形成金属，使得当与热退火的硅层接触时，金属硅化物形成金属在原位反应以形成金属硅化物层由热退火的硅层形成的部分消耗热退火的硅层。

9. 发明授权

US6143673A Method for forming gap filling silicon oxide intermetal dielectric (IMD) layer formed employing ozone-tEOS 有权
标题翻译：用臭氧tEOS形成间隙填充氧化硅金属间电介质（IMD）层的方法
公开(公告)号：US6143673A
公开(公告)日：2000-11-07
申请号：US409888
申请日：1999-10-01
申请人： Syun-Ming Jang , Ying-Ho Chen , Shwangming Jeng , Chen-Hua Yu
发明人： Syun-Ming Jang , Ying-Ho Chen , Shwangming Jeng , Chen-Hua Yu
IPC分类号： H01L21/311 , H01L21/316 , H01L21/31
CPC分类号： H01L21/02164 , H01L21/022 , H01L21/02211 , H01L21/02271 , H01L21/02274 , H01L21/02315 , H01L21/31116 , H01L21/31612
摘要： A method for forming within a microelectronics fabrication a dielectric layer formed over, around and between patterned conductor layers. There is first provided a substrate employed within a microelectronics fabrication upon which is formed a patterned conductor layers. There is then formed over the patterned conductor layer a silicon oxide dielectric layer. There is then treated the silicon oxide dielectric layer to an anisotropic sputter etching process to remove silicon oxide dielectric material without re-deposition from the bottom of the gap between lines of the patterned conductor layer and to reform the silicon oxide dielectric layers on the sidewalls of the patterned lines to form spacer layers thereon. Both the silicon oxide dielectric layer deposition process and the sputter etching process may be repeated as desired to form the desired depth of trench and shape of spacer layer. There is then exposed the substrate to a nitrogen plasma. There is then formed over the substrate a gap filling silicon oxide dielectric layer to complete the formation of the inter-level dielectric layer with minimal void content in gaps between patterned lines.
摘要翻译：在微电子制造中形成在图案化导体层之上，周围和之间形成介电层的方法。首先提供在微电子制造中使用的衬底，其上形成图案化的导体层。然后在图案化的导体层上形成氧化硅介电层。然后将氧化硅介电层处理成各向异性溅射蚀刻工艺以去除氧化硅介电材料，而不从图案化导体层的线之间的间隙的底部重新沉积，并且重新形成在图案化导体层的侧壁上的氧化硅介电层图案化线以在其上形成间隔层。可以根据需要重复氧化硅介电层沉积工艺和溅射蚀刻工艺，以形成期望的沟槽深度和间隔层的形状。然后将基板暴露于氮等离子体。然后在衬底上形成填充氧化硅介电层的间隙，以在图案化线之间的间隙中以最小的空隙含量完成层间电介质层的形成。

10. 发明授权

US6121111A Method of removing tungsten near the wafer edge after CMP 有权
标题翻译：在CMP之后去除晶片边缘附近的钨的方法
公开(公告)号：US6121111A
公开(公告)日：2000-09-19
申请号：US234093
申请日：1999-01-19
申请人： Syun-Ming Jang , Chen-Hua Yu , Shwangming Jeng
发明人： Syun-Ming Jang , Chen-Hua Yu , Shwangming Jeng
IPC分类号： H01L21/321 , H01L21/3213 , H01L21/76 , G03C5/00 , H01L21/301 , H01L21/44 , H01L23/544
CPC分类号： H01L21/3212 , H01L21/32136 , H01L2223/54493
摘要： A method is described for removing residual metal, such as tungsten, from the edge region of a wafer. After tungsten is deposited on a wafer to fill via holes in a dielectric the wafer is planarized using Chemical Mechanical Polishing, CMP. The CMP does not remove the tungsten from the edge of the wafer. After conductor metals for a layer of conducting electrodes has been deposited a layer of photoresist is formed on the wafer and patterned to clear the metals from over the alignment marks. This photoresist is then removed from the edge region of the wafer. The residual metals are then etched away from the edge region of the wafer using the remaining photoresist as a mask during the same etching step used to remove metals from the alignment marks or during a separate etching step. In one embodiment the alignment marks and laser marks are relocated to the edge region of the wafer and the residual metals are etched away from the edge region of the wafer during the same etching step used to remove metals from the alignment marks and laser marks.
摘要翻译：描述了从晶片的边缘区域去除诸如钨的残留金属的方法。在钨沉积在晶片上以填充电介质中的孔之后，使用化学机械抛光CMP将晶片平坦化。 CMP不会从晶片的边缘去除钨。在已经沉积了导电电极层的导体金属之后，在晶片上形成了一层光致抗蚀剂并被图案化以从对准标记上方清除金属。然后将该光致抗蚀剂从晶片的边缘区域移除。然后，在用于从对准标记中移除金属或在单独的蚀刻步骤期间的相同蚀刻步骤期间，使用剩余的光致抗蚀剂作为掩模，将残余金属从晶片的边缘区域蚀刻掉。在一个实施例中，将对准标记和激光标记重新定位到晶片的边缘区域，并且在用于从对准标记和激光标记去除金属的相同蚀刻步骤期间，残留的金属被从晶片的边缘区域蚀刻掉。

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