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1. 发明授权

US06451701B1 Method for making low-resistance silicide contacts between closely spaced electrically conducting lines for field effect transistors 有权
标题翻译：用于场效应晶体管的紧密间隔的导电线之间制造低电阻硅化物接触的方法
公开(公告)号：US06451701B1
公开(公告)日：2002-09-17
申请号：US09993068
申请日：2001-11-14
申请人： Mei-Yun Wang , Shwangming Jeng , Shau-Lin Shue
发明人： Mei-Yun Wang , Shwangming Jeng , Shau-Lin Shue
IPC分类号： H01L21425
CPC分类号： H01L29/665 , H01L21/28518 , H01L21/31155
摘要： A method for making reliable low-resistance contacts between closely spaced FET gate electrodes having high-aspect-ratio spacings. Polysilicon gate electrodes are formed. A conformal insulating layer is deposited and anisotropically etched back to form sidewall spacers on the gate electrodes. During conventional etch-back, the etch rate of the insulating layer between the closely spaced gate electrodes is slower resulting in a residual oxide that prevents the formation of reliable low-resistance contacts. This residual oxide requires an overetch in a hydrofluoric acid solution prior to forming silicide contacts. The wet overetch results in device degradation. A nitrogen or germanium implant is used to amorphize the oxide and to increase the wet etch rate of the residual oxide. Using this amorphization the wet etch that is commonly used as a pre-clean prior to forming silicide contacts can be used to remove the residual silicon oxide without overetching. The implant also results in a smoother interface between the silicide and the silicon substrate, which results in lower sheet resistance.
摘要翻译：一种用于在具有高纵横比间隔的紧密间隔的FET栅电极之间进行可靠的低电阻接触的方法。形成多晶硅栅电极。沉积保形绝缘层并各向异性地回蚀以在栅电极上形成侧壁间隔物。在传统的回蚀期间，绝缘层在紧密间隔的栅电极之间的蚀刻速率较慢，导致残留的氧化物阻止形成可靠的低电阻触点。在形成硅化物接触之前，该残余氧化物需要在氢氟酸溶液中进行过蚀刻。湿过滤会导致设备退化。氮或锗植入物用于使氧化物非晶化并增加残余氧化物的湿蚀刻速率。使用这种非晶化，通常在形成硅化物接触之前通常用作预清洁的湿法蚀刻可以用于除去剩余的氧化硅而不进行过蚀刻。该植入物还导致硅化物和硅衬底之间更平滑的界面，这导致较低的薄层电阻。

2. 发明申请

US20070284678A1 Methods of Manufacturing Metal-Silicide Features 有权
标题翻译：制造金属硅化物特性的方法
公开(公告)号：US20070284678A1
公开(公告)日：2007-12-13
申请号：US11838376
申请日：2007-08-14
申请人： Chen-Tung Lin , Chih-Wei Chang , Chii-Ming Wu , Mei-Yun Wang , Chiang-Ming Chuang , Shau-Lin Shue
发明人： Chen-Tung Lin , Chih-Wei Chang , Chii-Ming Wu , Mei-Yun Wang , Chiang-Ming Chuang , Shau-Lin Shue
IPC分类号： H01L21/3205 , H01L29/45
CPC分类号： H01L29/66545 , H01L21/28061 , H01L21/28097 , H01L21/28525 , H01L21/76877 , H01L21/76889 , H01L23/485 , H01L2924/0002 , Y10S438/926 , H01L2924/00
摘要： A method of manufacturing a microelectronic device including forming a dielectric layer surrounding a dummy feature located over a substrate, removing the dummy feature to form an opening in the dielectric layer, and forming a metal-silicide layer conforming to the opening by a metal deposition process employing a target which includes metal and silicon. The metal-silicide layer may then be annealed.
摘要翻译：一种制造微电子器件的方法，包括形成围绕位于衬底上的虚拟特征的介电层，去除虚拟特征以在电介质层中形成开口，以及通过金属沉积工艺形成符合开口的金属硅化物层使用包括金属和硅的靶。然后可以将金属硅化物层退火。

3. 发明授权

US07282450B2 Sidewall coverage for copper damascene filling 有权
标题翻译：铜镶嵌填料的侧壁覆盖
公开(公告)号：US07282450B2
公开(公告)日：2007-10-16
申请号：US10733722
申请日：2003-12-11
申请人： Shau-Lin Shue , Mei-Yun Wang , Chen-Hua Yu
发明人： Shau-Lin Shue , Mei-Yun Wang , Chen-Hua Yu
IPC分类号： H01L21/44
CPC分类号： H01L21/76843 , H01L21/2855 , H01L21/76862 , H01L21/76865 , H01L21/76873 , H01L21/76874 , H01L2221/1089
摘要： A general process is described for filling a hole or trench at the surface of an integrated circuit without trapping voids within the filler material. A particular application is the filling of a trench with copper in order to form damascene wiring. First, a seed layer is deposited in the hole or trench by means of PVD. This is then followed by a sputter etching step which removes any overhang of this seed layer at the mouth of the trench or hole. A number of process variations are described including double etch/deposit steps, varying pressure and voltage in the same chamber to allow sputter etching and deposition to take place without breaking vacuum, and reduction of contact resistance between wiring levels by reducing via depth.
摘要翻译：描述了在集成电路的表面处填充孔或沟槽而不在填充材料内捕获空隙的一般方法。具体应用是用铜填充沟槽以形成镶嵌线。首先，通过PVD将种子层沉积在孔或沟槽中。然后进行溅射蚀刻步骤，其移除沟槽或孔口处的该种子层的任何突出端。描述了许多工艺变化，包括双重蚀刻/沉积步骤，在相同的室中改变压力和电压，以允许在不破坏真空的情况下进行溅射蚀刻和沉积，并且通过减小通孔深度来降低布线水平之间的接触电阻。

4. 发明授权

US07247915B2 Cobalt/nickel bi-layer silicide process for very narrow line polysilicon gate technology 有权
标题翻译：钴/镍双层硅化物工艺，用于非常窄的多晶硅栅极技术
公开(公告)号：US07247915B2
公开(公告)日：2007-07-24
申请号：US11375778
申请日：2006-03-15
申请人： Chih-Wei Chang , Mei-Yun Wang , Shau-Lin Shue , Mong-Song Liang
发明人： Chih-Wei Chang , Mei-Yun Wang , Shau-Lin Shue , Mong-Song Liang
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062
CPC分类号： H01L21/28518 , H01L29/4941 , H01L29/665 , H01L29/7833
摘要： A silicide method for integrated circuit and semiconductor device fabrication wherein a layer of nickel is formed over at least one silicon region of a substrate and a layer of cobalt is formed over the nickel layer. The cobalt/nickel bi-layer is then annealed to transform the bi-layer to a bi-silicide film having a cobalt-rich silicide portion and a nickel-rich silicide portion.
摘要翻译：一种用于集成电路和半导体器件制造的硅化物方法，其中在镍层上形成在衬底的至少一个硅区域上形成镍层并且形成钴层。然后退火钴/镍双层以将双层转变为具有富钴硅化物部分和富镍硅化物部分的双硅化物膜。

5. 发明申请

US20060157800A1 Cobalt/nickel bi-layer silicide process for very narrow line polysilicon gate technology 有权
标题翻译：钴/镍双层硅化物工艺，用于非常窄的多晶硅栅极技术
公开(公告)号：US20060157800A1
公开(公告)日：2006-07-20
申请号：US11375778
申请日：2006-03-15
申请人： Chih-Wei Chang , Mei-Yun Wang , Shau-Lin Shue , Mong-Song Liang
发明人： Chih-Wei Chang , Mei-Yun Wang , Shau-Lin Shue , Mong-Song Liang
IPC分类号： H01L29/40
CPC分类号： H01L21/28518 , H01L29/4941 , H01L29/665 , H01L29/7833
摘要： A silicide method for integrated circuit and semiconductor device fabrication wherein a layer of nickel is formed over at least one silicon region of a substrate and a layer of cobalt is formed over the nickel layer. The cobalt/nickel bi-layer is then annealed to transform the bi-layer to a bi-silicide film having a cobalt-rich silicide portion and a nickel-rich silicide portion.
摘要翻译：一种用于集成电路和半导体器件制造的硅化物方法，其中在镍层上形成在衬底的至少一个硅区域上形成镍层并且形成钴层。然后退火钴/镍双层以将双层转变为具有富钴硅化物部分和富镍硅化物部分的双硅化物膜。

6. 发明授权

US06242338B1 Method of passivating a metal line prior to deposition of a fluorinated silica glass layer 有权
标题翻译：在沉积氟化石英玻璃层之前钝化金属线的方法
公开(公告)号：US06242338B1
公开(公告)日：2001-06-05
申请号：US09422175
申请日：1999-10-22
申请人： Chung-Shi Liu , Shau-Lin Shue , Yao-yi Cheng , Chen-Hua Yu , Mei-Yun Wang
发明人： Chung-Shi Liu , Shau-Lin Shue , Yao-yi Cheng , Chen-Hua Yu , Mei-Yun Wang
IPC分类号： H01L214763
CPC分类号： H01L21/02131 , H01L21/02274 , H01L21/02304 , H01L21/31629 , H01L21/321 , H01L21/76832 , H01L21/76834 , H01L21/76888
摘要： A process of forming a thin, protective insulator layer, on the sides of metal interconnect structures, prior to the deposition of a halogen containing, low k dielectric layer, has been developed. The process features the growth of a thin metal nitride, or thin metal oxide layer, on the exposed sides of the metal interconnect structures, via a plasma treatment, performed in either a nitrogen containing, or in a water containing, ambient. The thin layer protects the metal interconnect structure from the corrosive, as well as delamination effects, created by the halogen, or halogen products, contained in overlying low k dielectric layers, such as fluorinated silica glass.
摘要翻译：已经开发了在沉积含卤素的低k电介质层之前在金属互连结构的侧面上形成薄的保护性绝缘体层的工艺。该方法的特征在于金属互连结构的暴露侧上通过等离子体处理在含氮或含水环境中进行的金属氮化物或薄金属氧化物层的生长。薄层保护金属互连结构免受由覆盖在低k电介质层（例如氟化石英玻璃）中的卤素或卤素产物产生的腐蚀性以及分层影响。

7. 发明授权

US07514348B2 Sidewall coverage for copper damascene filling 有权
标题翻译：铜镶嵌填料的侧壁覆盖
公开(公告)号：US07514348B2
公开(公告)日：2009-04-07
申请号：US11860639
申请日：2007-09-25
申请人： Shau-Lin Shue , Mei-Yun Wang , Chen-Hua Yu
发明人： Shau-Lin Shue , Mei-Yun Wang , Chen-Hua Yu
IPC分类号： H01L21/302
CPC分类号： H01L21/76843 , H01L21/2855 , H01L21/76862 , H01L21/76865 , H01L21/76873 , H01L21/76874 , H01L2221/1089
摘要： A general process is described for filling a hole or trench at the surface of an integrated circuit without trapping voids within the filler material. A particular application is the filling of a trench with copper in order to form damascene wiring. First, a seed layer is deposited in the hole or trench by means of PVD. This is then followed by a sputter etching step which removes any overhang of this seed layer at the mouth of the trench or hole. A number of process variations are described including double etch/deposit steps, varying pressure and voltage in the same chamber to allow sputter etching and deposition to take place without breaking vacuum, and reduction of contact resistance between wiring levels by reducing via depth.
摘要翻译：描述了在集成电路的表面处填充孔或沟槽而不在填充材料内捕获空隙的一般方法。具体应用是用铜填充沟槽以形成镶嵌线。首先，通过PVD将种子层沉积在孔或沟槽中。然后进行溅射蚀刻步骤，其移除沟槽或孔口处的该种子层的任何突出端。描述了许多工艺变化，包括双重蚀刻/沉积步骤，在相同的室中改变压力和电压，以允许在不破坏真空的情况下进行溅射蚀刻和沉积，并且通过减小通孔深度来降低布线水平之间的接触电阻。

8. 发明授权

US07205234B2 Method of forming metal silicide 有权
标题翻译：形成金属硅化物的方法
公开(公告)号：US07205234B2
公开(公告)日：2007-04-17
申请号：US10772938
申请日：2004-02-05
申请人： Chii-Ming Wu , Mei-Yun Wang , Chih-Wei Chang , Shau-Lin Shue
发明人： Chii-Ming Wu , Mei-Yun Wang , Chih-Wei Chang , Shau-Lin Shue
IPC分类号： H01L21/44
CPC分类号： H01L21/28052 , H01L21/28518 , H01L21/823835 , H01L29/665
摘要： A method of optimizing the formation of nickel silicide on regions of a MOSFET structure, has been developed. The method features formation of nickel silicide using an anneal procedure performed at a temperature below which nickel silicide instability and agglomeration occurs. A thin titanium interlayer is first formed on the MOSFET structure prior to nickel deposition, allowing an anneal procedure, performed after nickel deposition, to successfully form nickel silicide at a temperature of about 400° C. To obtain the desired conformality and thickness uniformity the thin titanium interlayer is formed via an atomic layer deposition procedure.
摘要翻译：已经开发了在MOSFET结构的区域上优化硅化镍的形成的方法。该方法的特征是使用在低于该温度的镍硅化物不稳定性和聚集发生的温度下进行的退火程序形成硅化镍。首先在镍沉积之前在MOSFET结构上形成薄的钛中间层，允许在镍沉积之后进行的退火程序在约400℃的温度下成功形成硅化镍。为了获得所需的共形性和厚度均匀性，薄的通过原子层沉积工艺形成钛夹层。

9. 发明申请

US20050272235A1 Method of forming silicided gate structure 失效
标题翻译：形成硅化栅结构的方法
公开(公告)号：US20050272235A1
公开(公告)日：2005-12-08
申请号：US10859730
申请日：2004-06-03
申请人： Chii-Ming Wu , Cheng-Tung Lin , Mei-Yun Wang , Chih-Wei Chang , Shau-Lin Shue
发明人： Chii-Ming Wu , Cheng-Tung Lin , Mei-Yun Wang , Chih-Wei Chang , Shau-Lin Shue
IPC分类号： H01L21/28 , H01L21/285 , H01L21/336 , H01L21/4763 , H01L29/49
CPC分类号： H01L21/28097 , H01L21/28518 , H01L29/4975 , H01L29/66507 , H01L29/785
摘要： A method of forming a silicided gate of a field effect transistor on a substrate having active regions is provided. The method includes the following steps: (a) forming a silicide in at least a first portion of a gate; (b) after step (a), depositing a metal over the active regions and said gate; and (c) annealing to cause the metal to react to form silicide in the active regions, wherein the thickness of said gate silicide is greater than the thickness of said silicide in said active regions.
摘要翻译：提供了在具有有源区的基板上形成场效应晶体管的硅化物栅的方法。该方法包括以下步骤：（a）在栅极的至少第一部分中形成硅化物; （b）在步骤（a）之后，在有源区域和所述栅极上沉积金属; 和（c）退火以引起金属反应以在有源区中形成硅化物，其中所述栅极硅化物的厚度大于所述有源区中所述硅化物的厚度。

10. 发明申请

US20050092598A1 Sputtering process with temperature control for salicide application 审中-公开
标题翻译：用于自杀剂应用的温度控制的溅射过程
公开(公告)号：US20050092598A1
公开(公告)日：2005-05-05
申请号：US10702970
申请日：2003-11-05
申请人： Mei-Yun Wang , Chih-Wei Chang , Chii-Ming Wu , Cheng-Tung Lin , Shau-Lin Shue
发明人： Mei-Yun Wang , Chih-Wei Chang , Chii-Ming Wu , Cheng-Tung Lin , Shau-Lin Shue
IPC分类号： C23C14/16 , H01L21/285 , C23C16/00 , C23C14/32
CPC分类号： H01L21/28518 , C23C14/16
摘要： A process for reducing the thermal budget and enhancing stability in the thermal budget of a metal salicide process used in the formation of metal salicides on substrates, thus eliminating or reducing salicide spiking and junction leakage in microelectronic devices fabricated on the substrates. According to a typical embodiment, a substrate is cooled to a sub-processing temperature which is lower than the metal deposition processing temperature and the salicide-forming metal is deposited onto the reduced-temperature substrate.
摘要翻译：一种用于降低热预算并增强用于在基材上形成金属硅化物的金属硅化物工艺的热预算中的稳定性的方法，从而消除或减少在衬底上制造的微电子器件中的自杀剂尖峰和结漏电。根据典型的实施方式，将基板冷却至比金属沉积处理温度低的副处理温度，并将形成自杀型化合物的金属沉积在还原温度基板上。

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