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1. 发明授权

US5654577A Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US5654577A
公开(公告)日：1997-08-05
申请号：US476761
申请日：1995-06-07
申请人： Masayuki Nakamura , Kazuyuki Miyazawa , Hidetoshi Iwai
发明人： Masayuki Nakamura , Kazuyuki Miyazawa , Hidetoshi Iwai
IPC分类号： H01L27/04 , G11C11/408 , H01L21/822 , H01L21/8238 , H01L27/092 , H01L27/10 , H01L27/105 , H01L27/108 , H01L29/76
CPC分类号： H01L27/105
摘要： A semiconductor integrated circuit device includes in a substrate a P-type well region containing a memory array section in which dynamic memory cells are arranged in a matrix. The P-type well region is fed with a back bias voltage whose absolute value is reduced so as to be the most suitable for the refresh characteristics. Also included is a P-well region wherein there are formed N-channel MOSFETs of a peripheral circuit this P-well region is fed with a back bias voltage whose absolute value is smaller than that of the potential fed to the P-type well of the memory array section, considering the high-speed operation. A P-type well section, wherein there is formed are N-channel MOSFETs of an input circuit or an output circuit connected with external terminals, is fed with a back bias voltage whose absolute value is made large considering an undershoot voltage. The P-type well region provided with the memory array section is fed with a requisite minimum back bias voltage. Accordingly, the P-type well region provided with the input circuit or the output circuit corresponding to the external terminals is fed with the back bias voltage to provide a measure of protection against undershoot, while the refresh characteristics are improved by reducing the leakage current between the source/drain region connected with a capacitor and the P-type well, to thereby raise the operation speed of the peripheral circuit can be raised.
摘要翻译：半导体集成电路器件在衬底中包括含有存储器阵列部分的P型阱区域，其中动态存储器单元被布置成矩阵。 P型阱区域馈送有绝对值减小的背偏置电压，以便最适合刷新特性。还包括P阱区，其中形成外围电路的N沟道MOSFET，该P阱区被馈送反馈偏压，其绝对值小于馈送到P型阱的电位的绝对值存储器阵列部分，考虑高速运行。其中形成有输入电路的N沟道MOSFET或与外部端子连接的输出电路的P型阱区，考虑到下冲电压，馈送绝对值较大的反向偏置电压。设置有存储器阵列部分的P型阱区域被馈送必需的最小反向偏置电压。因此，设置有与外部端子相对应的输入电路或输出电路的P型阱区域被馈送有反向偏置电压，以提供对下冲的保护措施，同时通过减小刷新特性来减小可以提高与电容器和P型阱连接的源极/漏极区域，从而提高外围电路的操作速度。

2. 发明授权

US06906971B2 Semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件
公开(公告)号：US06906971B2
公开(公告)日：2005-06-14
申请号：US10767078
申请日：2004-01-30
申请人： Masayuki Nakamura , Kazuyuki Miyazawa , Hidetoshi Iwai
发明人： Masayuki Nakamura , Kazuyuki Miyazawa , Hidetoshi Iwai
IPC分类号： H01L27/04 , G11C11/408 , H01L21/822 , H01L21/8238 , H01L27/092 , H01L27/10 , H01L27/105 , G11C7/00
CPC分类号： H01L27/105
摘要： A semiconductor IC device includes, in a substrate, a P-type well region having a dynamic memory array section and applied with a reduced back bias voltage suitable for refreshing. Also included is a P-well region where N-channel MOSFETs of a peripheral circuit are formed. This P-well region is applied with a back bias voltage of an absolute value smaller than that applied to the P-type well of the memory array section. A P-type well section, where there are formed N-channel MOSFETs of an input circuit or an output circuit connected with external terminals, is applied with a back bias voltage of an absolute value large enough to provide a measure of protection against undershoot, while the refresh characteristics are improved by reducing the leakage current between the source/drain region connected with a capacitor and the P-type well, to thereby raise the operation speed of the peripheral circuit.
摘要翻译：半导体IC器件在衬底中包括具有动态存储器阵列部分并且施加有适于刷新的减小的背偏压的P型阱区。还包括形成外围电路的N沟道MOSFET的P阱区。该P阱区域施加的绝对值的反偏压小于施加到存储器阵列部分的P型阱的绝对值。形成输入电路的N沟道MOSFET或与外部端子连接的输出电路的P型阱部分被施加绝对值足够大的背偏压以提供防止下冲的保护措施，同时通过减少与电容器连接的源极/漏极区域与P型阱之间的漏电流来改善刷新特性，从而提高外围电路的操作速度。

3. 发明授权

US6078084A Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US6078084A
公开(公告)日：2000-06-20
申请号：US823167
申请日：1997-03-25
申请人： Masayuki Nakamura , Kazuyuki Miyazawa , Hidetoshi Iwai
发明人： Masayuki Nakamura , Kazuyuki Miyazawa , Hidetoshi Iwai
IPC分类号： H01L27/04 , G11C11/408 , H01L21/822 , H01L21/8238 , H01L27/092 , H01L27/10 , H01L27/105 , H01L27/108
CPC分类号： H01L27/105
摘要： A semiconductor integrated circuit device includes in a P-type well region containing a memory substrate a array section in which dynamic memory cells are arranged in a matrix. The P-type well region is fed with a back bias voltage whose absolute value is reduced so as to be the most suitable for the refresh characteristics. Also included is a P-well region wherein there are formed N-channel MOSFETs of a peripheral circuit this P-well region is fed with a back bias voltage whose absolute value is smaller than that of the potential fed to the P-type well of the memory array section, considering the high-speed operation. A P-type well section, wherein there is formed are N-channel MOSFETs of an input circuit or an output circuit connected with external terminals, is fed with a back bias voltage whose absolute value is made large considering an undershoot voltage. The P-type well region provided with the memory array section is fed with a requisite minimum back bias voltage. Accordingly, the P-type well region provided with the input circuit or the output circuit corresponding to the external terminals is fed with the back bias voltage to provide a measure of protection against undershoot, while the refresh characteristics are improved by reducing the leakage current between the source/drain region connected with a capacitor and the P-type well, to thereby raise the operation speed of the peripheral circuit can be raised.
摘要翻译：半导体集成电路器件包括在包含存储器基板的P型阱区中，其中动态存储单元以矩阵形式布置在其中。 P型阱区域馈送有绝对值减小的背偏置电压，以便最适合刷新特性。还包括P阱区，其中形成外围电路的N沟道MOSFET，该P阱区被馈送反馈偏压，其绝对值小于馈送到P型阱的电位的绝对值存储器阵列部分，考虑高速运行。其中形成有输入电路的N沟道MOSFET或与外部端子连接的输出电路的P型阱区，考虑到下冲电压，馈送绝对值较大的反向偏置电压。设置有存储器阵列部分的P型阱区域被馈送必需的最小反向偏置电压。因此，设置有与外部端子相对应的输入电路或输出电路的P型阱区域被馈送有反向偏置电压，以提供对下冲的保护措施，同时通过减小刷新特性来减小可以提高与电容器和P型阱连接的源极/漏极区域，从而提高外围电路的操作速度。

4. 发明授权

US5217917A Semiconductor memory device with improved substrate arrangement to permit forming a plurality of different types of random access memory, and a testing method therefor 失效
标题翻译：具有改进的基板布置以允许形成多种不同类型的随机存取存储器的半导体存储器件及其测试方法
公开(公告)号：US5217917A
公开(公告)日：1993-06-08
申请号：US496280
申请日：1990-03-20
申请人： Yasushi Takahashi , Hidetoshi Iwai , Satoshi Oguchi , Hisashi Nakamura , Hiroyuki Uchiyama , Toshitugu Takemuma , Shigetoshi Sakomura , Kazuyuki Miyazawa , Masamichi Ishihara , Ryoichi Hori , Takeshi Kizaki , Yoshihisa Koyama , Haruo Ii , Masaya Muranaka , Hidetomo Aoyagi , Hiromi Matsuura
发明人： Yasushi Takahashi , Hidetoshi Iwai , Satoshi Oguchi , Hisashi Nakamura , Hiroyuki Uchiyama , Toshitugu Takemuma , Shigetoshi Sakomura , Kazuyuki Miyazawa , Masamichi Ishihara , Ryoichi Hori , Takeshi Kizaki , Yoshihisa Koyama , Haruo Ii , Masaya Muranaka , Hidetomo Aoyagi , Hiromi Matsuura
IPC分类号： G11C5/00 , G11C5/02 , G11C7/10 , G11C11/4074 , G11C11/408 , G11C11/4096 , G11C29/00 , G11C29/02 , G11C29/46 , G11C29/50
CPC分类号： G11C29/027 , G11C11/4074 , G11C11/4082 , G11C11/4096 , G11C29/02 , G11C29/46 , G11C29/50 , G11C29/50012 , G11C5/00 , G11C5/025 , G11C7/1045 , G11C11/401 , G11C2029/5006 , G11C29/78
摘要： A semiconductor memory device is provided which includes a substrate arrangement which is suitable for forming a large number of types of DRAMs having different package specifications, different bit structure and different operating modes. In conjunction with this, the bonding pads are arranged at optimum locations for accommodating the different package types. Various layout arrangements are also provided to minimize space and to improve access time. Additional features are provided, including improved output buffer circuitry, protection circuitry and testing methods to facilitate operation of the semiconductor memory device.
摘要翻译：提供了一种半导体存储器件，其包括适于形成具有不同封装规格，不同位结构和不同工作模式的大量类型的DRAM的衬底布置。结合这些，接合垫被布置在适于不同包装类型的最佳位置处。还提供了各种布局布置以最小化空间并改善访问时间。提供了额外的功能，包括改进的输出缓冲器电路，保护电路和测试方法以便于半导体存储器件的操作。

5. 发明授权

US5151772A Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US5151772A
公开(公告)日：1992-09-29
申请号：US616705
申请日：1990-11-20
申请人： Yasushi Takahashi , Hiromi Matsuura , Yoshihisa Koyama , Masaya Muranaka , Katsutaka Kimura , Kazuyuki Miyazawa , Masamichi Ishihara , Hidetoshi Iwai
发明人： Yasushi Takahashi , Hiromi Matsuura , Yoshihisa Koyama , Masaya Muranaka , Katsutaka Kimura , Kazuyuki Miyazawa , Masamichi Ishihara , Hidetoshi Iwai
IPC分类号： H01L23/522 , H01L27/108
CPC分类号： H01L23/5226 , H01L27/10805 , H01L2924/0002 , Y10S257/923
摘要： A semiconductor integrated circuit device is provided which includes a memory cell array located in a generally central area of a semiconductor substrate with peripheral circuits located at both ends of the semiconductor substrate. A wiring layer is also provided which couples the peripheral circuits to one another. This wiring layer is arranged to have a double-layer structure of first and second aluminum layers which are electrically coupled to one another.
摘要翻译：提供一种半导体集成电路器件，其包括位于半导体衬底的大致中心区域中的存储单元阵列，其具有位于半导体衬底两端的外围电路。还提供了将外围电路彼此耦合的布线层。该布线层被布置成具有彼此电耦合的第一和第二铝层的双层结构。

6. 发明授权

US5436483A Semiconductor integrated circuit device having a first MISFET of an output buffer circuit and a second MISFET of an internal circuit 失效
标题翻译：具有输出缓冲电路的第一MISFET和内部电路的第二MISFET的半导体集成电路器件
公开(公告)号：US5436483A
公开(公告)日：1995-07-25
申请号：US142965
申请日：1993-10-29
申请人： Hidetoshi Iwai , Kazumichi Mitsusada , Masamichi Ishihara , Tetsuro Matsumoto , Kazuyuki Miyazawa , Hisao Katto , Kousuke Okuyama
发明人： Hidetoshi Iwai , Kazumichi Mitsusada , Masamichi Ishihara , Tetsuro Matsumoto , Kazuyuki Miyazawa , Hisao Katto , Kousuke Okuyama
IPC分类号： H01L21/8238 , H01L21/8242 , H01L27/02 , H01L27/092 , H01L29/78 , H01L29/06
CPC分类号： H01L21/823864 , H01L27/0251 , H01L27/0266 , H01L27/0922 , H01L27/10873 , H01L29/78
摘要： Disclosed is a semiconductor device having an internal circuit protected by an electrostatic protective circuit, the internal circuit and electrostatic protective circuit being formed on the same semiconductor substrate. The internal circuit includes MIS elements and has a double-diffused drain structure, while the protective circuit has a single-diffused drain structure. The internal circuit can be, e.g., a DRAM, and the protective circuit can have diffused resistors and clamping MIS elements. The single-diffused drain structure can be formed in the protective circuit on the semiconductor substrate, while providing double-diffused drain structure in the internal circuit on the same substrate, by: (1) scanning the ion implanting apparatus to avoid ion implantation of the first ions into the region of the protective circuit, and/or (2) forming a photoresist film over the region of the protective circuit to prevent ion implanation of the first ions into the protective circuit region. As a further embodiment of the present invention, a semiconductor integrated circuit device is provided wherein the source and drain regions of an MOSFET in the internal circuit have lightly doped drain (LDD) structure in order to suppress the appearance of hot carriers, and the source and drain regions of an MOSFET in the input/output circuit have structure doped with phosphorus at a high impurity concentration, in order to enhance an electrostatic breakdown voltage.
摘要翻译：公开了具有被静电保护电路保护的内部电路的半导体器件，内部电路和静电保护电路形成在同一半导体衬底上。内部电路包括MIS元件，并具有双扩散漏极结构，而保护电路具有单扩散漏极结构。内部电路可以是例如DRAM，并且保护电路可以具有扩散电阻器和钳位MIS元件。单扩散漏极结构可以形成在半导体衬底上的保护电路中，同时通过以下步骤在同一衬底上的内部电路中提供双扩散漏极结构：（1）扫描离子注入装置以避免离子注入第一离子进入保护电路的区域，和/或（2）在保护电路的区域上形成光致抗蚀剂膜，以防止第一离子离子注入保护电路区域。作为本发明的另一实施例，提供了一种半导体集成电路器件，其中内部电路中的MOSFET的源极和漏极区域具有轻掺杂漏极（LDD）结构，以便抑制热载流子的出现，源极并且输入/输出电路中的MOSFET的漏极区域掺杂有高杂质浓度的磷的结构，以增强静电击穿电压。

7. 发明授权

US5426613A Semiconductor memory device with improved substrate arrangement to permit forming a plurality of different types of random access memory, and a testing method therefor 失效
标题翻译：具有改进的基板布置以允许形成多种不同类型的随机存取存储器的半导体存储器件及其测试方法
公开(公告)号：US5426613A
公开(公告)日：1995-06-20
申请号：US972907
申请日：1992-11-06
申请人： Yasushi Takahashi , Hidetoshi Iwai , Satoshi Oguchi , Hisashi Nakamura , Hiroyuki Uchiyama , Toshitugu Takekuma , Shigetoshi Sakomura , Kazuyuki Miyazawa , Masamichi Ishihara , Ryoichi Hori , Takeshi Kizaki , Yoshihisa Koyama , Haruo Ii , Masaya Muranaka , Hidetomo Aoyagi , Hiromi Matsuura
发明人： Yasushi Takahashi , Hidetoshi Iwai , Satoshi Oguchi , Hisashi Nakamura , Hiroyuki Uchiyama , Toshitugu Takekuma , Shigetoshi Sakomura , Kazuyuki Miyazawa , Masamichi Ishihara , Ryoichi Hori , Takeshi Kizaki , Yoshihisa Koyama , Haruo Ii , Masaya Muranaka , Hidetomo Aoyagi , Hiromi Matsuura
IPC分类号： G11C5/00 , G11C5/02 , G11C7/10 , G11C11/4074 , G11C11/408 , G11C11/4096 , G11C29/00 , G11C29/02 , G11C29/46 , G11C29/50 , G11C7/00 , G11C8/00
CPC分类号： G11C29/027 , G11C11/4074 , G11C11/4082 , G11C11/4096 , G11C29/02 , G11C29/46 , G11C29/50 , G11C29/50012 , G11C5/00 , G11C5/025 , G11C7/1045 , G11C11/401 , G11C2029/5006 , G11C29/78
摘要： A semiconductor memory device is provided which includes a substrate arrangement which is suitable for forming a large number of types of DRAMs having different package specifications, different bit structure and different operating modes. In conjunction with this, the bonding pads are arranged at optimum locations for accommodating the different package types. Various layout arrangements are also provided to minimize space and to improve access time. Additional features are provided, including improved output buffer circuitry, protection circuitry and testing methods to facilitate operation of the semiconductor memory device.
摘要翻译：提供了一种半导体存储器件，其包括适于形成具有不同封装规格，不同位结构和不同工作模式的大量类型的DRAM的衬底布置。结合这些，接合垫被布置在适于不同包装类型的最佳位置处。还提供了各种布局布置以最小化空间并改善访问时间。提供了额外的功能，包括改进的输出缓冲器电路，保护电路和测试方法以便于半导体存储器件的操作。

8. 发明授权

US5208782A Semiconductor integrated circuit device having a plurality of memory blocks and a lead on chip (LOC) arrangement 失效
标题翻译：具有多个存储块和片上芯片（LOC）布置的半导体集成电路器件
公开(公告)号：US5208782A
公开(公告)日：1993-05-04
申请号：US892708
申请日：1992-05-29
申请人： Toshiyuki Sakuta , Masamichi Ishihara , Kazuyuki Miyazawa , Masanori Tazunoki , Hidetoshi Iwai , Hisashi Nakamura , Yasushi Takahashi , Toshio Maeda , Hiromi Matsuura , Ryoichi Hori , Toshio Sasaki , Osamu Sakai , Hiroyuki Uchiyama , Eiji Miyamoto , Kazuyoshi Oshima , Yasuhiro Kasama
发明人： Toshiyuki Sakuta , Masamichi Ishihara , Kazuyuki Miyazawa , Masanori Tazunoki , Hidetoshi Iwai , Hisashi Nakamura , Yasushi Takahashi , Toshio Maeda , Hiromi Matsuura , Ryoichi Hori , Toshio Sasaki , Osamu Sakai , Hiroyuki Uchiyama , Eiji Miyamoto , Kazuyoshi Oshima , Yasuhiro Kasama
IPC分类号： G06F11/18 , G06F11/20 , G11C11/406 , G11C29/00 , H01L27/105 , H01L27/108
CPC分类号： G11C29/808 , G11C11/406 , G11C29/88 , H01L24/06 , H01L27/10805 , G06F11/1666 , G06F11/183 , H01L2224/4826 , H01L27/105 , H01L2924/13091 , H01L2924/14
摘要： A semiconductor integrated circuit memory structure is provided which uses macro-cellulated circuit blocks that can permit a very large storage capability (for example, on the order of 64 Mbits in a DRAM) on a single chip. To achieve, this, a plurality of macro-cellulated memory blocks can be provided, with each of the memory blocks including a memory array as well as additional circuitry such as address selection circuits and input/output circuits. Other peripheral circuits are provided on the chip which are common to the plurality of macro-cell memory blocks. The macro-cell memory blocks themselves can be formed in an array so that their combined storage capacity will form the large overall storage capacity of the chip. The combination of the macro-cell memory blocks and the common peripheral circuitry for controlling the memory blocks permits a faster and more efficient refreshing operation for a DRAM. This is enhanced by a LOC (Lead On Chip) arrangement used in conjunction with the memory blocks.
摘要翻译：提供了一种半导体集成电路存储器结构，其使用宏单元电路块，其可以在单个芯片上允许非常大的存储能力（例如，DRAM中的64Mbits）。为了实现这一点，可以提供多个宏单元存储器块，其中每个存储器块包括存储器阵列以及诸如地址选择电路和输入/输出电路的附加电路。在芯片上提供了多个宏单元存储块通用的其他外围电路。宏单元存储器块本身可以形成为阵列，使得它们的组合存储容量将形成芯片的大的总体存储容量。宏单元存储器块和用于控制存储器块的公共外围电路的组合允许DRAM的更快更有效的刷新操作。这通过与存储器块结合使用的LOC（片上芯片）布置来增强。

9. 发明授权

US5436484A Semiconductor integrated circuit device having input protective elements and internal circuits 失效
标题翻译：具有输入保护元件和内部电路的半导体集成电路器件
公开(公告)号：US5436484A
公开(公告)日：1995-07-25
申请号：US143151
申请日：1993-10-29
申请人： Hidetoshi Iwai , Kazumichi Mitsusada , Masamichi Ishihara , Tetsuro Matsumoto , Kazuyuki Miyazawa , Hisao Katto , Kousuke Okuyama
发明人： Hidetoshi Iwai , Kazumichi Mitsusada , Masamichi Ishihara , Tetsuro Matsumoto , Kazuyuki Miyazawa , Hisao Katto , Kousuke Okuyama
IPC分类号： H01L21/8238 , H01L21/8242 , H01L27/02 , H01L27/092 , H01L29/78 , H01L29/06
CPC分类号： H01L21/823864 , H01L27/0251 , H01L27/0266 , H01L27/0922 , H01L27/10873 , H01L29/78
摘要： Disclosed is a semiconductor device having an internal circuit protected by an electrostatic protective circuit, the internal circuit and electrostatic protective circuit being formed on the same semiconductor substrate. The internal circuit includes MIS elements and has a double-diffused drain structure, while the protective circuit has a single-diffused drain structure. The internal circuit can be, e.g., a DRAM, and the protective circuit can have diffused resistors and clamping MIS elements. The single-diffused drain structure can be formed in the protective circuit on the semiconductor substrate, while providing double-diffused drain structure in the internal circuit on the same substrate, by: (1) scanning the ion implanting apparatus to avoid ion implantation of the first ions into the region of the protective circuit, and/or (2) forming a photoresist film over the region of the protective circuit to prevent ion implanation of the first ions into the protective circuit region. As a further embodiment of the present invention, a semiconductor integrated circuit device is provided wherein the source and drain regions of an MOSFET in the internal circuit have lightly doped drain (LDD) structure in order to suppress the appearance of hot carriers, and the source and drain regions of an MOSFET in the input/output circuit have structure doped with phosphorus at a high impurity concentration, in order to enhance an electrostatic breakdown voltage.
摘要翻译：公开了具有被静电保护电路保护的内部电路的半导体器件，内部电路和静电保护电路形成在同一半导体衬底上。内部电路包括MIS元件，并具有双扩散漏极结构，而保护电路具有单扩散漏极结构。内部电路可以是例如DRAM，并且保护电路可以具有扩散电阻器和钳位MIS元件。单扩散漏极结构可以形成在半导体衬底上的保护电路中，同时通过以下步骤在同一衬底上的内部电路中提供双扩散漏极结构：（1）扫描离子注入装置以避免离子注入第一离子进入保护电路的区域，和/或（2）在保护电路的区域上形成光致抗蚀剂膜，以防止第一离子离子注入保护电路区域。作为本发明的另一实施例，提供了一种半导体集成电路器件，其中内部电路中的MOSFET的源极和漏极区域具有轻掺杂漏极（LDD）结构，以便抑制热载流子的出现，源极并且输入/输出电路中的MOSFET的漏极区域掺杂有高杂质浓度的磷的结构，以增强静电击穿电压。

10. 发明授权

US5276346A Semiconductor integrated circuit device having protective/output elements and internal circuits 失效
标题翻译：具有保护/输出元件和内部电路的半导体集成电路器件
公开(公告)号：US5276346A
公开(公告)日：1994-01-04
申请号：US815863
申请日：1992-01-02
申请人： Hidetoshi Iwai , Kazumichi Mitsusada , Masamichi Ishihara , Tetsuro Matsumoto , Kazuyuki Miyazawa , Hisao Katto , Kousuke Okuyama
发明人： Hidetoshi Iwai , Kazumichi Mitsusada , Masamichi Ishihara , Tetsuro Matsumoto , Kazuyuki Miyazawa , Hisao Katto , Kousuke Okuyama
IPC分类号： H01L21/8238 , H01L21/8242 , H01L27/02 , H01L27/092 , H01L29/78 , H01L29/06
CPC分类号： H01L21/823864 , H01L27/0251 , H01L27/0266 , H01L27/0922 , H01L27/10873 , H01L29/78
摘要： Disclosed is a semiconductor device having an internal circuit protected by an electrostatoc protective circuit, the internal circuit and electrostatic protective circuit being formed on the same semiconductor substrate. The internal circuit includes MIS elements and has a double-diffused drain structure, while the protective circuit has a single-diffused drain structure. The internal circuit can be, e.g., a DRAM, and the protective circuit can have diffused resistors and clamping MIS elements. The single-diffused drain structure can be formed in the protective circuit on the semiconductor substrate, while providing double-diffused drain structure in the internal circuit on the same substrate, by: (1) scanning the ion implanting apparatus to avoid ion implantation of the first ions into the region of the protective circuit, and/or (2) forming a photoresist film over the region of the protective circuit to prevent ion implanation of the first ions into the protective circuit region. As a further embodiment of the present invention, a semiconductor integrated circuit device is provided wherein the source and drain regions of an MOSFET in the internal circuit have lightly doped drain (LDD) structure in order to suppress the appearance of hot carriers, and the source and drain regions of an MOSFET in the input/output circuit have structure doped with phosphorus at a high impurity concentration, in order to enhance an electrostatic breakdown voltage.
摘要翻译：本发明公开了一种半导体器件，其具有由静电场保护电路保护的内部电路，内部电路和静电保护电路形成在同一半导体衬底上。内部电路包括MIS元件，并具有双扩散漏极结构，而保护电路具有单扩散漏极结构。内部电路可以是例如DRAM，并且保护电路可以具有扩散电阻器和钳位MIS元件。单扩散漏极结构可以形成在半导体衬底上的保护电路中，同时通过以下步骤在同一衬底上的内部电路中提供双扩散漏极结构：（1）扫描离子注入装置以避免离子注入第一离子进入保护电路的区域，和/或（2）在保护电路的区域上形成光致抗蚀剂膜，以防止第一离子离子注入保护电路区域。作为本发明的另一个实施例，提供一种半导体集成电路器件，其中内部电路中的MOSFET的源极和漏极区域具有轻掺杂漏极（LDD）结构，以便抑制热载流子的出现，源极并且输入/输出电路中的MOSFET的漏极区域掺杂有高杂质浓度的磷的结构，以增强静电击穿电压。

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