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1. 发明授权

US6104626A Analog value memory circuit 失效
标题翻译：模拟值存储电路
公开(公告)号：US6104626A
公开(公告)日：2000-08-15
申请号：US808866
申请日：1997-02-28
申请人： Masayuki Katakura , Masashi Takeda
发明人： Masayuki Katakura , Masashi Takeda
IPC分类号： G11C7/22 , G11C27/04 , G11C27/00
CPC分类号： G11C7/222 , G11C27/04 , G11C7/22
摘要： An analog delay circuit which includes an analog memory circuit wherein a plurality of memory cells each including a memory capacitor and a selection switch for the memory capacitor are arranged in a matrix includes row switches provided for the individual columns for individually being driven by row selection signals. A same clock signal from a clock generation circuit is supplied commonly to an X direction scanning circuit and a Y direction scanning circuit. The number of stages of registers of the X direction scanning circuit and the number of stages of registers of the Y direction scanning circuit are set so that they have no common divisor other than 1 Consequently, when the memory cells are to be selectively scanned, a same selection condition can be provided to all of the memory cells without relying upon the positions of the memory cells, and the parasitic capacitance connected to a signal write/read terminal is reduced.
摘要翻译：一种包括模拟存储电路的模拟延迟电路，其中包括存储电容器和用于存储电容器的选择开关的多个存储单元被布置成矩阵，包括为各个列提供的行开关，用于单独由行选择信号驱动。来自时钟发生电路的相同时钟信号被共同地提供给X方向扫描电路和Y方向扫描电路。 X方向扫描电路的寄存器的级数和Y方向扫描电路的寄存器的级数被设置为使得它们除了1之外没有公共除数。因此，当要选择性地扫描存储器单元时，可以在不依赖于存储单元的位置的情况下，向所有存储单元提供相同的选择条件，并且减少连接到信号写入/读取端子的寄生电容。

2. 发明授权

US5999462A Clock generation circuit for analog value memory circuit 失效
标题翻译：模拟值存储电路的时钟发生电路
公开(公告)号：US5999462A
公开(公告)日：1999-12-07
申请号：US205200
申请日：1998-12-04
申请人： Masayuki Katakura , Masashi Takeda
发明人： Masayuki Katakura , Masashi Takeda
IPC分类号： G11C7/22 , G11C27/04 , G11C7/00
CPC分类号： G11C7/222 , G11C27/04 , G11C7/22
摘要： An analog delay circuit which includes an analog memory circuit wherein a plurality of memory cells each including a memory capacitor and a selection switch for the memory capacitor are arranged in a matrix includes row switches provided for the individual columns for individually being driven by row selection signals. A same clock signal from a clock generation circuit is supplied commonly to an X direction scanning circuit and a Y direction scanning circuit. The number of stages of registers of the X direction scanning circuit and the number of stages of registers of the Y direction scanning circuit are set so that they have no common divisor other than 1. Consequently, when the memory cells are to be selectively scanned, a same selection condition can be provided to all of the memory cells without relying upon the positions of the memory cells, and the parasitic capacitance connected to a signal write/read terminal is reduced.
摘要翻译：一种包括模拟存储电路的模拟延迟电路，其中包括存储电容器和用于存储电容器的选择开关的多个存储单元被布置成矩阵，包括为各个列提供的行开关，用于单独由行选择信号驱动。来自时钟发生电路的相同时钟信号被共同地提供给X方向扫描电路和Y方向扫描电路。将X方向扫描电路的寄存器的级数和Y方向扫描电路的寄存器的级数设置为除了1以外没有公共除数。因此，当要选择性地扫描存储器单元时，可以在不依赖于存储单元的位置的情况下向所有存储单元提供相同的选择条件，并且减少连接到信号写/读终端的寄生电容。

3. 发明授权

US4739304A Digital-to-analog converting system 失效
标题翻译：数模转换系统
公开(公告)号：US4739304A
公开(公告)日：1988-04-19
申请号：US917308
申请日：1986-10-10
申请人： Masashi Takeda , Ikuro Hata , Masayuki Katakura , Norio Shoji
发明人： Masashi Takeda , Ikuro Hata , Masayuki Katakura , Norio Shoji
IPC分类号： H03M1/00 , H03M1/68 , H03M1/82
CPC分类号： H03M1/68 , H03M1/745 , H03M1/822
摘要： A digital-to-analog convertor divides an input digital signal into a least significant bit group and a most significant bit group. The most significant bit group is converted using pulse amplitude modulation and the least significant bit group is converted using pulse width modulation, in which the pulse widths are varied symmetrically about predetermined time points within a conversion period in order to improve the linearity of the pulse width modulation conversion.
摘要翻译：数模转换器将输入数字信号分为最低有效位组和最高有效位组。使用脉冲幅度调制转换最高有效位组，并且使用脉冲宽度调制转换最低有效位组，其中脉冲宽度在转换周期内关于预定时间点对称地改变，以便提高脉冲宽度的线性调制转换。

4. 发明授权

US07631030B2 Sine wave multiplication circuit and sine wave multiplication method 失效
标题翻译：正弦波乘法电路和正弦波乘法法
公开(公告)号：US07631030B2
公开(公告)日：2009-12-08
申请号：US11049784
申请日：2005-02-03
申请人： Masayuki Katakura
发明人： Masayuki Katakura
IPC分类号： G06G7/16
CPC分类号： G06G7/16 , H03B19/00 , H03D7/1458 , H03D7/1466 , H03D7/1483 , H03D2200/0086
摘要： A sine wave multiplication circuit multiplies an analog input signal by n (n is an integer equal to or greater than 2) weighting coefficients each having a unique value. The polarity of the analog input signal multiplied by one of the n weighting coefficients is changed over. Further, changeover among the n weighting coefficients and of the polarity is performed after every sampling period equal to ½k (k is an integer, and 2k is equal to or greater than 6 but equal to or smaller than 4n) of one period of the sine wave signal by which the analog input signal is multiplied. As a result, a staircase waveform having 2n positive and negative stairs is generated while unnecessary harmonic wave components in the proximity of the sine wave signal by which the analog input signal is multiplied can be reduced.
摘要翻译：正弦波乘法电路将模拟输入信号乘以每个具有唯一值的n（n是等于或大于2的整数）加权系数。模拟输入信号乘以n个加权系数中的一个的极性被改变。此外，n个加权系数和极性之间的切换在正弦的一个周期的等于½k（k是整数，2k等于或大于6但等于或小于4n）的每个采样周期之后执行波信号，模拟输入信号通过该信号相乘。结果，产生具有2n个正和负楼梯的阶梯波形，同时可以减少模拟输入信号相乘的正弦波信号附近的不必要的谐波分量。

5. 发明授权

US07522691B2 Phase-locked circuit 有权
标题翻译：锁相电路
公开(公告)号：US07522691B2
公开(公告)日：2009-04-21
申请号：US11137642
申请日：2005-05-26
申请人： Masayuki Katakura
发明人： Masayuki Katakura
IPC分类号： H03D3/24
CPC分类号： H03C3/0966 , H03L7/07 , H03L7/085 , H03L7/087
摘要： A phase-locked circuit comprises a complex signal processor and a feedback portion wherein the complex signal processor: receives as an input a first complex signal composed of a real part component and an imaginary part component; generates a second complex signal composed of a first signal component and a second signal component and having a second frequency in accordance with a feedback control signal input from the feedback portion; and generates a signal in accordance with a declination of a third complex signal obtained by multiplying the first complex signal with the second complex signal and outputs to the feedback portion. The feedback portion generates the feedback control signal in accordance with a signal input from the complex signal processor, so that the declination converges to a constant value; and the complex signal processor synchronizes a phase of the second complex signal with the first complex signal and outputs.
摘要翻译：锁相电路包括复信号处理器和反馈部分，其中复信号处理器：接收由实部分量和虚部分量组成的第一复信号作为输入; 产生由第一信号分量和第二信号分量组成的具有根据从反馈部分输入的反馈控制信号的第二频率的第二复信号; 并且根据通过将第一复数信号与第二复数信号相乘而获得的第三复数信号的偏角产生信号，并将其输出到反馈部分。反馈部分根据从复信号处理器输入的信号产生反馈控制信号，使得偏角收敛到恒定值; 并且所述复信号处理器将所述第二复信号的相位与所述第一复信号同步并输出。

6. 发明申请

US20080143439A1 Fully-differential amplifier 有权
标题翻译：全差分放大器
公开(公告)号：US20080143439A1
公开(公告)日：2008-06-19
申请号：US11812378
申请日：2007-06-18
申请人： Hiroshi Tanimoto , Masayuki Katakura
发明人： Hiroshi Tanimoto , Masayuki Katakura
IPC分类号： H03F3/45
CPC分类号： H03F3/45183 , H03F3/45475 , H03F3/45659 , H03F3/45748 , H03F3/45757 , H03F3/45973 , H03F3/45982 , H03F2200/513 , H03F2203/45082 , H03F2203/45088 , H03F2203/45134 , H03F2203/45212 , H03F2203/45526 , H03F2203/45644
摘要： A fully-differential amplifier able to operate at a low power supply voltage and provided with a common-mode signal suppression function is disclosed. This fully-differential amplifier is provided with a first fully-differential amplifier configured by a single-stage configuration inverting amplifier and canceling out the common-mode signal of the input side by a feedforward means and a second fully-differential amplifier configured by a single-stage configuration inverting amplifier and canceling out the common-mode signal of the output side by a feedback means, the output of the first fully-differential amplifier being connected to the input of the second fully-differential amplifier.
摘要翻译：公开了能够在低电源电压下工作并提供共模信号抑制功能的全差分放大器。该全差分放大器配备有由单级配置反相放大器配置的第一全差分放大器，并且由前馈装置消除输入侧的共模信号，并且由单个配置反相放大器配置的第二全差分放大器级配置反相放大器，并通过反馈装置消除输出侧的共模信号，第一全差分放大器的输出连接到第二全差分放大器的输入端。

7. 发明授权

US06873830B2 Bias circuit and radio communication apparatus using same 失效
标题翻译：偏置电路和使用它的无线电通信装置
公开(公告)号：US06873830B2
公开(公告)日：2005-03-29
申请号：US09852273
申请日：2001-05-10
申请人： Masayuki Katakura , Hideshi Motoyama
发明人： Masayuki Katakura , Hideshi Motoyama
IPC分类号： H03F1/30 , H03F3/193 , H04B1/04
CPC分类号： H03F1/306 , H03F2200/372
摘要： A bias circuit according to the present invention includes a monitoring circuit having a second FET and a resistance connected to a drain of the second FET for monitoring a drain current of a first FET to be supplied with a gate bias; a differential circuit including a third FET having a gate supplied with a reference voltage, a fourth FET having a gate connected to the drain of the second FET, sources of the third FET and the fourth FET being connected to a common point, and resistances connected to drains of the third FET and the fourth FET, respectively; and a fifth FET having a drain connected to the common source of the third FET and the fourth FET; wherein a drain voltage of the third FET is fed back to gates of the first FET and the second FET, and a drain voltage of the fourth FET is fed back to a gate of the fifth FET.
摘要翻译：根据本发明的偏置电路包括具有第二FET的监控电路和连接到第二FET的漏极的电阻，用于监视要被提供栅极偏压的第一FET的漏极电流; 包括具有提供有参考电压的栅极的第三FET的差分电路，具有连接到第二FET的漏极的栅极的第四FET，第三FET和第四FET的源极连接到公共点，并且电阻连接分别连接到第三FET和第四FET的漏极; 以及第五FET，其漏极连接到第三FET和第四FET的公共源; 其中所述第三FET的漏极电压被反馈到所述第一FET和所述第二FET的栅极，并且所述第四FET的漏极电压被反馈到所述第五FET的栅极。

8. 发明授权

US5625321A Variable gain amplifier apparatus 失效
标题翻译：可变增益放大器装置
公开(公告)号：US5625321A
公开(公告)日：1997-04-29
申请号：US547120
申请日：1995-10-23
申请人： Kazuji Sasaki , Masayuki Katakura , Kazuyuki Saijo
发明人： Kazuji Sasaki , Masayuki Katakura , Kazuyuki Saijo
IPC分类号： H03G3/20 , H03F3/62 , H03G3/30 , H04B1/16 , H03F3/68
CPC分类号： H03F3/62 , H03G3/3052
摘要： In a variable gain amplifier apparatus, wide input dynamic range can be secured and low noise characteristic can be obtained by employing first and second variable gain amplifiers have different noise characteristics and different saturation input levels and receive a same input signal. Output signals of the first and second variable gain amplifiers are added to each other to provide an output signal of the variable gain amplifier apparatus. Desired noise characteristic and saturation input level characteristic of the variable gain amplifier apparatus can be obtained by selecting the noise characteristics and the saturation input levels of the first and second variable gain amplifiers appropriately. This allows the variable gain amplifier apparatus to have a wide input dynamic range and low noise characteristic.
摘要翻译：在可变增益放大器装置中，通过采用具有不同噪声特性和不同饱和输入电平的第一和第二可变增益放大器，并且接收相同的输入信号，可以确保宽的输入动态范围并且可以获得低噪声特性。将第一和第二可变增益放大器的输出信号彼此相加以提供可变增益放大器装置的输出信号。可以通过适当地选择第一和第二可变增益放大器的噪声特性和饱和输入电平来获得可变增益放大器装置的期望噪声特性和饱和输入电平特性。这允许可变增益放大器装置具有宽的输入动态范围和低噪声特性。

9. 发明授权

US4084129A Voltage controlled variable gain circuit 失效
标题翻译：电压可变增益电路
公开(公告)号：US4084129A
公开(公告)日：1978-04-11
申请号：US768366
申请日：1977-02-14
申请人： Masayuki Katakura
发明人： Masayuki Katakura
IPC分类号： H03G1/00 , H03G7/00 , H03G3/30
CPC分类号： H03G7/004 , H03G1/0017 , H03G1/0035 , H03G7/002
摘要： A voltage controlled variable gain circuit comprising: first, second, third and fourth same polarity transistors for dividing the output current of a first operational amplifier by dc gain control voltage and being connected with the output terminal of the first operational amplifier to which an input signal is applied; means for driving in inverse phase the respective pairs of a first and third transistors, and a second and fourth transistors; a first feedback circuit including a second operational amplifier with an inverting input terminal connected with the output terminal of the first transistor, a first resistor element and a first PN junction element connected in series between the input and output terminals of the second operational amplifier, and a second resistor element and a second PN junction element connected in series between the output of the second operational amplifier and the input terminal of the first operational amplifier, so as to negatively feedback the output current of the first transistor to the input terminal of the first operational amplifier: a second feedback circuit for negatively feeding back the output current of the second transistor to the input terminal of the first operational amplifier; and summing device for summing the output current of the third transistor inversed and the output current of the fourth transistor.
摘要翻译：一种压控可变增益电路，包括：第一，第二，第三和第四相同极性晶体管，用于将第一运算放大器的输出电流除以直流增益控制电压，并与第一运算放大器的输出端连接，输入信号被申请;被应用; 用于以相反方向驱动第一和第三晶体管以及第二和第四晶体管的各对的装置; 第一反馈电路，包括具有与第一晶体管的输出端连接的反相输入端的第二运算放大器，串联连接在第二运算放大器的输入和输出端之间的第一电阻元件和第一PN结元件，以及第二电阻元件和第二PN结元件串联连接在第二运算放大器的输出端和第一运算放大器的输入端之间，从而将第一晶体管的输出电流负反馈到第一运算放大器的输入端运算放大器：用于将第二晶体管的输出电流负反馈到第一运算放大器的输入端的第二反馈电路; 以及用于将第三晶体管的输出电流反相和第四晶体管的输出电流相加的求和装置。

10. 发明申请

US20060132338A1 Angle detection signal processing apparatus 有权
标题翻译：角度检测信号处理装置
公开(公告)号：US20060132338A1
公开(公告)日：2006-06-22
申请号：US11205079
申请日：2005-08-17
申请人： Masayuki Katakura , Asako Toda , Yuichi Takagi , Hiroshi Kushihara
发明人： Masayuki Katakura , Asako Toda , Yuichi Takagi , Hiroshi Kushihara
IPC分类号： H03M1/48
CPC分类号： G01D5/244 , H03M1/485
摘要： A resolver use angle detection IC subjected to a phase lock operation so as to follow not an angle θ(t) for detection, but a phase angle ωot±θ(t) having an offset of a frequency ωot in the phase lock units. For this reason, when the excitation frequency ωot is set sufficiently high with respect to the frequency of the angle θ(t), the phase angle ωot±θ to be followed in the phase lock units will not become zero. For this reason, an angle having a high precision can be found in real time regardless of the configuration not including the conventional apparatus in which the configuration is complex and the power consumption is large like a bipolar VCO and an up/down type counter.
摘要翻译：旋转变压器使用经受相位锁定操作的角度检测IC，以便不跟踪用于检测的角度θ（t），而是在相位锁定单元中具有ωω的频率偏移的相位角ωoot±θ（t）。因此，当相对于角度θ（t）的频率将激发频率ωoot设定得足够高时，相位锁定单元中要遵循的相位角ωoot±θ将不会变为零。由于这个原因，可以实时地发现具有高精度的角度，而不管不是像双极型VCO和上/下型计数器那样的配置复杂并且功耗大的常规装置的配置。

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