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1. 发明授权

US06614304B2 Variable gain circuit having external controls and a low supply voltage 有权
标题翻译：具有外部控制和低电源电压的可变增益电路
公开(公告)号：US06614304B2
公开(公告)日：2003-09-02
申请号：US10035241
申请日：2002-01-04
申请人： Norio Shoji , Tatsuya Shirakawa
发明人： Norio Shoji , Tatsuya Shirakawa
IPC分类号： H03F345
CPC分类号： H03G1/0023 , H03F3/45098 , H03F3/45103 , H03F2203/45466 , H03F2203/45471 , H03F2203/45472 , H03F2203/45702
摘要： The present invention relates to a variable gain circuit including: a first transistor and a second transistor each having a control electrode connected to a circuit input terminal; a load connected between a first power supply and a first electrode of at least one of the first transistor and the second transistor; a third transistor and a fourth transistor having second electrodes connected to the first transistor and the second transistor, respectively, and each having a first electrode and a control electrode connected to each other; a first variable current source connected between a second power supply and the second electrodes of the first transistor and the third transistor and having a current value variable according to an external control signal; a second variable current source connected between the second power supply and the second electrodes of the second transistor and the fourth transistor and having a current value variable according to the control signal; a current source connected between the first power supply and a node of the first electrodes and the control electrodes of the third transistor and the fourth transistor; and an impedance component having one end connected to the first electrodes and the control electrodes of the third transistor and the fourth transistor.
摘要翻译：本发明涉及一种可变增益电路，包括：第一晶体管和第二晶体管，每个具有连接到电路输入端的控制电极; 连接在所述第一晶体管和所述第二晶体管中的至少一个的第一电源和第一电极之间的负载; 第三晶体管和第四晶体管，其具有分别连接到第一晶体管和第二晶体管的第二电极，并且每个具有彼此连接的第一电极和控制电极; 连接在第二电源和第一晶体管和第三晶体管的第二电极之间并具有根据外部控制信号而变化的电流值的第一可变电流源; 第二可变电流源，连接在第二电源和第二晶体管的第二电极和第四晶体管之间，并具有根据控制信号而变化的电流值; 连接在第一电源和第一电极的节点与第三晶体管和第四晶体管的控制电极之间的电流源; 以及阻抗分量，其一端连接到第三晶体管和第四晶体管的第一电极和控制电极。

2. 发明授权

US5926936A Method for applying corrosion-protective coating to joint between corrosion-protectively coated steel pipes 失效
标题翻译：在防腐涂层钢管之间对接头施加防腐蚀涂层的方法
公开(公告)号：US5926936A
公开(公告)日：1999-07-27
申请号：US728969
申请日：1996-10-11
申请人： Ryouichi Ikeda , Minoru Komura , Yoshihiro Okano , Norio Shoji , Toshiyuki Namioka , Akio Kida , Kiyotaka Hirahara
发明人： Ryouichi Ikeda , Minoru Komura , Yoshihiro Okano , Norio Shoji , Toshiyuki Namioka , Akio Kida , Kiyotaka Hirahara
IPC分类号： F16L58/10 , B29C63/00 , B29C63/42 , B29C65/00 , B29C65/34 , B29C65/66 , F16L58/18 , B23P17/00
CPC分类号： B29C65/66 , B29C63/0047 , B29C63/42 , B29C65/3428 , B29C66/001 , B29C66/1122 , B29C66/5221 , B29C66/73715 , F16L58/18 , F16L58/181 , B29C2791/006 , B29C65/3468 , B29C65/3476 , B29C66/71 , Y10T29/49888
摘要： In a joint between welded end portions of corrosion-protectively coated steel pipes, a heat-shrinkable tube is positioned so as to cover the outer circumference of a welded portion and the outer circumferences of its adjacent portions, and the heat-shrinkable tube is thermally shrunk in a state in which a gap between the heat-shrinkable tube and the aforementioned portions is kept in a vacuum so that the aforementioned portions are corrosion-protectively coated with the heat-shrinkable outer layer of the heat-shrinkable tube thus thermally shrunk.
摘要翻译：在防腐蚀涂层钢管的焊接端部之间的接头中，热收缩管被定位成覆盖焊接部分的外周和其相邻部分的外周，并且热收缩管是热的在将热收缩管与上述部分之间的间隙保持在真空状态的状态下收缩，使得上述部分被热收缩管的热收缩外层防腐蚀涂覆，从而热收缩。

3. 发明授权

US5898328A PLL circuit having a switched charge pump for charging a loop filter up or down and signal processing apparatus using the same 失效
标题翻译： PLL电路具有用于向上或向下充电环路滤波器的开关电荷泵和使用该电路的信号处理装置
公开(公告)号：US5898328A
公开(公告)日：1999-04-27
申请号：US835988
申请日：1997-04-10
申请人： Norio Shoji
发明人： Norio Shoji
IPC分类号： H03L7/093 , H03L7/08 , H03L7/089 , H03K5/00 , H03L7/00
CPC分类号： H03L7/0891
摘要： The invention provides a PLL circuit which can form a phase difference between input and output signals with a high degree of accuracy without employing a current source for a very weak current and eliminates dependency of the phase difference upon the input signal frequency. In the PLL circuit, phase difference forming current is added within a term of a fixed period to a selected one of charge-up current and charge-down current, selected by a phase comparison circuit, of a charge pump circuit, which charges up or charges down a loop filter under the control of an output signal of a phase comparison circuit, to form a phase difference between input and output signals of the PLL circuit which are to be compared in phase by the phase comparison circuit. The magnitude of the phase difference depends upon and is controlled by a term within which the phase difference forming current.
摘要翻译：本发明提供了一种PLL电路，其可以以高精度形成输入和输出信号之间的相位差，而不需要用于非常弱的电流的电流源，并消除相位差对输入信号频率的依赖性。在PLL电路中，相位差形成电流在固定周期的期限内相加到电荷泵电路所选择的充电电流和相位比较电路选择的选择的一个充电电流和充电电流，在相位比较电路的输出信号的控制下对环路滤波器进行充电，以便通过相位比较电路在相位上形成PLL电路的输入和输出信号之间的相位差。相位差的大小取决于并由相位差形成电流的项控制。

4. 发明授权

US4843303A Voltage regulator circuit 失效
标题翻译：稳压电路
公开(公告)号：US4843303A
公开(公告)日：1989-06-27
申请号：US216148
申请日：1988-07-07
申请人： Norio Shoji
发明人： Norio Shoji
IPC分类号： H03F1/30 , G05F3/16 , G05F3/22
CPC分类号： G05F3/222
摘要： A voltage regulator circuit arranged such that a constant current source through which a current of an integral multiple of a current from a reference current source is connected to a collector-emitter path of a transistor in series so that it is possible to suppress a base-emitter voltage of the transistor from being fluctated due to the scattering of the base impurity concentration in the transistor during the manufacturing process.
摘要翻译：一种电压调节器电路，其布置成使得来自参考电流源的电流的整数倍的电流通过该恒定电流源串联连接到晶体管的集电极 - 发射极路径，使得可以抑制基极 - 晶体管的发射极电压在制造过程中由于晶体管中的基极杂质浓度的散射而波动。

5. 发明授权

US4714841A Double-sided logic input differential switch 失效
标题翻译：双面逻辑输入差分开关
公开(公告)号：US4714841A
公开(公告)日：1987-12-22
申请号：US748596
申请日：1985-06-25
申请人： Norio Shoji , Masashi Takeda
发明人： Norio Shoji , Masashi Takeda
IPC分类号： H03K3/286 , H03K3/2885 , H03K19/086 , H03K17/60 , H03K19/003 , H03K19/092
CPC分类号： H03K3/2885 , H03K19/086
摘要： A logic circuit adapted for fabrication as an integrated circuit is formed having a differential amplifier operating with a constant current source and an appropriate voltage source, and having output transistors to provide the necessary output voltages, does not require a reference voltage input to the differential amplifier, thus, reference voltage transistors are not required. The two binary input signals are selected to have the same amplitude difference between the high and low levels thereof and one of the two input signals is shifted relative to the other one by the amount substantially equal to 1/2 the selected amplitude difference, and the output signals are similarly level shifted. Using this basic logic circuit as a building block other, more complex, logic circuits can be obtained.
摘要翻译：适用于作为集成电路制造的逻辑电路形成为具有用恒定电流源和适当电压源工作的差分放大器，并且具有输出晶体管以提供必要的输出电压，不需要将参考电压输入到差分放大器因此，不需要参考电压晶体管。选择两个二进制输入信号在其高电平和低电平之间具有相同的幅度差，并且两个输入信号中的一个相对于另一个输入信号相移大约等于所选择的幅度差的1/2，输出信号类似地电平移位。使用该基本逻辑电路作为构建块，可以获得更复杂的逻辑电路。

6. 发明授权

US06683740B1 Architecture for a hard disk drive write amplifier circuit with damping control 失效
标题翻译：具有阻尼控制的硬盘驱动器写放大器电路架构
公开(公告)号：US06683740B1
公开(公告)日：2004-01-27
申请号：US09504160
申请日：2000-02-15
申请人： Soon-Gil Jung , Shang-Ching Dong , Hiroshi Takeuchi , Norio Shoji , Keiji Narusawa , Michiya Sako
发明人： Soon-Gil Jung , Shang-Ching Dong , Hiroshi Takeuchi , Norio Shoji , Keiji Narusawa , Michiya Sako
IPC分类号： G11B502
CPC分类号： G11B5/09 , G11B5/012
摘要： A write amplifier circuit in a magnetic storage system has a cross coupling circuit and an active damp circuit to supply an improved write current to the head writing the data onto the media within the magnetic storage system. The inclusion of the cross coupling circuit decreases a rise time and a fall time associated with the write current. The active damp circuit reduces the undershoot and ringing of the write current. Thus, the write amplifier circuit is suitable for high speed data storage writing applications requiring minimal distortion of the data written to a magnetic medium. The write amplifier circuit achieves these improvements in the waveform of the write current by incorporating circuit elements and using both a negative feedback path and a feedforward path. In particular, the cross coupling circuit provides a feedforward path within the write amplifier circuit to a first current which creates a second current that is proportional and greater than the first current such that the second current increases the write current available for the head. Similarly, the active damp circuit provides a negative feedback path from the output terminals of the write amplifier circuit to a third current which creates a fourth current that is proportional and greater than the third current such that the fourth current damps an undershoot and ringing associated with the write current.
摘要翻译：磁存储系统中的写放大器电路具有交叉耦合电路和有源阻尼电路，用于向磁头提供改善的写入电流，从而将数据写入到磁存储系统内的介质上。交叉耦合电路的包含减少了与写入电流相关联的上升时间和下降时间。有源潮湿电路可以减少写入电流的下冲和振荡。因此，写放大器电路适用于要求写入磁介质的数据失真最小的高速数据存储写入应用。写放大器电路通过并入电路元件并使用负反馈路径和前馈路径来实现写入电流波形的这些改进。特别地，交叉耦合电路将写入放大器电路内的前馈路径提供到第一电流，该第一电流产生比第一电流成比例并且大于第一电流的第二电流，使得第二电流增加可用于磁头的写入电流。类似地，有源阻尼电路提供从写入放大器电路的输出端子到第三电流的负反馈路径，该第三电流产生比第三电流成比例并且大于第三电流的第四电流，使得第四电流抑制下行和与写入电流。

7. 发明授权

US06597650B2 Nonlinearity compensation circuit and method, control circuit and method for nonlinearity compenstation circuit and recording and/or playback apparatus employing the same 失效
标题翻译：用于非线性补偿电路的非线性补偿电路和方法，控制电路和方法以及采用该非线性补偿电路的记录和/或重放装置
公开(公告)号：US06597650B2
公开(公告)日：2003-07-22
申请号：US09870714
申请日：2001-06-01
申请人： Masayuki Katakura , Junkichi Sugita , Norio Shoji , Masato Sekine , Kimimasa Senba , Katsuhisa Daio
发明人： Masayuki Katakura , Junkichi Sugita , Norio Shoji , Masato Sekine , Kimimasa Senba , Katsuhisa Daio
IPC分类号： G11B700
CPC分类号： G06G7/24
摘要： A nonlinearity compensation circuit is disclosed which includes an inverse hyperbolic function generation circuit for converting differential currents corresponding to input signals in+ and in− into differential voltages which increase in proportion to an inverse hyperbolic function, an offset provision circuit for providing an offset corresponding to control signals c+ and c− to the differential voltages outputted from the inverse hyperbolic function generation circuit and a hyperbolic function generation circuit for converting the differential voltages to which the offset has been provided by the offset provision circuit into signals which increase in proportion to a hyperbolic function and outputting the resulting signals as output signals out+ and out−. Consequently, compensation for the nonlinearity such as second order distortion can be performed for the read signal from a recording medium.
摘要翻译：公开了一种非线性补偿电路，其包括反相双曲线函数产生电路，用于将对应于+中的输入信号的差分电流转换为与反双曲线函数成比例增加的差分电压;偏移提供电路，用于提供与控制相对应的偏移信号c +和c-对应于从反双曲函数生成电路输出的差分电压，以及双曲线函数生成电路，用于将由偏移提供电路提供的偏移的差分电压转换为与双曲线函数成比例增加的信号并将所得信号作为输出信号out +和out输出。因此，可以对来自记录介质的读取信号执行诸如二阶失真之类的非线性的补偿。

8. 发明申请

US20050179484A1 Bias voltage supply circuit and radio-frequency amplification circuit 失效
标题翻译：偏置电压电路和射频放大电路
公开(公告)号：US20050179484A1
公开(公告)日：2005-08-18
申请号：US11047564
申请日：2005-02-02
申请人： Noboru Sasho , Norio Shoji
发明人： Noboru Sasho , Norio Shoji
IPC分类号： G05F3/26 , G05F3/16 , G05F3/20 , H03F3/19
CPC分类号： G05F3/205
摘要： A bias voltage supply circuit of a radio-frequency amplification circuit has a constant-voltage power supply generating a constant voltage higher than the bias voltage, a rectifier transistor and a constant-current power supply supplying a constant current to the rectifier transistor. The rectifier transistor is connected between a supply point of a bias voltage connected to an input terminal of the radio-frequency amplification transistor via an element for bias supply and a power supply voltage supply line, wherein a control terminal is kept by a constant voltage that the constant-voltage power supply generates. Since descent of electric potential of the input terminal of a radio-frequency signal does not arise because of circuit composition, the radio-frequency amplification circuit has a saturation characteristic superior than a prior art.
摘要翻译：射频放大电路的偏置电压电路具有产生高于偏置电压的恒定电压的恒压电源，整流晶体管和向整流晶体管供给恒定电流的恒流电源。整流晶体管经由用于偏置电源的元件和电源电压供给线连接在与射频放大晶体管的输入端子连接的偏置电压的供电点之间，其中控制端子由恒定电压保持，产生恒压电源。由于电路组成，不产生射频信号的输入端的电位下降，所以射频放大电路的饱和特性优于现有技术。

9. 发明授权

US06762894B2 Head apparatus, hard disk apparatus and recording and playback apparatus 失效
标题翻译：头装置，硬盘装置和记录和重放装置
公开(公告)号：US06762894B2
公开(公告)日：2004-07-13
申请号：US09892999
申请日：2001-06-28
申请人： Keiji Narusawa , Norio Shoji
发明人： Keiji Narusawa , Norio Shoji
IPC分类号： G11B509
CPC分类号： G11B5/012 , G11B5/02 , G11B5/09 , G11B20/10009 , G11B20/24 , G11B33/121 , G11B2005/0013 , G11B2005/0018
摘要： A head apparatus which is tough against disturbing noise and superior in the S/N ratio and which can cope with an increase of the capacity of a recording medium is disclosed. A first playback amplifier for amplifying the playback signal of a MR head and a register circuit for setting the bias current to the MR head are formed as a COS IC. The COS IC is mounted on a suspension together with the MR head. A feeble playback signal outputted from the MR head is amplified by the first playback amplifier once and then transmitted to a mother IC over a pair of signal lines. The amplified playback signal is tough against disturbing noise during transmission.
摘要翻译：公开了一种能够抵抗干扰噪声并且S / N比优异并且能够应付记录介质的容量增加的头装置。形成用于放大MR磁头的重放信号的第一重放放大器和用于将偏置电流设置到MR磁头的寄存器电路作为COS IC。 COS IC与MR头一起安装在悬架上。由MR头输出的微弱重放信号被第一重放放大器放大一次，然后通过一对信号线发送到母IC。放大的播放信号在传输期间对于干扰噪声是坚韧的。

10. 发明授权

US06496076B1 PLL circuit and recorded data reproduction apparatus 有权
标题翻译： PLL电路和记录数据再现装置
公开(公告)号：US06496076B1
公开(公告)日：2002-12-17
申请号：US09717102
申请日：2000-11-22
申请人： Norio Shoji , Kimimasa Senba
发明人： Norio Shoji , Kimimasa Senba
IPC分类号： G11B509
CPC分类号： G11B20/1426 , G11B5/012 , G11B5/09 , H03L7/091
摘要： A PLL (phase-locked loop) circuit is configured with a phase-error detection circuit comprises the following: a provisional judge circuit for provisionally judging a data signal being input to an A/D converter into three levels of 1, 0, and −1; a pattern detector which, among data signals being input in accordance with a result of the provisional judgment, checks a transition pattern ranging from a data signal that precedes one clock cycle to the actually present data signal, and then, when a specific pattern is detected, instructs a selector to select output data from the A/D converter; and the selector which, in compliance with instruction from the pattern detector, selects phase-error data from data signals output from the A/D converter, and then converts the selected phase-error data into an electric current before externally delivering it as an error-current.
摘要翻译： PLL（锁相环）电路配置有一个包括以下的相位误差检测电路：临时判断电路，用于将输入到A / D转换器的数据信号临时判断为三个等级的1,0和 - 1; 在根据临时判断结果输入的数据信号中的模式检测器检查从一个时钟周期之前的数据信号到实际存在的数据信号的转换模式，然后，当检测到特定模式时指示选择器从A / D转换器选择输出数据; 以及选择器，其根据来自模式检测器的指令从从A / D转换器输出的数据信号中选择相位误差数据，然后将所选择的相位误差数据转换为电流，然后将其作为错误传送给外部 -当前。

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