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1. 发明授权

US08330254B2 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US08330254B2
公开(公告)日：2012-12-11
申请号：US12647639
申请日：2009-12-28
申请人： Masayuki Furumiya , Hiroaki Ohkubo , Fuyuki Okamoto , Masayuki Mizuno , Koichi Nose , Yoshihiro Nakagawa , Yoshio Kameda
发明人： Masayuki Furumiya , Hiroaki Ohkubo , Fuyuki Okamoto , Masayuki Mizuno , Koichi Nose , Yoshihiro Nakagawa , Yoshio Kameda
IPC分类号： H01L23/544
CPC分类号： H01L23/48 , G01R31/2884 , G01R31/3025 , G01R31/31721 , H01L22/32 , H01L23/50 , H01L23/5286 , H01L23/544 , H01L24/06 , H01L2223/5446 , H01L2924/01029
摘要： A semiconductor device includes a semiconductor wafer in which semiconductor chip forming regions and a scribe region located between the semiconductor chip forming regions are formed, a plurality of semiconductor chip circuit portions provided over the semiconductor wafer, a plurality of first conductive layers, provided in each of the semiconductor chip forming regions, which is electrically connected to each of the circuit portions, and a first connecting portion that electrically connects the first conductive layers to each other across a portion of the scribe region. An external power supply or grounding pad is connected to any one of the first conductive layer and the first connecting portion. The semiconductor device includes a communication portion, connected to the circuit portion, which performs communication with the outside by capacitive coupling or inductive coupling.
摘要翻译：一种半导体器件包括其半导体芯片形成区域和位于半导体芯片形成区域之间的划线区域形成的半导体晶片，设置在半导体晶片上的多个半导体芯片电路部分，设置在每个半导体芯片形成区域中的多个第一导电层电连接到每个电路部分的半导体芯片形成区域以及跨越划线区域的一部分将第一导电层彼此电连接的第一连接部分。外部电源或接地焊盘连接到第一导电层和第一连接部分中的任一个。半导体器件包括连接到电路部分的通信部分，其通过电容耦合或电感耦合与外部进行通信。

2. 发明授权

US08188566B2 Semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件
公开(公告)号：US08188566B2
公开(公告)日：2012-05-29
申请号：US13075615
申请日：2011-03-30
申请人： Masayuki Furumiya , Hiroaki Ohkubo , Yasutaka Nakashiba
发明人： Masayuki Furumiya , Hiroaki Ohkubo , Yasutaka Nakashiba
IPC分类号： H01L29/00 , H01L21/8238 , H01L21/8222
CPC分类号： H01L21/761 , H01L21/823481 , H01L27/0629 , H01L27/088
摘要： The bottom side of an N type silicon substrate is connected to a power supply terminal, a second P type epitaxial layer is formed on all sides of the N type silicon substrate, and a device forming portion is provided on the second P type epitaxial layer. A first P type epitaxial layer and an interlayer insulating film are provided on the device forming portion and an N well and a P well are formed on the top surface of the first P type epitaxial layer. The second P type epitaxial layer is connected to a ground terminal via the first P type epitaxial layer, the P well, a p+ diffusion region, a via and a wire. Accordingly, a pn junction is formed at the interface between the second P type epitaxial layer and the N type silicon substrate.
摘要翻译： N型硅衬底的底侧连接到电源端子，在N型硅衬底的所有侧面上形成第二P型外延层，在第二P型外延层上设置器件形成部分。第一P型外延层和层间绝缘膜设置在器件形成部分上，N阱和P阱形成在第一P型外延层的顶表面上。第二P型外延层通过第一P型外延层，P阱，p +扩散区，通孔和导线连接到接地端子。因此，在第二P型外延层和N型硅衬底之间的界面处形成pn结。

3. 发明授权

US08357990B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08357990B2
公开(公告)日：2013-01-22
申请号：US12458139
申请日：2009-07-01
申请人： Masayuki Furumiya , Hiroaki Ohkubo , Yasutaka Nakashiba
发明人： Masayuki Furumiya , Hiroaki Ohkubo , Yasutaka Nakashiba
IPC分类号： H01L29/00
CPC分类号： H01L21/823878 , H01L21/823892 , H01L27/0733 , H01L27/0928
摘要： A width of a region where each of the N wells is in contact with the buried P well is not more than 2 μm. A ground voltage and a power supply voltage are applied to the P well and the N well, respectively. A decoupling capacitor is formed between the N well and the buried P well.
摘要翻译：每个N阱与埋置的P阱接触的区域的宽度不大于2μm。接地电压和电源电压分别施加到P阱和N阱。在N阱和P阱之间形成去耦电容。

4. 发明授权

US07288826B2 Semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件
公开(公告)号：US07288826B2
公开(公告)日：2007-10-30
申请号：US10688000
申请日：2003-10-17
申请人： Masayuki Furumiya , Hiroaki Ohkubo , Yasutaka Nakashiba
发明人： Masayuki Furumiya , Hiroaki Ohkubo , Yasutaka Nakashiba
IPC分类号： H01L29/00
CPC分类号： H01L21/761 , H01L21/823481 , H01L27/0629 , H01L27/088
摘要： The bottom side of an N type silicon substrate is connected to a power supply terminal, a second P type epitaxial layer is formed on all sides of the N type silicon substrate, and a device forming portion is provided on the second P type epitaxial layer. A first P type epitaxial layer and an interlayer insulating film are provided on the device forming portion and an N well and a P well are formed on the top surface of the first P type epitaxial layer. The second P type epitaxial layer is connected to a ground terminal via the first P type epitaxial layer, the P well, a p+ diffusion region, a via and a wire. Accordingly, a pn junction is formed at the interface between the second P type epitaxial layer and the N type silicon substrate.
摘要翻译： N型硅衬底的底侧连接到电源端子，在N型硅衬底的所有侧面上形成第二P型外延层，并且在第二P型外延层上设置器件形成部分。第一P型外延层和层间绝缘膜设置在器件形成部分上，并且N阱和P阱形成在第一P型外延层的顶表面上。第二P型外延层通过第一P型外延层，P阱，p + +扩散区，通孔和导线连接到接地端子。因此，在第二P型外延层和N型硅衬底之间的界面处形成pn结。

5. 发明授权

US07256456B2 SOI substrate and semiconductor integrated circuit device 失效
标题翻译： SOI衬底和半导体集成电路器件
公开(公告)号：US07256456B2
公开(公告)日：2007-08-14
申请号：US10739166
申请日：2003-12-19
申请人： Hiroaki Ohkubo , Masayuki Furumiya , Ryota Yamamoto , Yasutaka Nakashiba
发明人： Hiroaki Ohkubo , Masayuki Furumiya , Ryota Yamamoto , Yasutaka Nakashiba
IPC分类号： H01L27/12 , H01L27/01 , H01L31/0392
CPC分类号： H01L21/743 , H01L21/84 , H01L27/1203
摘要： A semiconductor IC device includes a base substrate comprising P−-type silicon, a first P+-type silicon layer is provided on the base substrate, and an N+-type silicon layer and a second P+-type silicon layer are provided in the same layer thereon. The impurity concentration of the first P+-type silicon layer and the N+-type silicon layer is higher than that of the base substrate. Also, a buried oxide layer and an SOI layer are provided on the entire upper surface of the N+-type silicon layer and the second P+-type silicon layer. The first P+-type silicon layer is connected to ground potential wiring GND, and the N+-type silicon layer is connected to power-supply potential wiring VDD. Accordingly, a decoupling capacitor, which is connected in parallel to the power supply, is formed between the P+-type silicon layer and the N+-type silicon layer.
摘要翻译：半导体IC器件包括基底衬底，其包括P型 - 硅，第一P + +型硅层设置在基底衬底上，并且N + +型硅层和第二P + +型硅层设置在其上的同一层中。第一P + + / - 型硅层和N + + - 型硅层的杂质浓度高于基底衬底的杂质浓度。此外，在N + +型硅层和第二P + +型硅层的整个上表面上设置掩埋氧化物层和SOI层。第一P + + / - 型硅层连接到地电位布线GND，并且N + +型硅层连接到电源电位布线VDD。因此，在P + +型硅层和N + +型硅层之间形成与电源并联连接的去耦电容器。

6. 发明申请

US20050139956A1 Semiconductor device and fabrication method thereof 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20050139956A1
公开(公告)日：2005-06-30
申请号：US11017695
申请日：2004-12-22
申请人： Hiroaki Ohkubo , Ryota Yamamoto , Masayuki Furumiya , Masaharu Sato , Kuniko Kikuta , Makoto Nakayama , Yasutaka Nakashiba
发明人： Hiroaki Ohkubo , Ryota Yamamoto , Masayuki Furumiya , Masaharu Sato , Kuniko Kikuta , Makoto Nakayama , Yasutaka Nakashiba
IPC分类号： H01L27/04 , H01L21/02 , H01L21/822 , H01L23/522 , H01L21/8234 , H01L21/20 , H01L29/00
CPC分类号： H01L28/40 , H01L23/5223 , H01L2924/0002 , H01L2924/00
摘要： On a silicon substrate, a first insulation layer, a lower conductive layer, a capacitor-insulator layer, and an upper conductive layer are formed in that order. Then, a first resist pattern is formed, the upper conductive layer is etched to form an upper electrode, and the capacitor-insulator layer is successively etched partway under the same etching condition as that of the upper conductive layer. Next, second resist pattern is formed, the remaining part of the capacitor-insulator layer is etched to form a second insulation layer, and the lower conductive layer is successively etched under the same etching condition as that of the capacitor-insulator layer so as to form a lower electrode and a lower wiring. In this manner, an MiM capacitor element constituted by the upper electrode, a part of the second insulation layer, and the lower electrode can be fabricated.
摘要翻译：在硅衬底上依次形成第一绝缘层，下导电层，电容器 - 绝缘体层和上导电层。然后，形成第一抗蚀剂图案，蚀刻上导电层以形成上电极，并且在与上导电层的蚀刻条件相同的蚀刻条件下，电容器 - 绝缘体层被连续蚀刻。接下来，形成第二抗蚀剂图案，蚀刻电容器 - 绝缘体层的其余部分以形成第二绝缘层，并且在与电容器 - 绝缘体层的蚀刻条件相同的蚀刻条件下，依次蚀刻下导电层，以便形成下电极和下布线。以这种方式，可以制造由上电极，第二绝缘层的一部分和下电极构成的MiM电容器元件。

7. 发明授权

US06879234B2 Semiconductor integrated circuit 失效
标题翻译：半导体集成电路
公开(公告)号：US06879234B2
公开(公告)日：2005-04-12
申请号：US10352048
申请日：2003-01-28
申请人： Masayuki Furumiya , Ryota Yamamoto , Jun Kishi , Hiroaki Ohkubo , Yasutaka Nakashiba
发明人： Masayuki Furumiya , Ryota Yamamoto , Jun Kishi , Hiroaki Ohkubo , Yasutaka Nakashiba
IPC分类号： H01F17/00 , H01F17/02 , H01L21/822 , H01L27/04 , H01L27/08 , H03B5/12 , H01F5/00 , H01F27/28
CPC分类号： H01L27/08 , H01F17/0006 , H01F2021/125 , H03B5/1215 , H03B5/1228 , H03B5/124
摘要： Electrically conductive layers 1a and 2a connected to each other via a contact form one inductor, while electrically conductive layers 1b and 2b connected to each other via other contact form the other inductor. Since the areas defined by the loops forming these two inductors are equal to each other, the inductances of the inductors are also equal to each other. Between both the inductors, the lengths in the loop of the portions (the conductive layers 1a and 1b) formed on a lower interlayer insulating film are equal to each other, while the lengths in the loop of the portions (the conductive layers 2a and 2b) formed on an upper interlayer insulating film are also equal to each other. This allows external disturbances such as parasitic capacitance to affect both the inductors equally. Accordingly, a voltage controlled oscillator incorporating the invention can stably provide undistorted sinusoidal oscillation signals.
摘要翻译：导电层1a和2a通过接触形成一个电感器，而导电层1b和2b通过其它触点相互连接形成另一个电感器。由于由形成这两个电感器的环形成的区域彼此相等，所以电感器的电感也彼此相等。在两个电感器之间，形成在下层间绝缘膜上的部分（导电层1a和1b）的环路中的长度彼此相等，而部分（导电层2a和2b）的环路中的长度）也相互相等。这允许诸如寄生电容的外部干扰同样影响电感器。因此，结合本发明的压控振荡器可以稳定地提供无失真的正弦振荡信号。

8. 发明授权

US07973383B2 Semiconductor integrated circuit device having a decoupling capacitor 有权
标题翻译：具有去耦电容器的半导体集成电路器件
公开(公告)号：US07973383B2
公开(公告)日：2011-07-05
申请号：US11860050
申请日：2007-09-24
申请人： Masayuki Furumiya , Hiroaki Ohkubo , Yasutaka Nakashiba
发明人： Masayuki Furumiya , Hiroaki Ohkubo , Yasutaka Nakashiba
IPC分类号： H01L29/00 , H01L21/8238
CPC分类号： H01L21/761 , H01L21/823481 , H01L27/0629 , H01L27/088
摘要： The bottom side of an N type silicon substrate is connected to a power supply terminal, a second P type epitaxial layer is formed on all sides of the N type silicon substrate, and a device forming portion is provided on the second P type epitaxial layer. A first P type epitaxial layer and an interlayer insulating film are provided on the device forming portion and an N well and a P well are formed on the top surface of the first P type epitaxial layer. The second P type epitaxial layer is connected to a ground terminal via the first P type epitaxial layer, the P well, a p+ diffusion region, a via and a wire. Accordingly, a pn junction is formed at the interface between the second P type epitaxial layer and the N type silicon substrate.
摘要翻译： N型硅衬底的底侧连接到电源端子，在N型硅衬底的所有侧面上形成第二P型外延层，在第二P型外延层上设置器件形成部分。第一P型外延层和层间绝缘膜设置在器件形成部分上，N阱和P阱形成在第一P型外延层的顶表面上。第二P型外延层通过第一P型外延层，P阱，p +扩散区，通孔和导线连接到接地端子。因此，在第二P型外延层和N型硅衬底之间的界面处形成pn结。

9. 发明申请

US20070262383A1 SOI SUBSTRATE AND SEMICONDUCTOR INTEGRATED CIRUIT DEVICE 审中-公开
标题翻译： SOI衬底和半导体集成电路器件
公开(公告)号：US20070262383A1
公开(公告)日：2007-11-15
申请号：US11767112
申请日：2007-06-22
申请人： Hiroaki OHKUBO , Masayuki Furumiya , Ryota Yamamoto , Yasutaka Nakashiba
发明人： Hiroaki OHKUBO , Masayuki Furumiya , Ryota Yamamoto , Yasutaka Nakashiba
IPC分类号： H01L31/0392
CPC分类号： H01L21/743 , H01L21/84 , H01L27/1203
摘要： A semiconductor IC device includes a base substrate comprising P−-type silicon, a first P+-type silicon layer is provided on the base substrate, and an N+-type silicon layer and a second P+-type silicon layer are provided in the same layer thereon. The impurity concentration of the first P+-type silicon layer and the N+-type silicon layer is higher than that of the base substrate. Also, a buried oxide layer and an SOI layer are provided on the entire upper surface of the N+-type silicon layer and the second P+-type silicon layer. The first P+-type silicon layer is connected to ground potential wiring GND, and the N+-type silicon layer is connected to power-supply potential wiring VDD. Accordingly, a decoupling capacitor, which is connected in parallel to the power supply, is formed between the P+-type silicon layer and the N+-type silicon layer.
摘要翻译：半导体IC器件包括基底衬底，其包括P型 - 硅，第一P + +型硅层设置在基底衬底上，并且N + +型硅层和第二P + +型硅层设置在其上的同一层中。第一P + + / - 型硅层和N + + - 型硅层的杂质浓度高于基底衬底的杂质浓度。此外，在N + +型硅层和第二P + +型硅层的整个上表面上设置掩埋氧化物层和SOI层。第一P + + / - 型硅层连接到地电位布线GND，并且N + +型硅层连接到电源电位布线VDD。因此，在P + +型硅层和N + +型硅层之间形成与电源并联连接的去耦电容器。

10. 发明授权

US07095072B2 Semiconductor device with wiring layers forming a capacitor 有权
标题翻译：具有形成电容器的布线层的半导体器件
公开(公告)号：US07095072B2
公开(公告)日：2006-08-22
申请号：US10753325
申请日：2004-01-09
申请人： Masayuki Furumiya , Hiroaki Ohkubo , Yasutaka Nakashiba
发明人： Masayuki Furumiya , Hiroaki Ohkubo , Yasutaka Nakashiba
IPC分类号： H01L27/108 , H01L29/76 , H01L29/94 , H01G4/228 , H01G4/30
CPC分类号： H01L28/82 , H01L23/5222 , H01L27/0805 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A semiconductor device, in which four pieces of strip-shaped electrodes, whose longitudinal directions are the same, are formed in each layer of a plurality of wiring layers that are provided by a same design rule with each other, simultaneously with regular wirings. In each wiring layer, two pieces each of first electrode and second electrode are formed parallelly with each other, alternately, and remote from each other. Then, the first electrodes formed in each layer are connected to each other by a first via, the second electrodes formed in each layer are connected to each other by a second via, a first structure body formed by connecting the first electrodes and the first via to each other is connected to a ground wiring, and a second structure body formed by connecting the second electrodes and the second via to each other is connected to a power source wiring.
摘要翻译：在规则布线的同时，以相同的设计规则设置的多个布线层的每一层中形成长度方向相同的四条条状电极的半导体装置。在每个布线层中，第一电极和第二电极中的两个彼此平行地彼此交替地彼此远离地形成。然后，形成在各层中的第一电极通过第一通孔相互连接，形成在各层中的第二电极通过第二通孔相互连接，第一结构体通过将第一电极和第一通孔彼此连接到接地布线，并且通过将第二电极和第二通孔彼此连接而形成的第二结构体连接到电源布线。

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