专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08330254B2 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US08330254B2
公开(公告)日：2012-12-11
申请号：US12647639
申请日：2009-12-28
申请人： Masayuki Furumiya , Hiroaki Ohkubo , Fuyuki Okamoto , Masayuki Mizuno , Koichi Nose , Yoshihiro Nakagawa , Yoshio Kameda
发明人： Masayuki Furumiya , Hiroaki Ohkubo , Fuyuki Okamoto , Masayuki Mizuno , Koichi Nose , Yoshihiro Nakagawa , Yoshio Kameda
IPC分类号： H01L23/544
CPC分类号： H01L23/48 , G01R31/2884 , G01R31/3025 , G01R31/31721 , H01L22/32 , H01L23/50 , H01L23/5286 , H01L23/544 , H01L24/06 , H01L2223/5446 , H01L2924/01029
摘要： A semiconductor device includes a semiconductor wafer in which semiconductor chip forming regions and a scribe region located between the semiconductor chip forming regions are formed, a plurality of semiconductor chip circuit portions provided over the semiconductor wafer, a plurality of first conductive layers, provided in each of the semiconductor chip forming regions, which is electrically connected to each of the circuit portions, and a first connecting portion that electrically connects the first conductive layers to each other across a portion of the scribe region. An external power supply or grounding pad is connected to any one of the first conductive layer and the first connecting portion. The semiconductor device includes a communication portion, connected to the circuit portion, which performs communication with the outside by capacitive coupling or inductive coupling.
摘要翻译：一种半导体器件包括其半导体芯片形成区域和位于半导体芯片形成区域之间的划线区域形成的半导体晶片，设置在半导体晶片上的多个半导体芯片电路部分，设置在每个半导体芯片形成区域中的多个第一导电层电连接到每个电路部分的半导体芯片形成区域以及跨越划线区域的一部分将第一导电层彼此电连接的第一连接部分。外部电源或接地焊盘连接到第一导电层和第一连接部分中的任一个。半导体器件包括连接到电路部分的通信部分，其通过电容耦合或电感耦合与外部进行通信。

2. 发明授权

US06833869B1 Solid-state imaging device with voltage followers formed by selected row transistors and column transistors 失效
标题翻译：具有由选定的行晶体管和列晶体管形成的电压跟随器的固态成像器件
公开(公告)号：US06833869B1
公开(公告)日：2004-12-21
申请号：US09551102
申请日：2000-04-18
申请人： Fuyuki Okamoto
发明人： Fuyuki Okamoto
IPC分类号： H04N314
CPC分类号： H04N5/378 , H04N5/355
摘要： A solid-state imaging device has an array of pixels arranged in a matrix pattern of rows and columns. Each pixel has a photodiode for developing a voltage corresponding to light incident thereon, a first amplifying transistor for amplifying the voltage and a row select switching transistor responsive to a row select signal from a row line for coupling the amplified voltage to a column line. Multiple second amplifying transistors are respectively connected to multiple column lines. When the row select switching transistors of the pixels in one of the rows are turned on in response to a row select signal, the second amplifying transistors and the first amplifying transistors of the selected row jointly constitute voltage followers for respectively amplifying the voltages coupled to the column lines. Multiple column select switching transistors provide sequentially coupling of the outputs of the voltage followers to an output line in response to column select signals.
摘要翻译：固态成像装置具有以行和列的矩阵图案排列的像素阵列。每个像素具有用于显影对应于其上的光的电压的光电二极管，用于放大电压的第一放大晶体管和响应来自用于将放大的电压耦合到列线的行线选择信号的行选择开关晶体管。多个第二放大晶体管分别连接到多个列线。当响应于行选择信号使行中一行中的像素的行选择开关晶体管导通时，所选行的第二放大晶体管和第一放大晶体管共同构成电压跟随器，用于分别放大耦合到列线。多列选择开关晶体管响应于列选择信号，将电压跟随器的输出依次耦合到输出线。

3. 发明授权

US5546035A Latch circuit having a logical operation function 失效
标题翻译：锁存电路具有逻辑运算功能
公开(公告)号：US5546035A
公开(公告)日：1996-08-13
申请号：US390044
申请日：1995-02-17
申请人： Fuyuki Okamoto
发明人： Fuyuki Okamoto
IPC分类号： H03K3/012 , H03K3/037 , H03K3/356 , H03K19/0948 , H03K19/20
CPC分类号： H03K3/356156 , H03K3/012 , H03K3/037 , H03K3/35606
摘要： A latch circuit with an NAND function comprises a three-input NAND gate circuit, a first transfer gate connected between a first input terminal and a first input of the NAND gate circuit, a second transfer gate connected between a second input terminal and a second input of the NAND gate circuit, and a third transfer gate connected between a third input terminal and a third input of the NAND gate circuit. An input of a feedback inverter is connected To an output of the NAND gate circuit, and an output of the feedback inverter is connected to the first input of the NAND gate circuit through a fourth transfer gate. The second and third inputs of the NAND gate circuit are pulled up to a logical high level through P-channel MOS transistors. The first, second, third and fourth transfer gates and the P-channel MOS transistors are controlled by a clock signal in such a manner that when the first, second and third transfer gates are on, the fourth transfer gate and the P-channel MOS transistors are off, so that the NAND gate circuit performs a NAND operation in response to input signals applied to the first, second and third input terminals, and when the first, second and third transfer gates are off, the third transfer gate and the P-channel MOS transistors are on, so that a latch operation is performed to maintain a logical value on the output of the NAND gate circuit.
摘要翻译：具有NAND功能的锁存电路包括三输入NAND门电路，连接在第一输入端和非门电路的第一输入端之间的第一传输栅极，连接在第二输入端和第二输入端之间的第二传输栅和与非门电路的第三输入端连接的第三传输栅极。反馈反相器的输入端连接到非门电路的输出端，反相逆变器的输出通过第四传输门连接到与非门电路的第一输入端。 NAND门电路的第二和第三输入通过P沟道MOS晶体管被提升到逻辑高电平。第一，第二，第三和第四传输门和P沟道MOS晶体管由时钟信号控制，使得当第一，第二和第三传输门导通时，第四传输门和P沟道MOS 晶体管截止，使得NAND门电路响应于施加到第一，第二和第三输入端的输入信号而执行NAND操作，并且当第一，第二和第三传输门关闭时，第三传输门和P 通道MOS晶体管导通，使得执行锁存操作以保持NAND门电路的输出上的逻辑值。

4. 发明授权

US5369607A Floating-point and fixed-point addition-subtraction assembly 失效
标题翻译：浮点和定点加减法装配
公开(公告)号：US5369607A
公开(公告)日：1994-11-29
申请号：US3491
申请日：1993-01-12
申请人： Fuyuki Okamoto
发明人： Fuyuki Okamoto
IPC分类号： G06F7/00 , G06F7/485 , G06F7/50 , G06F7/505 , G06F7/76 , G06F7/38
CPC分类号： G06F7/505 , G06F7/485
摘要： Apparatus for use in a floating-point and fixed-point adder-subtractor assembly. The apparatus includes a comparator and selector circuit disposed prior to an adder-subtracter for determining a larger and smaller operand prior to the addition and subtraction operation. The comparator and selector circuit inputs the larger operand into a first predetermined input of the adder-subtracter and the smaller operand into a second predetermined input of the adder-subtracter. Additionally, first and second selector circuits may be provided for multiplexing first and second fixed point data operands into the first and second inputs of the adder-subtracter, respectively. A shifter is provided for shifting at least one of the operands prior to inputting the operand into the adder-subtracter for selectively performing a position alignment. Accordingly, a simplified structure provides fixed-point and floating-point data addition-subtraction in a highly efficient manner.
摘要翻译：用于浮点和定点加减法器组件的装置。该装置包括比较器和选择器电路，其设置在加法器 - 减法器之前，用于在加法和减法运算之前确定较大和较小的操作数。比较器和选择器电路将较大的操作数输入到加法器 - 减法器的第一预定输入端，将较小的操作数输入到加法器 - 减法器的第二预定输入端。此外，可以提供第一和第二选择器电路，用于将第一和第二固定点数据操作数分别复用到加法器 - 减法器的第一和第二输入端。提供一个移位器，用于在将操作数输入到加法器 - 减法器中以选择性地执行位置对准之前使操作数中的至少一个移位。因此，简化的结构以高效的方式提供定点和浮点数据加减。

5. 发明申请

US20050206465A1 Voltage control oscillator 审中-公开
标题翻译：电压控制振荡器
公开(公告)号：US20050206465A1
公开(公告)日：2005-09-22
申请号：US11081618
申请日：2005-03-17
申请人： Fuyuki Okamoto
发明人： Fuyuki Okamoto
IPC分类号： H01L29/00 , H03B5/00 , H03B5/04 , H03B5/12
CPC分类号： H03B5/1228 , H03B5/1212 , H03B5/1253 , H03B5/1293
摘要： An LC circuit including an inductor and a pair of varactor elements is provided in an LC-VCO. This LC circuit outputs complementary alternating current signals from a pair of output terminals. The varactor element is formed by providing a gate electrode on an N well. Then, the well terminals of the varactor elements are connected to the respective output terminals, and the gate terminals of the varactor elements are connected to a control terminal. Thereby, as a control voltage to be applied to the control terminal becomes higher, the capacitance of the varactor element increases, and the frequency of the alternating current signal lowers.
摘要翻译：在LC-VCO中提供了包括电感器和一对变容二极管元件的LC电路。该LC电路从一对输出端子输出互补的交流信号。通过在N阱上设置栅电极来形成变容二极管元件。然后，变容二极管元件的阱端子连接到各个输出端子，变容二极管元件的栅极端子连接到控制端子。因此，随着要施加到控制端子的控制电压变高，变容二极管元件的电容增加，并且交流信号的频率降低。

6. 发明授权

US06410900B1 Solid-state image sensor and method of driving the same 有权
标题翻译：固态图像传感器及其驱动方法
公开(公告)号：US06410900B1
公开(公告)日：2002-06-25
申请号：US09563208
申请日：2000-05-02
申请人： Fuyuki Okamoto
发明人： Fuyuki Okamoto
IPC分类号： H01L2700
CPC分类号： H01L27/14643 , H04N5/341
摘要： There is provided a solid-state image sensor including (a) a plurality of pixels arranged in a matrix in a photoelectric transfer region, (b) at least one movement-detector located in the photoelectric transfer region, (c) a first Y-scanner making successive access to the pixels in rows in a predetermined region in the photoelectric transfer region, and (d) a first X-scanner reading out signals running through signal output lines extending through the predetermined region. The first and second scanners both scan a predetermined region associated with a movement-detector which has transmitted a detection signal. The solid-state image sensor makes it possible to immediately detect movement when it has occurred, identify a region in which movement has occurred, and detect movement while carrying out scanning in a normal mode.
摘要翻译：提供了一种固态图像传感器，包括：（a）在光电转移区域中以矩阵形式布置的多个像素，（b）位于光电转移区域中的至少一个运动检测器，（c）第一Y- 扫描器连续访问光电转移区域中预定区域中的行中的像素，以及（d）第一X扫描器读出通过延伸穿过预定区域的信号输出线的信号。第一和第二扫描仪都扫描与已发送检测信号的运动检测器相关联的预定区域。固态图像传感器使得可以立即检测到发生时的移动，识别发生移动的区域，并且在正常模式下执行扫描时检测移动。

7. 发明授权

US06313458B1 Gain-adjustable photoreceiver circuit with photoelectric converter and amplifier 有权
标题翻译：光电转换器和放大器的增益可调光接收电路
公开(公告)号：US06313458B1
公开(公告)日：2001-11-06
申请号：US09349766
申请日：1999-07-09
申请人： Fuyuki Okamoto
发明人： Fuyuki Okamoto
IPC分类号： H01J4014
CPC分类号： H03G3/3084
摘要： A photoreceiver circuit includes (a) a photoelectric conversion element for converting incident light to a current, (b) an analog voltage amplifier circuit for amplifying a voltage corresponding to the current of the photoelectric conversion element and for producing an amplified voltage as an output of the photoreceiver circuit, and (c) an analog multiplier circuit for multiplying the amplified voltage produced by the voltage amplifier circuit by an adjusting voltage and for producing an output current with a component proportional to a product of the amplified voltage and the adjusting voltage. The output current of the analog multiplier circuit is supplied to the photoelectric converter element, thereby forming a feedback path of the voltage amplifier circuit. A voltage-lowering part and a current-leaking part may be additionally provided. The voltage-lowering part is connected between the voltage amplifier and the analog multiplier circuit, and the current-leaking part is connected in parallel to the voltage-lowering part.
摘要翻译：光接收器电路包括（a）用于将入射光转换成电流的光电转换元件，（b）模拟电压放大器电路，用于放大对应于光电转换元件的电流的电压，并产生放大电压作为输出光接收器电路，以及（c）模拟乘法器电路，用于将由电压放大器电路产生的放大电压乘以调节电压，并产生具有与放大电压和调节电压的乘积成比例的分量的输出电流。模拟乘法器电路的输出电流被提供给光电转换元件，从而形成电压放大器电路的反馈路径。可以另外设置降压部和漏电部。降压部分连接在电压放大器和模拟乘法器电路之间，漏电部分并联连接到降压部分。

8. 发明授权

US06954111B2 Voltage controlled oscillator having switches to adjust effective inductor lengths 有权
标题翻译：压控振荡器具有用于调节有效电感器长度的开关
公开(公告)号：US06954111B2
公开(公告)日：2005-10-11
申请号：US10352031
申请日：2003-01-28
申请人： Yoshinori Muramatsu , Fuyuki Okamoto
发明人： Yoshinori Muramatsu , Fuyuki Okamoto
IPC分类号： H03B1/00 , H03B5/12 , H03B5/00
CPC分类号： H03B5/1212 , H03B5/124 , H03B5/1268 , H03B5/1293 , H03B2201/0208 , H03B2201/025
摘要： At the same control voltage Vtune, the oscillation frequency with only switches SW3 and SW4 being closed is higher than that with only switches SW1 and SW2 being closed. Accordingly, even when the oscillation frequency is lower than designed with only the switches SW1 and SW2 being closed and the capacitance of varactor diodes D1 and D2 cannot be controlled to provide the desired oscillation frequency, the desired oscillation frequency can be provided by closing only the switches SW3 and SW4 to control the capacitance of the varactor diodes D1 and D2. On the oscillation frequency, a coarse tuning can be performed by controlling the switches SW1 to SW4, while a fine tuning can be performed with the varactor diodes D1 and D2. Consequently, the range of the oscillation frequency is increased.
摘要翻译：在相同的控制电压Vtune，只有开关SW 3和SW 4闭合的振荡频率高于只有开关SW 1和SW 2闭合的振荡频率。因此，即使当振荡频率低于仅开关SW 1和SW 2闭合并且变容二极管D 1和D 2的电容不能被控制以提供期望的振荡频率的设计时，可以提供期望的振荡频率通过闭合开关SW 3和SW 4来控制变容二极管D1和D2的电容。在振荡频率上，可以通过控制开关SW 1至SW 4来执行粗调，同时可以用变容二极管D1和D2进行微调。因此，振荡频率的范围增加。

9. 发明授权

US5424968A Priority encoder and floating-point adder-substractor 失效
标题翻译：优先编码器和浮点加法器 - 减法器
公开(公告)号：US5424968A
公开(公告)日：1995-06-13
申请号：US44411
申请日：1993-04-08
申请人： Fuyuki Okamoto
发明人： Fuyuki Okamoto
IPC分类号： G06F7/00 , G06F7/485 , G06F7/50 , G06F7/74 , G06F7/38 , G06F15/00
CPC分类号： G06F7/74 , G06F7/485 , G06F7/49936
摘要： A priority encoder for a normalization at a floating-point addition of subtraction for encoding a leading zero number of a difference of two input binary numbers within an error of -1, and a floating-point adder-subtractor using this priority encoder. The priority encoder includes a pre-encoder for outputting an n-bit bit string Q (=Q.sub.n, Q.sub.n-1, . . . and Q.sub.1,) from a combination (X.sub.i, Y.sub.i, X.sub.i-1, Y.sub.i-1) of ith and (i-1)th digits of input two binary numbers X and Y, and a conventional priority encoder circuit for encoding the bit string Q output from the pre-encoder. The floating-point adder-subtractor includes the priority encoder operating in parallel with a mantissa add-subtract circuit so as to output the leading zero number of the difference between the two binary numbers X and Y.
摘要翻译：一个优先编码器，用于在浮点加法运算中用于对误差为1的两个输入二进制数的差的前导零数进行编码，以及使用该优先编码器的浮点加减法器。优先级编码器包括用于从第i个组合（Xi，Yi，Xi-1，Yi-1）输出n比特串Q（= Qn，Qn-1，...）的预编码器和输入二进制数X和Y的第（i-1）位，以及用于编码从预编码器输出的位串Q的常规优先级编码器电路。浮点加减法器包括与尾数加减法电路并联运行的优先编码器，以输出两个二进制数X和Y之间的差的前零零号。

10. 发明授权

US5084835A Method and apparatus for absolute value summation and subtraction 失效
标题翻译：绝对值求和和减法的方法和装置
公开(公告)号：US5084835A
公开(公告)日：1992-01-28
申请号：US432829
申请日：1989-11-07
申请人： Fuyuki Okamoto
发明人： Fuyuki Okamoto
IPC分类号： G06F7/50 , G06F7/508 , G06F7/544
CPC分类号： G06F7/544 , G06F2207/5442
摘要： In an absolute value subtraction processing of .vertline.X-Y.vertline., carry generation and propagation functions and group carry generation and propagation functions are first generated. Then, a carry is calculated at the most significant bit in the summation of a first operand and a complement of "2" of a second operand by use of the above functions. Where the carry is "1", the above summation remains continued. Where the carry is zero, additional first and second functions are generated by inverting logic ORs of the carry generation and propagation functions and of the group carry generation and propagation functions. Thus, the summation of the second operand and a complement of "2" of the first operand is realized by use of the additional functions, the carry propagation function, and the group carry propagation function.
摘要翻译：在| X-Y |的绝对值减法处理中，首先生成携带生成和传播函数，并进行组进位生成和传播功能。然后，通过使用上述功能，在第二操作数的第一操作数和补数“2”的最大有效位中计算进位。如果进位为“1”，则上述总和仍然继续。在进位为零的情况下，通过反转进位生成和传播函数以及组进位生成和传播函数的逻辑OR产生附加的第一和第二功能。因此，通过使用附加功能，进位传播函数和组携带传播函数来实现第一操作数的第二操作数和“2”的补数的和。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式