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1. 发明申请

US20050139956A1 Semiconductor device and fabrication method thereof 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20050139956A1
公开(公告)日：2005-06-30
申请号：US11017695
申请日：2004-12-22
申请人： Hiroaki Ohkubo , Ryota Yamamoto , Masayuki Furumiya , Masaharu Sato , Kuniko Kikuta , Makoto Nakayama , Yasutaka Nakashiba
发明人： Hiroaki Ohkubo , Ryota Yamamoto , Masayuki Furumiya , Masaharu Sato , Kuniko Kikuta , Makoto Nakayama , Yasutaka Nakashiba
IPC分类号： H01L27/04 , H01L21/02 , H01L21/822 , H01L23/522 , H01L21/8234 , H01L21/20 , H01L29/00
CPC分类号： H01L28/40 , H01L23/5223 , H01L2924/0002 , H01L2924/00
摘要： On a silicon substrate, a first insulation layer, a lower conductive layer, a capacitor-insulator layer, and an upper conductive layer are formed in that order. Then, a first resist pattern is formed, the upper conductive layer is etched to form an upper electrode, and the capacitor-insulator layer is successively etched partway under the same etching condition as that of the upper conductive layer. Next, second resist pattern is formed, the remaining part of the capacitor-insulator layer is etched to form a second insulation layer, and the lower conductive layer is successively etched under the same etching condition as that of the capacitor-insulator layer so as to form a lower electrode and a lower wiring. In this manner, an MiM capacitor element constituted by the upper electrode, a part of the second insulation layer, and the lower electrode can be fabricated.
摘要翻译：在硅衬底上依次形成第一绝缘层，下导电层，电容器 - 绝缘体层和上导电层。然后，形成第一抗蚀剂图案，蚀刻上导电层以形成上电极，并且在与上导电层的蚀刻条件相同的蚀刻条件下，电容器 - 绝缘体层被连续蚀刻。接下来，形成第二抗蚀剂图案，蚀刻电容器 - 绝缘体层的其余部分以形成第二绝缘层，并且在与电容器 - 绝缘体层的蚀刻条件相同的蚀刻条件下，依次蚀刻下导电层，以便形成下电极和下布线。以这种方式，可以制造由上电极，第二绝缘层的一部分和下电极构成的MiM电容器元件。

2. 发明授权

US07432170B2 Semiconductor device and fabrication method thereof 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US07432170B2
公开(公告)日：2008-10-07
申请号：US11017695
申请日：2004-12-22
申请人： Hiroaki Ohkubo , Ryota Yamamoto , Masayuki Furumiya , Masaharu Sato , Kuniko Kikuta , Makoto Nakayama , Yasutaka Nakashiba
发明人： Hiroaki Ohkubo , Ryota Yamamoto , Masayuki Furumiya , Masaharu Sato , Kuniko Kikuta , Makoto Nakayama , Yasutaka Nakashiba
IPC分类号： H01L21/20
CPC分类号： H01L28/40 , H01L23/5223 , H01L2924/0002 , H01L2924/00
摘要： On a silicon substrate, a first insulation layer, a lower conductive layer, a capacitor-insulator layer, and an upper conductive layer are formed in that order. Then, a first resist pattern is formed, the upper conductive layer is etched to form an upper electrode, and the capacitor-insulator layer is successively etched partway under the same etching condition as that of the upper conductive layer. Next, second resist pattern is formed, the remaining part of the capacitor-insulator layer is etched to form a second insulation layer, and the lower conductive layer is successively etched under the same etching condition as that of the capacitor-insulator layer so as to form a lower electrode and a lower wiring. In this manner, an MiM capacitor element constituted by the upper electrode, a part of the second insulation layer, and the lower electrode can be fabricated.
摘要翻译：在硅衬底上依次形成第一绝缘层，下导电层，电容器 - 绝缘体层和上导电层。然后，形成第一抗蚀剂图案，蚀刻上导电层以形成上电极，并且在与上导电层的蚀刻条件相同的蚀刻条件下，电容器 - 绝缘体层被连续蚀刻。接下来，形成第二抗蚀剂图案，蚀刻电容器 - 绝缘体层的其余部分以形成第二绝缘层，并且在与电容器 - 绝缘体层的蚀刻条件相同的蚀刻条件下，依次蚀刻下导电层，以便形成下电极和下布线。以这种方式，可以制造由上电极，第二绝缘层的一部分和下电极构成的MiM电容器元件。

3. 发明授权

US07986026B2 Semiconductor device including metal-insulator-metal capacitor arrangement 失效
标题翻译：半导体器件包括金属 - 绝缘体 - 金属电容器布置
公开(公告)号：US07986026B2
公开(公告)日：2011-07-26
申请号：US12707121
申请日：2010-02-17
申请人： Masayuki Furumiya , Kuniko Kikuta , Ryota Yamamoto , Makoto Nakayama
发明人： Masayuki Furumiya , Kuniko Kikuta , Ryota Yamamoto , Makoto Nakayama
IPC分类号： H01L21/02
CPC分类号： H01L23/5223 , H01L27/0805 , H01L28/87 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device has a semiconductor substrate, a multi-layered wiring construction formed over the semiconductor device, and a metal-insulator-metal (MIM) capacitor arrangement established in the multi-layered wiring construction. The MIM capacitor arrangement includes first, second, third, fourth, fifth, and sixth electrode structures, which are arranged in order in parallel with each other at regular intervals. The first, second, fifth and sixth electrode structures are electrically connected to each other so as to define a first capacitor, and the third and fourth electrode structures are electrically connected to each other so as to define a second capacitor.
摘要翻译：半导体器件具有形成在半导体器件上的半导体衬底，多层布线结构以及在多层布线结构中建立的金属 - 绝缘体 - 金属（MIM）电容器布置。 MIM电容器装置包括以规则的间隔彼此平行地排列的第一，第二，第三，第四，第五和第六电极结构。第一，第二，第五和第六电极结构彼此电连接以限定第一电容器，并且第三和第四电极结构彼此电连接以限定第二电容器。

4. 发明授权

US07663207B2 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US07663207B2
公开(公告)日：2010-02-16
申请号：US11407323
申请日：2006-04-20
申请人： Kuniko Kikuta , Masayuki Furumiya , Ryota Yamamoto , Makoto Nakayama
发明人： Kuniko Kikuta , Masayuki Furumiya , Ryota Yamamoto , Makoto Nakayama
IPC分类号： H01L29/00
CPC分类号： H01L23/5223 , H01L28/60 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes a capacitor with an MIM structure, by which the dimensional accuracy of the device is improved, and a stable capacitance value is given. The semiconductor device 100 includes: a semiconductor substrate 102; a capacitor forming region 130 in which an MIM capacitor is formed, which has an insulating interlayer 104 formed on the semiconductor substrate 102, a first electrode 110, and a second electrode 112, and the first electrode 110 and the second electrode 112 are arranged facing each other through the insulating interlayer 104; and a shielding region 132 which includes a plurality of shielding electrodes 114 formed in the outer edge of the capacitor forming region 130 and, at the same time, set at a predetermined potential in the same layer as that of the MIM capacitor on the semiconductor substrate 102, and shields the capacitor forming region 130 from other regions.
摘要翻译：半导体器件包括具有MIM结构的电容器，通过该电容器提高器件的尺寸精度，并给出稳定的电容值。半导体器件100包括：半导体衬底102; 形成有MIM电容器的电容器形成区域130，其具有形成在半导体衬底102上的绝缘中间层104，第一电极110和第二电极112，并且第一电极110和第二电极112面向彼此通过绝缘夹层104; 以及屏蔽区域132，其包括形成在电容器形成区域130的外边缘中的多个屏蔽电极114，并且同时在与半导体衬底上的MIM电容器相同的层中设定预定电位 102，并且将电容器形成区域130与其他区域屏蔽。

5. 发明申请

US20060087004A1 Semiconductor device including metal-insulator-metal capacitor arrangement 失效
公开(公告)号：US20060087004A1
公开(公告)日：2006-04-27
申请号：US11247296
申请日：2005-10-12
申请人： Masayuki Furumiya , Kuniko Kikuta , Ryota Yamamoto , Makoto Nakayama
发明人： Masayuki Furumiya , Kuniko Kikuta , Ryota Yamamoto , Makoto Nakayama
IPC分类号： H01L29/00
CPC分类号： H01L23/5223 , H01L27/0805 , H01L28/87 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device has a semiconductor substrate, a multi-layered wiring construction formed over the semiconductor device, and a metal-insulator-metal (MIM) capacitor arrangement established in the multi-layered wiring construction. The MIM capacitor arrangement includes first, second, third, fourth, fifth, and sixth electrode structures, which are arranged in order in parallel with each other at regular intervals. The first, second, fifth and sixth electrode structures are electrically connected to each other so as to define a first capacitor, and the third and fourth electrode structures are electrically connected to each other so as to define a second capacitor.

6. 发明授权

US08378454B2 Semiconductor device including metal-insulator-metal capacitor arrangement 失效
标题翻译：半导体器件包括金属 - 绝缘体 - 金属电容器布置
公开(公告)号：US08378454B2
公开(公告)日：2013-02-19
申请号：US13173709
申请日：2011-06-30
申请人： Masayuki Furumiya , Kuniko Kikuta , Ryota Yamamoto , Makoto Nakayama
发明人： Masayuki Furumiya , Kuniko Kikuta , Ryota Yamamoto , Makoto Nakayama
IPC分类号： H01L21/02
CPC分类号： H01L23/5223 , H01L27/0805 , H01L28/87 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device has a semiconductor substrate, a multi-layered wiring construction formed over the semiconductor device, and a metal-insulator-metal (MIM) capacitor arrangement established in the multi-layered wiring construction. The MIM capacitor arrangement includes first, second, third, fourth, fifth, and sixth electrode structures, which are arranged in order in parallel with each other at regular intervals. The first, second, fifth and sixth electrode structures are electrically connected to each other so as to define a first capacitor, and the third and fourth electrode structures are electrically connected to each other so as to define a second capacitor.
摘要翻译：半导体器件具有形成在半导体器件上的半导体衬底，多层布线结构以及在多层布线结构中建立的金属 - 绝缘体 - 金属（MIM）电容器布置。 MIM电容器装置包括以规则的间隔彼此平行地排列的第一，第二，第三，第四，第五和第六电极结构。第一，第二，第五和第六电极结构彼此电连接以限定第一电容器，并且第三和第四电极结构彼此电连接以限定第二电容器。

7. 发明授权

US07705422B2 Semiconductor device including metal-insulator-metal capacitor arrangement 失效
标题翻译：半导体器件包括金属 - 绝缘体 - 金属电容器布置
公开(公告)号：US07705422B2
公开(公告)日：2010-04-27
申请号：US11247296
申请日：2005-10-12
申请人： Masayuki Furumiya , Kuniko Kikuta , Ryota Yamamoto , Makoto Nakayama
发明人： Masayuki Furumiya , Kuniko Kikuta , Ryota Yamamoto , Makoto Nakayama
IPC分类号： H01L29/00
CPC分类号： H01L23/5223 , H01L27/0805 , H01L28/87 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device has a semiconductor substrate, a multi-layered wiring construction formed over the semiconductor device, and a metal-insulator-metal (MIM) capacitor arrangement established in the multi-layered wiring construction. The MIM capacitor arrangement includes first, second, third, fourth, fifth, and sixth electrode structures, which are arranged in order in parallel with each other at regular intervals. The first, second, fifth and sixth electrode structures are electrically connected to each other so as to define a first capacitor, and the third and fourth electrode structures are electrically connected to each other so as to define a second capacitor.
摘要翻译：半导体器件具有形成在半导体器件上的半导体衬底，多层布线结构以及在多层布线结构中建立的金属 - 绝缘体 - 金属（MIM）电容器布置。 MIM电容器装置包括以规则的间隔彼此平行地排列的第一，第二，第三，第四，第五和第六电极结构。第一，第二，第五和第六电极结构彼此电连接以限定第一电容器，并且第三和第四电极结构彼此电连接以限定第二电容器。

8. 发明申请

US20060237819A1 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US20060237819A1
公开(公告)日：2006-10-26
申请号：US11407323
申请日：2006-04-20
申请人： Kuniko Kikuta , Masayuki Furumiya , Ryota Yamamoto , Makoto Nakayama
发明人： Kuniko Kikuta , Masayuki Furumiya , Ryota Yamamoto , Makoto Nakayama
IPC分类号： H01L29/00
CPC分类号： H01L23/5223 , H01L28/60 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes a capacitor with an MIM structure, by which the dimensional accuracy of the device is improved, and a stable capacitance value is given. The semiconductor device 100 includes: a semiconductor substrate 102; a capacitor forming region 130 in which an MIM capacitor is formed, which has an insulating interlayer 104 formed on the semiconductor substrate 102, a first electrode 110, and a second electrode 112, and the first electrode 110 and the second electrode 112 are arranged facing each other through the insulating interlayer 104; and a shielding region 132 which includes a plurality of shielding electrodes 114 formed in the outer edge of the capacitor forming region 130 and, at the same time, set at a predetermined potential in the same layer as that of the MIM capacitor on the semiconductor substrate 102, and shields the capacitor forming region 130 from other regions.
摘要翻译：半导体器件包括具有MIM结构的电容器，通过该电容器提高器件的尺寸精度，并给出稳定的电容值。半导体器件100包括：半导体衬底102; 形成有MIM电容器的电容器形成区域130，其具有形成在半导体衬底102上的绝缘中间层104，第一电极110和第二电极112，并且第一电极110和第二电极112面向彼此通过绝缘夹层104; 以及屏蔽区域132，其包括形成在电容器形成区域130的外边缘中的多个屏蔽电极114，并且同时在与半导体衬底上的MIM电容器相同的层中设定预定电位 102，并且将电容器形成区域130与其他区域屏蔽。

9. 发明授权

US07777288B2 Integrated circuit device and fabrication method therefor 有权
标题翻译：集成电路器件及其制造方法
公开(公告)号：US07777288B2
公开(公告)日：2010-08-17
申请号：US11052215
申请日：2005-02-08
申请人： Naoyoshi Kawahara , Hiroshi Murase , Hiroaki Ohkubo , Kuniko Kikuta , Yasutaka Nakashiba , Naoki Oda , Tokuhito Sasaki , Nobukazu Ito
发明人： Naoyoshi Kawahara , Hiroshi Murase , Hiroaki Ohkubo , Kuniko Kikuta , Yasutaka Nakashiba , Naoki Oda , Tokuhito Sasaki , Nobukazu Ito
IPC分类号： H01L31/058
CPC分类号： H01C7/1013 , H01L27/16 , H01L2924/0002 , H01L2924/00
摘要： In a temperature sensor section of a semiconductor integrated circuit device, wires of the topmost wiring layer of a multi-layer wiring structure are formed. A sheet-like temperature monitor element of vanadium oxide is provided between two of the wires in such a way as to cover the two wires. Accordingly, the temperature monitor element is connected between the two wires of an underlying wiring layer of the multi-layer wiring structure through two vias and the two wires of the topmost wiring layer.
摘要翻译：在半导体集成电路器件的温度传感器部分中，形成多层布线结构的最上层布线层的布线。在两条电线之间设置氧化钒的片状温度监视元件，以覆盖两条电线。因此，温度监视元件通过两个通孔和最上面布线层的两条导线连接在多层布线结构的底层布线层的两条导线之间。

10. 发明申请

US20050161822A1 Integrated circuit device 有权
标题翻译：集成电路器件
公开(公告)号：US20050161822A1
公开(公告)日：2005-07-28
申请号：US11038094
申请日：2005-01-21
申请人： Hiroaki Ohkubo , Kuniko Kikuta , Yasutaka Nakashiba , Naoyoshi Kawahara , Hiroshi Murase , Naoki Oda , Tokuhito Sasaki , Nobukazu Ito
发明人： Hiroaki Ohkubo , Kuniko Kikuta , Yasutaka Nakashiba , Naoyoshi Kawahara , Hiroshi Murase , Naoki Oda , Tokuhito Sasaki , Nobukazu Ito
IPC分类号： G01K1/14 , G01K7/00 , G01K7/01 , H01L21/4763 , H01L21/822 , H01L23/00 , H01L23/34 , H01L23/48 , H01L23/522 , H01L27/02 , H01L27/04 , H01L27/06 , H01L37/00
CPC分类号： H01L23/34 , G01K7/015 , H01L23/522 , H01L27/0248 , H01L2924/0002 , H01L2924/00
摘要： In a temperature sensor section of a semiconductor integrated circuit device, first vias of tungsten are formed at the topmost layer of a multi-layer wiring layer and pads of titanium are provided on regions of the multi-layer wiring layer which covers the vias. An insulating layer is provided in such a way as to cover the multi-layer wiring layer and the pads, second vias are so formed as to reach the pads. Vanadium oxide is buried in the second vias by reactive sputtering, and a temperature monitor part of vanadium oxide is provided in such a way as to connect the second vias each other. Accordingly, the temperature monitor part is connected between the two wires.
摘要翻译：在半导体集成电路器件的温度传感器部分中，在多层布线层的最上层形成钨的第一通孔，并且在覆盖通孔的多层布线层的区域上设置钛焊盘。以覆盖多层布线层和焊盘的方式设置绝缘层，第二通孔形成为到达焊盘。通过反应性溅射将氧化钒埋在第二通孔中，并且以使得第二通孔彼此连接的方式提供氧化钒的温度监视部分。因此，温度监视器部分连接在两条线之间。

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