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1. 发明授权

US06647539B1 Method of designing semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件设计方法
公开(公告)号：US06647539B1
公开(公告)日：2003-11-11
申请号：US09710910
申请日：2000-11-14
申请人： Masayoshi Tojima , Masahiro Ohashi , Mana Hamada , Miki Arita , Yuji Sugisawa
发明人： Masayoshi Tojima , Masahiro Ohashi , Mana Hamada , Miki Arita , Yuji Sugisawa
IPC分类号： G06F1750
CPC分类号： G06F17/5045
摘要： A system which allows signal transmission between circuit locks is constructed promptly by automatically generating an I/F circuit in response to the adjustment of a timing relationship and to a modification in a waveform on a GUI and automatically inserting the I/F circuit between the circuit blocks or adding the I/F circuit to any of the circuit block. A circuit for outputting an operation enable for a receiving side is generated automatically between a plurality of blocks operating with different frequencies, whereby the use of the circuit blocks is expanded in spite of the different frequencies. Further, the design of a large-scale system is performed efficiently by automatically generating a desired waveform by a simple editing operation, generating a desired signal waveform by forming a combinational circuit of signals in the circuit block, and automatically generating a logic synthesis script.
摘要翻译：通过自动产生I / F电路来响应于时序关系的调整和GUI上的波形的修改，迅速地构成允许电路锁之间的信号传输的系统，并且自动地将I / F电路插入电路块或将I / F电路添加到任何电路块。用于输出用于接收侧的操作使能的电路在以不同频率操作的多个块之间自动生成，由此尽管频率不同，电路块的使用也被扩展。此外，通过简单的编辑操作自动生成期望的波形，通过形成电路块中的信号的组合电路，生成期望的信号波形，自动生成逻辑综合脚本，有效地执行大规模系统的设计。

2. 发明授权

US06898771B2 Method of designing semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件设计方法
公开(公告)号：US06898771B2
公开(公告)日：2005-05-24
申请号：US10330097
申请日：2002-12-30
申请人： Masayoshi Tojima , Masahiro Ohashi , Mana Hamada , Miki Arita , Yuji Sugisawa
发明人： Masayoshi Tojima , Masahiro Ohashi , Mana Hamada , Miki Arita , Yuji Sugisawa
IPC分类号： H01L21/82 , G06F17/50
CPC分类号： G06F17/5045
摘要： A system which allows signal transmission between circuit blocks is constructed promptly by automatically generating an I/F circuit in response to the adjustment of a timing relationship and to a modification in a waveform on a GUI and automatically inserting the I/F circuit between the circuit blocks or adding the I/F circuit to any of the circuit block. A circuit for outputting an operation enable for a receiving side is generated automatically between a plurality of blocks operating with different frequencies, whereby the use of the circuit blocks is expanded in spite of the different frequencies. Further, the design of a large-scale system is performed efficiently by automatically generating a desired waveform by a simple editing operation, generating a desired signal waveform by forming a combinational circuit of signals in the circuit block, and automatically generating a logic synthesis script.
摘要翻译：通过自动生成I / F电路，可以快速构建允许电路块之间进行信号传输的系统，以响应于定时关系的调整和GUI上的波形的修改，并自动将I / F电路插入电路块或将I / F电路添加到任何电路块。用于输出用于接收侧的操作使能的电路在以不同频率操作的多个块之间自动生成，由此尽管频率不同，电路块的使用也被扩展。此外，通过简单的编辑操作自动生成期望的波形，通过形成电路块中的信号的组合电路，生成期望的信号波形，自动生成逻辑综合脚本，有效地执行大规模系统的设计。

3. 发明授权

US06826731B2 Method of designing semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件设计方法
公开(公告)号：US06826731B2
公开(公告)日：2004-11-30
申请号：US10330083
申请日：2002-12-30
申请人： Masayoshi Tojima , Masahiro Ohashi , Mana Hamada , Miki Arita , Yuji Sugisawa
发明人： Masayoshi Tojima , Masahiro Ohashi , Mana Hamada , Miki Arita , Yuji Sugisawa
IPC分类号： G06F1750
CPC分类号： G06F17/5045
摘要： A system which allows signal transmission between circuit blocks is constructed promptly by automatically generating an I/F circuit in response to the adjustment of a timing relationship and to a modification in a waveform on a GUI and automatically inserting the I/F circuit between the circuit blocks or adding the I/F circuit to any of the circuit block. A circuit for outputting an operation enable for a receiving side is generated automatically between a plurality of blocks operating with different frequencies, whereby the use of the circuit blocks is expanded in spite of the different frequencies. Further, the design of a large-scale system is performed efficiently by automatically generating a desired waveform by a simple editing operation, generating a desired signal waveform by forming a combinational circuit of signals in the circuit block, and automatically generating a logic synthesis script.
摘要翻译：通过自动生成I / F电路，可以快速构建允许电路块之间进行信号传输的系统，以响应于定时关系的调整和GUI上的波形的修改，并自动将I / F电路插入电路块或将I / F电路添加到任何电路块。用于输出用于接收侧的操作使能的电路在以不同频率操作的多个块之间自动生成，由此尽管频率不同，电路块的使用也被扩展。此外，通过简单的编辑操作自动生成期望的波形，通过形成电路块中的信号的组合电路，生成期望的信号波形，自动生成逻辑综合脚本，有效地执行大规模系统的设计。

4. 发明授权

US06332152B1 Arithmetic unit and data processing unit 失效
标题翻译：算术单元和数据处理单元
公开(公告)号：US06332152B1
公开(公告)日：2001-12-18
申请号：US09201720
申请日：1998-11-30
申请人： Masahiro Ohashi , Mana Hamada , Tomonori Yonezawa , Shunichi Kurohmaru , Yasuo Kouhashi , Masatoshi Matsuo , Masayoshi Toujima
发明人： Masahiro Ohashi , Mana Hamada , Tomonori Yonezawa , Shunichi Kurohmaru , Yasuo Kouhashi , Masatoshi Matsuo , Masayoshi Toujima
IPC分类号： G06F738
CPC分类号： H03M7/4006 , G06F7/02 , G06F2207/025 , H03M7/46
摘要： For every data, the number of data matches that occurred consecutively is written to a memory together with nonmatching data, and data from the memory is read out to continuously perform subsequent data processing and detect, at the same time, the last data written to the memory. To achieve this, a desired value is set in a data register, and a comparison instruction is issued by which the value set in the register is compared with a value set in a second register, and the number of matches that occurred consecutively is output together with nonmatching data; upon the output of a retrieval counter reaching a predetermined value, the comparison instruction is terminated, whereupon the number of consecutive matches, the nonmatching data, and an end flag signal are written to the memory at the same address.
摘要翻译：对于每个数据，连续发生的数据匹配数量与非匹配数据一起写入存储器，并且读出来自存储器的数据以连续执行后续数据处理，同时检测写入到记忆。为了实现这一点，在数据寄存器中设置期望值，并且发出比较指令，通过该比较指令将寄存器中设置的值与在第二寄存器中设置的值进行比较，并且连续发生的匹配次数一起输出具有不匹配的数据; 在检索计数器的输出达到预定值的情况下，比较指令被终止，因此连续匹配的数量，非匹配数据和结束标志信号被写入同一地址的存储器。

5. 发明授权

US06564237B2 Arithmetic unit and data processing unit 失效
公开(公告)号：US06564237B2
公开(公告)日：2003-05-13
申请号：US09978204
申请日：2001-10-17
申请人： Masahiro Ohashi , Mana Hamada , Tomonori Yonezawa , Shunichi Kurohmaru , Yasuo Kouhashi , Masatoshi Matsuo , Masayoshi Toujima
发明人： Masahiro Ohashi , Mana Hamada , Tomonori Yonezawa , Shunichi Kurohmaru , Yasuo Kouhashi , Masatoshi Matsuo , Masayoshi Toujima
IPC分类号： G06F738
CPC分类号： H03M7/4006 , G06F7/02 , G06F2207/025 , H03M7/46
摘要： For every data, the number of data matches that occurred consecutively is written to a memory together with nonmatching data, and data from the memory is read out to continuously perform subsequent data processing and detect, at the same time, the last data written to the memory. To achieve this, a desired value is set in a data register, and a comparison instruction is issued by which the value set in the register is compared with a value set in a second register, and the number of matches that occurred consecutively is output together with nonmatching data; upon the output of a retrieval counter reaching a predetermined value, the comparison instruction is terminated, whereupon the number of consecutive matches, the nonmatching data, and an end flag signal are written to the memory at the same address.

6. 发明授权

US08324083B2 Method for producing group III nitride compound semiconductor element 有权
标题翻译：制备III族氮化物半导体元件的方法
公开(公告)号：US08324083B2
公开(公告)日：2012-12-04
申请号：US12585969
申请日：2009-09-29
申请人： Toshiya Uemura , Masanobu Ando , Tomoharu Shiraki , Masahiro Ohashi , Naoki Arazoe , Ryohei Inazawa
发明人： Toshiya Uemura , Masanobu Ando , Tomoharu Shiraki , Masahiro Ohashi , Naoki Arazoe , Ryohei Inazawa
IPC分类号： H01L21/00 , H01L21/30 , H01L21/46
CPC分类号： H01L33/0079 , H01L33/0095 , H01L33/44 , H01L33/46
摘要： A method for producing a Group III nitride compound semiconductor element includes growing an epitaxial layer containing a Group III nitride compound semiconductor using a different kind of substrate as an epitaxial growth substrate, adhering a supporting substrate to the top surface of the epitaxial growth layer through a conductive layer, and then removing the epitaxial growth substrate by laser lift-off. Before adhesion of the epitaxial layer and the supporting substrate, a first groove that at least reaches an interface between the bottom surface of the epitaxial layer and the epitaxial growth substrate from the top surface of the epitaxial layer formed on the epitaxial growth substrate and acts as an air vent communicating with the outside of a wafer when the epitaxial layer and the supporting substrate are joined to each other. Next, the epitaxial layer is divided into each chip by separating the epitaxial growth substrate by laser lift-off, and then removing the epitaxial layer serving as the outer periphery of each chip. Next, the outer peripheral side surface of the epitaxial layer of each chip is at least completely covered with an insulating protective film. Next, the supporting substrate is separated into each chip.
摘要翻译：制造III族氮化物化合物半导体元件的方法包括：使用不同种类的基板作为外延生长基板，生长含有III族氮化物化合物半导体的外延层，将支撑基板通过外延生长层的上表面附着在外延生长层的顶面导电层，然后通过激光剥离去除外延生长衬底。在外延层和支撑基板的粘合之前，形成至少到达外延层的底表面与外延生长衬底之间的界面的第一沟槽，该外延生长衬底从形成在外延生长衬底上的外延层的顶表面起作用当所述外延层和所述支撑基板彼此接合时与所述晶片的外部连通的通风口。接下来，通过用激光剥离分离外延生长衬底，然后除去作为每个芯片的外周的外延层，将外延层分成每个芯片。接下来，每个芯片的外延层的外周侧表面至少完全被绝缘保护膜覆盖。接下来，将支撑基板分离成各个芯片。

7. 发明申请

US20120015229A1 LAMINATED SEPARATOR, POLYOLEFIN MICROPOROUS MEMBRANE, AND SEPARATOR FOR ELECTRICITY STORAGE DEVICE 有权
标题翻译：层压分离器，聚菲林薄膜和电力储存装置分离器
公开(公告)号：US20120015229A1
公开(公告)日：2012-01-19
申请号：US13255424
申请日：2010-03-09
申请人： Masahiro Ohashi , Keitaro Ameyama , Yuzuru Sakakibara
发明人： Masahiro Ohashi , Keitaro Ameyama , Yuzuru Sakakibara
IPC分类号： H01M2/16 , B29C67/20 , B32B3/00
CPC分类号： H01M2/1686 , B29C47/0057 , B29C67/202 , B29K2023/12 , B29L2031/755 , B32B27/08 , B32B27/18 , B32B27/205 , B32B27/32 , B32B2250/03 , B32B2250/24 , B32B2250/242 , B32B2250/40 , B32B2264/102 , B32B2270/00 , B32B2305/026 , B32B2305/30 , B32B2307/306 , B32B2307/518 , B32B2307/724 , H01M2/145 , H01M2/1653 , H01M2/166 , H01M10/052 , H01M10/0525 , Y02T10/7011
摘要： Disclosed is a laminated separator including a first polyolefin microporous layer and a second polyolefin microporous layer which is laminated on the first polyolefin microporous layer and which is different from the first polyolefin microporous layer, wherein at least one of the first microporous layer and the second microporous layer includes an inorganic particle having a primary particle size of 1 nm or more and 80 nm or less.
摘要翻译：公开了一种层压隔板，其包括第一聚烯烃微孔层和第二聚烯烃微孔层，层压在第一聚烯烃微孔层上，并且与第一聚烯烃微孔层不同，其中第一微孔层和第二微孔层中的至少一个层包含一次粒径为1nm以上且80nm以下的无机粒子。

8. 发明授权

US07618743B2 Microporous polyolefin film 有权
标题翻译：微孔聚烯烃膜
公开(公告)号：US07618743B2
公开(公告)日：2009-11-17
申请号：US10551465
申请日：2004-04-02
申请人： Masahiro Ohashi , Takahiko Kondo
发明人： Masahiro Ohashi , Takahiko Kondo
IPC分类号： H01M2/16 , H01M4/58
CPC分类号： B32B27/32 , B32B5/145 , B32B2250/242 , B32B2270/00 , B32B2305/026 , B32B2307/718 , B32B2309/105 , B32B2457/10 , H01M2/1653 , H01M2/1686
摘要： A microporous polyolefin film that comprises polyethylene and polypropylene as essential components and is composed of a laminate film of two or more layers, wherein the percentage of polypropylene blended in at least one surface layer of the film is more than 50% by weight and 95% by weight or less and the content of polyethylene in the entire film is 50% or more and 95% or less.
摘要翻译：一种微孔聚烯烃膜，其包含聚乙烯和聚丙烯作为必要组分，并且由两层或多层的层压膜组成，其中在所述膜的至少一个表面层中共混的聚丙烯的百分比大于50重量％且95重量％以下，整个膜中的聚乙烯的含量为50％以上且95％以下。

9. 发明申请

US20090072138A1 Test Apparatus 有权
标题翻译：测试仪器
公开(公告)号：US20090072138A1
公开(公告)日：2009-03-19
申请号：US12173038
申请日：2008-07-15
申请人： Katsunori HIRANO , Tadanobu Toba , Masahiro Ohashi , Masashi Wada
发明人： Katsunori HIRANO , Tadanobu Toba , Masahiro Ohashi , Masashi Wada
IPC分类号： G01N23/00
CPC分类号： G01N23/2251 , H01J2237/221 , H01J2237/2817
摘要： A scan control unit for generating two-dimensional coordinates for performing a scan with an electron beam of an electron scanning microscope is provided with first and second transforming units for transforming coordinates in the horizontal (X) direction and the vertical (V) direction. An area to be tested in a sample is scanned with an electron beam in an arbitrary direction. As the first and second transforming units, small-capacity transformation tables (LUTs) capable of operating at high speed in each of the horizontal (X) direction and the vertical (Y) direction are used. By also using a large-capacity transformation table (LUT) that stores coordinate transformation data corresponding to plural scan types, a test apparatus compatible with the plural scan types, having multiple functions, and capable of performing high-speed scan control is realized.
摘要翻译：用于产生用电子扫描显微镜的电子束执行扫描的二维坐标的扫描控制单元设置有用于变换水平（X）方向和垂直（V）方向上的坐标的第一和第二变换单元。用任意方向的电子束扫描样品中要测试的区域。作为第一变换单元和第二变换单元，使用能够在水平（X）方向和垂直（Y）方向中的每一个中高速运转的小容量变换表（LUT）。通过使用存储与多种扫描类型相对应的坐标变换数据的大容量变换表（LUT），实现具有多种功能，能够执行高速扫描控制的具有多种扫描类型的测试装置。

10. 发明申请

US20060190890A1 Cell instance generating method 审中-公开
标题翻译：单元实例生成方法
公开(公告)号：US20060190890A1
公开(公告)日：2006-08-24
申请号：US11339736
申请日：2006-01-26
申请人： Masahiro Ohashi , Takahiro Kondo
发明人： Masahiro Ohashi , Takahiro Kondo
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： By a hierarchical structure developing process at Step S1, layout pattern data possessing hierarchical structure is developed to flat layout pattern data. An optimizing process at Step S2 generates optimized flat layout pattern data accompanying a new inserted cell. By a hierarchical structure cell instance allotting process at Step S3, optimized flat layout pattern data is generated, in which an instance possessing hierarchical structure is allotted to the new inserted cell.
摘要翻译：通过步骤S1的层次结构开发过程，开发具有层次结构的布局图案数据，以平坦布局图案数据。步骤S2中的优化处理产生伴随新插入单元格的优化平面布局图案数据。通过在步骤S 3的分层结构单元实例分配处理，生成优化的平面布局模式数据，其中具有层次结构的实例被分配给新插入的单元。

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