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1. 发明授权

US08825943B2 Semiconductor device and driving method the same 有权
标题翻译：半导体器件和驱动方法相同
公开(公告)号：US08825943B2
公开(公告)日：2014-09-02
申请号：US12872254
申请日：2010-08-31
申请人： Masato Ishii , Yasuyuki Takahashi , Takuro Ohmaru , Hidetomo Kobayashi , Yutaka Shionoiri
发明人： Masato Ishii , Yasuyuki Takahashi , Takuro Ohmaru , Hidetomo Kobayashi , Yutaka Shionoiri
IPC分类号： G06F12/02
CPC分类号： G06F12/1433 , G06F2212/178
摘要： In a semiconductor device including a control circuit and a memory, the memory includes at least a sector for preventing additional writing and an information sector. When data for preventing additional writing is written to the sector for preventing additional writing and information is written to the information sector which is electrically connected to the sector for preventing additional writing, additional writing to the information sector is impossible.
摘要翻译：在包括控制电路和存储器的半导体器件中，存储器至少包括用于防止额外写入的扇区和信息扇区。当防止额外写入的数据被写入扇区以防止额外写入时，信息被写入与扇区电连接以防止额外写入的信息扇区，对信息扇区的额外写入是不可能的。

2. 发明申请

US20120287703A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20120287703A1
公开(公告)日：2012-11-15
申请号：US13467097
申请日：2012-05-09
申请人： Hidetomo Kobayashi , Masashi Fujita , Takuro Ohmaru
发明人： Hidetomo Kobayashi , Masashi Fujita , Takuro Ohmaru
IPC分类号： G11C11/24
CPC分类号： G06F12/08 , G06F1/3275 , G11C11/005 , G11C11/404 , H01L27/10873 , H01L27/115 , H01L27/11517 , H01L27/1203 , H01L27/1225 , Y02D10/14
摘要： When a CPU provided with a latch memory is operated, a constant storage method or an end storage method is selected depending on what is processed by the CPU; thus, the CPU provided with a latch memory has low power consumption. When the CPU provided with a latch memory is operated, in the case where the number of times of turning on and off the power source is high, a constant storage method is employed and in the case where the number of times of turning on and off the power source is low, an end storage method is employed. Whether a constant storage method or an end storage method is selected is determined based on the threshold value set depending on power consumption.
摘要翻译：当具有闩锁存储器的CPU被操作时，根据CPU处理的内容选择恒定存储方法或结束存储方法; 因此，具有闩锁存储器的CPU具有低功耗。当具有闩锁存储器的CPU被操作时，在电源打开和关闭的次数高的情况下，采用恒定的存储方法，并且在打开和关闭的次数的情况下电源低，采用端存储方式。基于根据功耗设定的阈值来确定是否选择恒定存储方法或结束存储方法。

3. 发明授权

US09559105B2 Signal processing circuit 有权
标题翻译：信号处理电路
公开(公告)号：US09559105B2
公开(公告)日：2017-01-31
申请号：US13473706
申请日：2012-05-17
申请人： Takuro Ohmaru , Hidetomo Kobayashi
发明人： Takuro Ohmaru , Hidetomo Kobayashi
IPC分类号： G11C11/24 , H01L27/115 , H01L27/105 , H01L27/108 , H01L27/12 , G11C11/413
CPC分类号： H01L27/115 , G11C11/413 , H01L27/1052 , H01L27/108 , H01L27/1203 , H01L27/1225
摘要： A signal processing circuit includes a memory and a control portion configured to control the memory. The control portion includes a volatile memory circuit including data latch terminals, a first non-volatile memory circuit electrically connected to one of the data latch terminals, a second non-volatile memory circuit electrically connected to the other of the data latch terminals, and a precharge circuit having a function of supplying a potential that is a half of a high power supply potential to the one and the other of the data latch terminals. Each of the first non-volatile memory circuit and the second non-volatile memory circuit includes a transistor having a channel formation region including an oxide semiconductor and a capacitor connected to a node that is brought into a floating state by turning off the transistor.
摘要翻译：信号处理电路包括存储器和被配置为控制存储器的控制部分。控制部分包括易失性存储器电路，其包括数据锁存端子，电连接到数据锁存端子之一的第一非易失性存储器电路，电连接到数据锁存端子中的另一个的第二非易失性存储器电路，以及预充电电路具有向数据锁存端子中的另一个提供高电源电位的一半的电位的功能。第一非易失性存储器电路和第二非易失性存储器电路中的每一个包括晶体管，其具有包括氧化物半导体的沟道形成区域和连接到通过截止晶体管而处于浮置状态的节点的电容器。

4. 发明授权

US08817527B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08817527B2
公开(公告)日：2014-08-26
申请号：US13467097
申请日：2012-05-09
申请人： Hidetomo Kobayashi , Masashi Fujita , Takuro Ohmaru
发明人： Hidetomo Kobayashi , Masashi Fujita , Takuro Ohmaru
IPC分类号： G11C11/00 , G06F12/08
CPC分类号： G06F12/08 , G06F1/3275 , G11C11/005 , G11C11/404 , H01L27/10873 , H01L27/115 , H01L27/11517 , H01L27/1203 , H01L27/1225 , Y02D10/14
摘要： When a CPU provided with a latch memory is operated, a constant storage method or an end storage method is selected depending on what is processed by the CPU; thus, the CPU provided with a latch memory has low power consumption. When the CPU provided with a latch memory is operated, in the case where the number of times of turning on and off the power source is high, a constant storage method is employed and in the case where the number of times of turning on and off the power source is low, an end storage method is employed. Whether a constant storage method or an end storage method is selected is determined based on the threshold value set depending on power consumption.
摘要翻译：当具有闩锁存储器的CPU被操作时，根据CPU处理的内容选择恒定存储方法或结束存储方法; 因此，具有闩锁存储器的CPU具有低功耗。当具有闩锁存储器的CPU被操作时，在电源打开和关闭的次数高的情况下，采用恒定的存储方法，并且在打开和关闭的次数的情况下电源低，采用端存储方式。基于根据功耗设定的阈值来确定是否选择恒定存储方法或结束存储方法。

5. 发明申请

US20120294069A1 SIGNAL PROCESSING CIRCUIT 有权
标题翻译：信号处理电路
公开(公告)号：US20120294069A1
公开(公告)日：2012-11-22
申请号：US13473706
申请日：2012-05-17
申请人： Takuro Ohmaru , Hidetomo Kobayashi
发明人： Takuro Ohmaru , Hidetomo Kobayashi
IPC分类号： G11C11/24 , G11C7/10
CPC分类号： H01L27/115 , G11C11/413 , H01L27/1052 , H01L27/108 , H01L27/1203 , H01L27/1225
摘要： A signal processing circuit includes a memory and a control portion configured to control the memory. The control portion includes a volatile memory circuit including data latch terminals, a first non-volatile memory circuit electrically connected to one of the data latch terminals, a second non-volatile memory circuit electrically connected to the other of the data latch terminals, and a precharge circuit having a function of supplying a potential that is a half of a high power supply potential to the one and the other of the data latch terminals. Each of the first non-volatile memory circuit and the second non-volatile memory circuit includes a transistor having a channel formation region including an oxide semiconductor and a capacitor connected to a node that is brought into a floating state by turning off the transistor.
摘要翻译：信号处理电路包括存储器和被配置为控制存储器的控制部分。控制部分包括易失性存储器电路，其包括数据锁存端子，电连接到数据锁存端子之一的第一非易失性存储器电路，电连接到数据锁存端子中的另一个的第二非易失性存储器电路，以及预充电电路具有向数据锁存端子中的另一个提供高电源电位的一半的电位的功能。第一非易失性存储器电路和第二非易失性存储器电路中的每一个包括晶体管，其具有包括氧化物半导体的沟道形成区域和连接到通过截止晶体管而处于浮置状态的节点的电容器。

6. 发明授权

US08570065B2 Programmable LSI 有权
标题翻译：可编程LSI
公开(公告)号：US08570065B2
公开(公告)日：2013-10-29
申请号：US13437961
申请日：2012-04-03
申请人： Hidetomo Kobayashi , Masami Endo , Yutaka Shionoiri , Hiroki Dembo , Tatsuji Nishijima , Kazuaki Ohshima , Seiichi Yoneda , Jun Koyama
发明人： Hidetomo Kobayashi , Masami Endo , Yutaka Shionoiri , Hiroki Dembo , Tatsuji Nishijima , Kazuaki Ohshima , Seiichi Yoneda , Jun Koyama
IPC分类号： H03K19/177 , G11C11/24
CPC分类号： H03K19/17796 , G11C16/0433 , H01L27/11803 , H01L27/1203
摘要： A low-power programmable LSI that can perform dynamic configuration is provided. The programmable LSI includes a plurality of logic elements. The plurality of logic elements each include a configuration memory. Each of the plurality of logic elements performs different arithmetic processing and changes an electrical connection between the logic elements, in accordance with the configuration data stored in the configuration memory. The configuration memory includes a set of a volatile storage circuit and a nonvolatile storage circuit. The nonvolatile storage circuit includes a transistor whose channel is formed in an oxide semiconductor layer and a capacitor whose one of a pair of electrodes is electrically connected to a node that is set in a floating state when the transistor is turned off.
摘要翻译：提供了可以执行动态配置的低功耗可编程LSI。可编程LSI包括多个逻辑元件。多个逻辑元件各自包括配置存储器。多个逻辑元件中的每一个执行不同的运算处理，并且根据存储在配置存储器中的配置数据改变逻辑元件之间的电连接。配置存储器包括一组易失性存储电路和非易失性存储电路。非易失性存储电路包括其沟道形成在氧化物半导体层中的晶体管和一对电极中的一个电极与晶体管截止时被设置为浮置状态的节点电连接的电容器。

7. 发明授权

US08207756B2 Logic circuit and semiconductor device 有权
标题翻译：逻辑电路和半导体器件
公开(公告)号：US08207756B2
公开(公告)日：2012-06-26
申请号：US12912397
申请日：2010-10-26
申请人： Yutaka Shionoiri , Hidetomo Kobayashi
发明人： Yutaka Shionoiri , Hidetomo Kobayashi
IPC分类号： H03K19/096
CPC分类号： H01L29/7869 , H01L27/088 , H01L27/1225 , H03K3/0375 , H03K19/0016 , H03K19/096
摘要： In a logic circuit where clock gating is performed, the standby power is reduced or malfunction is suppressed. The logic circuit includes a transistor which is in an off state where a potential difference exists between a source terminal and a drain terminal over a period during which a clock signal is not supplied. A channel formation region of the transistor is formed using an oxide semiconductor in which the hydrogen concentration is reduced. Specifically, the hydrogen concentration of the oxide semiconductor is 5×1019 (atoms/cm3) or lower. Thus, leakage current of the transistor can be reduced. As a result, in the logic circuit, reduction in standby power and suppression of malfunction can be achieved.
摘要翻译：在执行时钟门控的逻辑电路中，待机功率降低或故障被抑制。该逻辑电路包括在不提供时钟信号的时段内处于源极端子和漏极端子之间存在电位差的关断状态的晶体管。使用其中氢浓度降低的氧化物半导体形成晶体管的沟道形成区域。具体地说，氧化物半导体的氢浓度为5×1019（原子/ cm3）以下。因此，可以减小晶体管的漏电流。结果，在逻辑电路中，可以实现待机功率的降低和故障的抑制。

8. 发明授权

US09059704B2 Programmable logic device 有权
标题翻译：可编程逻辑器件
公开(公告)号：US09059704B2
公开(公告)日：2015-06-16
申请号：US13477192
申请日：2012-05-22
申请人： Seiichi Yoneda , Jun Koyama , Yutaka Shionoiri , Masami Endo , Hiroki Dembo , Tatsuji Nishijima , Hidetomo Kobayashi , Kazuaki Ohshima
发明人： Seiichi Yoneda , Jun Koyama , Yutaka Shionoiri , Masami Endo , Hiroki Dembo , Tatsuji Nishijima , Hidetomo Kobayashi , Kazuaki Ohshima
IPC分类号： G06F1/00 , H03K19/177 , H03K19/173 , G06F3/06
CPC分类号： H03K19/173 , G06F1/3243 , G06F3/0679 , H03K19/17772 , Y02D10/152
摘要： An object is to provide a programmable logic device configured to keep a connection state of logic circuits even while power supply voltage is stopped. The programmable logic device includes arithmetic circuits each of whose logic state can be changed; a configuration changing circuit changing the logic states of the arithmetic circuits; a power supply control circuit controlling supply of power supply voltage to the arithmetic circuits; a state memory circuit storing data on the logic states and data on states of the power supply voltage of the arithmetic circuits; and an arithmetic state control circuit controlling the configuration changing circuit and the power supply control circuit in accordance with the data stored in the state memory circuit. A transistor in which a channel formation region is formed in an oxide semiconductor layer is provided between the configuration changing circuit and each of the arithmetic circuits.
摘要翻译：目的是提供一种可编程逻辑器件，其被配置为即使在电源电压停止时仍保持逻辑电路的连接状态。可编程逻辑器件包括可以改变其逻辑状态的运算电路; 配置改变电路改变运算电路的逻辑状态; 电源控制电路，控制对所述运算电路的电源电压供给; 存储关于逻辑状态的数据的状态存储电路和关于运算电路的电源电压的状态的数据; 以及算术状态控制电路，根据存储在状态存储电路中的数据控制配置改变电路和电源控制电路。在配置改变电路和每个运算电路之间设置有在氧化物半导体层中形成沟道形成区的晶体管。

9. 发明申请

US20090079572A1 Semiconductor device and wireless communication system using the same 有权
标题翻译：半导体器件和使用其的无线通信系统
公开(公告)号：US20090079572A1
公开(公告)日：2009-03-26
申请号：US11919497
申请日：2006-05-17
申请人： Tomoaki Atsumi , Yutaka Shionoiri , Hidetomo Kobayashi
发明人： Tomoaki Atsumi , Yutaka Shionoiri , Hidetomo Kobayashi
IPC分类号： G08B13/22
CPC分类号： G06K19/07749 , G06K19/0708
摘要： Initialization of a semiconductor device can be efficiently performed, which transmits and receives data through wireless communication. The semiconductor device includes an antenna, a power source circuit, a circuit which uses a DC voltage generated by the power source circuit as a power source voltage, and a resistor. The antenna includes a pair of terminals and receives a wireless signal (a modulated carrier wave). The power source circuit includes a first terminal and a second terminal and generates a DC voltage between the first terminal and the second terminal by using a received wireless signal (the modulated carrier wave). The resistor is connected between the first terminal and the second terminal. In this manner, the semiconductor device and the wireless communication system can transmit and receive data accurately.
摘要翻译：可以有效地执行半导体器件的初始化，其通过无线通信发送和接收数据。半导体器件包括天线，电源电路，使用由电源电路产生的直流电压作为电源电压的电路和电阻器。天线包括一对终端，并接收无线信号（调制载波）。电源电路包括第一端子和第二端子，并且通过使用接收的无线信号（调制载波）在第一端子和第二端子之间产生直流电压。电阻器连接在第一端子和第二端子之间。以这种方式，半导体器件和无线通信系统可以准确地发送和接收数据。

10. 发明授权

US09117701B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US09117701B2
公开(公告)日：2015-08-25
申请号：US13459537
申请日：2012-04-30
申请人： Hiroyuki Tomatsu , Hidetomo Kobayashi , Yutaka Shionoiri
发明人： Hiroyuki Tomatsu , Hidetomo Kobayashi , Yutaka Shionoiri
IPC分类号： G11C11/00 , G11C7/00 , H01L27/115 , G11C7/02 , G11C11/408 , G11C11/4091 , G11C11/4094
CPC分类号： H01L27/1156 , G11C7/02 , G11C11/4085 , G11C11/4091 , G11C11/4094
摘要： Noise generated on a word line is reduced without increasing a load on the word line. A semiconductor device is provided in which a plurality of storage elements each including at least one switching element are provided in matrix; each of the plurality of storage elements is electrically connected to a word line and a bit line; the word line is connected to a gate (or a source and a drain) of a transistor in which minority carriers do not exist substantially; and capacitance of the transistor in which minority carriers do not exist substantially can be controlled by controlling a potential of a source and a drain (or a gate) the transistor in which minority carriers do not exist substantially. The transistor in which minority carriers do not exist substantially may include a wide band gap semiconductor.
摘要翻译：在字线上产生的噪声减小，而不增加字线上的负载。提供一种半导体器件，其中包括至少一个开关元件的多个存储元件设置为矩阵; 多个存储元件中的每一个电连接到字线和位线; 字线连接到其中少数载体基本不存在的晶体管的栅极（或源极和漏极）; 并且通过控制其中不存在少数载流子的晶体管的源极和漏极（或栅极）的电位，可以控制其中不存在少数载流子的晶体管的电容。少数载流子不存在的晶体管可以包括宽带隙半导体。

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