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1. 发明授权

US06677203B2 Method of manufacturing a semiconductor memory device which reduces the minimum area requirements of the device 失效
标题翻译：制造半导体存储器件的方法，其减小了器件的最小面积要求
公开(公告)号：US06677203B2
公开(公告)日：2004-01-13
申请号：US09964521
申请日：2001-09-28
申请人： Masataka Kusumi , Seiki Ogura
发明人： Masataka Kusumi , Seiki Ogura
IPC分类号： H01L21336
CPC分类号： H01L27/11521 , H01L27/115
摘要： A semiconductor memory device according to the present invention includes isolations, active regions, control gate electrodes and floating gate electrodes. The isolations are formed on a semiconductor substrate. The active regions are defined on the semiconductor substrate and isolated from each other by the isolations. The control gate electrodes are formed over the semiconductor substrate. Each of the control gate electrodes crosses all of the isolations and all of the active regions with a first insulating film interposed between the control gate electrode and the semiconductor substrate. Each of the floating gate electrodes is formed for associated one of the active regions so as to cover a side face of associated one of the control gate electrodes with a second insulating film interposed between the floating gate electrode and the control gate electrodes. In this device, the isolations are spaced apart from each other along the width of the control gate electrodes and each of the isolations crosses all of the control gate electrodes and extends continuously along the length of the control gate electrodes.
摘要翻译：根据本发明的半导体存储器件包括隔离，有源区，控制栅电极和浮栅电极。隔离物形成在半导体衬底上。有源区限定在半导体衬底上，并通过隔离彼此隔离。控制栅电极形成在半导体衬底上。每个控制栅极电极与介于控制栅极电极和半导体衬底之间的第一绝缘膜与所有的隔离层和所有有源区域交叉。每个浮栅电极被形成为用于相关联的一个有源区域，以便覆盖相关联的一个控制栅电极的侧面，其中第二绝缘膜置于浮置栅电极和控制栅电极之间。在该装置中，隔离件沿着控制栅电极的宽度彼此间隔开，并且每个隔离件跨越所有控制栅电极并沿着控制栅电极的长度连续地延伸。

2. 发明授权

US06828621B2 Nonvolatile semiconductor memory device and method for fabricating the same 失效
公开(公告)号：US06828621B2
公开(公告)日：2004-12-07
申请号：US10679431
申请日：2003-10-07
申请人： Masataka Kusumi , Fumihiko Noro , Hiromasa Fujimoto , Akihiro Kamada , Shinji Odanaka , Seiki Ogura
发明人： Masataka Kusumi , Fumihiko Noro , Hiromasa Fujimoto , Akihiro Kamada , Shinji Odanaka , Seiki Ogura
IPC分类号： H01L29788
CPC分类号： H01L29/66825 , H01L21/28273 , H01L29/42324 , H01L29/7885
摘要： A nonvolatile semiconductor memory device has a protective insulating film deposited on each of the side surfaces of a control gate electrode to protect the control gate electrode during the formation of a floating gate electrode, the floating gate electrode opposed to one of the side surfaces of the control gate electrode with the protective insulating film interposed therebetween so as to be capacitively coupled to the control gate electrode, a tunnel insulating film formed between the floating gate electrode and the semiconductor substrate, a drain region formed in a region of the semiconductor substrate containing a portion underlying the floating gate electrode, and a source region formed in a region of the semiconductor substrate opposite to the drain region relative to the control gate electrode.

3. 发明授权

US06642572B2 Nonvolatile semiconductor memory device and method for fabricating the same 失效
公开(公告)号：US06642572B2
公开(公告)日：2003-11-04
申请号：US10382520
申请日：2003-03-07
申请人： Masataka Kusumi , Fumihiko Noro , Hiromasa Fujimoto , Akihiro Kamada , Shinji Odanaka , Seiki Ogura
发明人： Masataka Kusumi , Fumihiko Noro , Hiromasa Fujimoto , Akihiro Kamada , Shinji Odanaka , Seiki Ogura
IPC分类号： H01L29788
CPC分类号： H01L29/66825 , H01L21/28273 , H01L29/42324 , H01L29/7885
摘要： A nonvolatile semiconductor memory device has a protective insulating film deposited on each of the side surfaces of a control gate electrode to protect the control gate electrode during the formation of a floating gate electrode, the floating gate electrode opposed to one of the side surfaces of the control gate electrode with the protective insulating film interposed therebetween so as to be capacitively coupled to the control gate electrode, a tunnel insulating film formed between the floating gate electrode and the semiconductor substrate, a drain region formed in a region of the semiconductor substrate containing a portion underlying the floating gate electrode, and a source region formed in a region of the semiconductor substrate opposite to the drain region relative to the control gate electrode.

4. 发明授权

US06784040B2 Nonvolatile semiconductor memory device and method for fabricating the same 失效
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US06784040B2
公开(公告)日：2004-08-31
申请号：US10382508
申请日：2003-03-07
申请人： Masataka Kusumi , Fumihiko Noro , Hiromasa Fujimoto , Akihiro Kamada , Shinji Odanaka , Seiki Ogura
发明人： Masataka Kusumi , Fumihiko Noro , Hiromasa Fujimoto , Akihiro Kamada , Shinji Odanaka , Seiki Ogura
IPC分类号： H01L29788
CPC分类号： H01L29/66825 , H01L21/28273 , H01L29/42324 , H01L29/7885
摘要： A nonvolatile semiconductor memory device has a protective insulating film deposited on each of the side surfaces of a control gate electrode to protect the control gate electrode during the formation of a floating gate electrode, the floating gate electrode opposed to one of the side surfaces of the control gate electrode with the protective insulating film interposed therebetween so as to be capacitively coupled to the control gate electrode, a tunnel insulating film formed between the floating gate electrode and the semiconductor substrate, a drain region formed in a region of the semiconductor substrate containing a portion underlying the floating gate electrode, and a source region formed in a region of the semiconductor substrate opposite to the drain region relative to the control gate electrode.
摘要翻译：非易失性半导体存储器件具有沉积在控制栅电极的每个侧表面上的保护绝缘膜，以在形成浮栅电极期间保护控制栅电极，浮置栅极与其中一个侧表面相对控制栅电极，其间插入有保护绝缘膜，以便电容耦合到控制栅电极，形成在浮置栅电极和半导体衬底之间的隧道绝缘膜，形成在半导体衬底的包含并且形成在半导体衬底的与漏极区相对的控制栅电极相对的区域中的源极区。

5. 发明授权

US06545312B2 Nonvolatile semiconductor memory device and method for fabricating the same 有权
公开(公告)号：US06545312B2
公开(公告)日：2003-04-08
申请号：US09897417
申请日：2001-07-03
申请人： Masataka Kusumi , Fumihiko Noro , Hiromasa Fujimoto , Akihiro Kamada , Shinji Odanaka , Seiki Ogura
发明人： Masataka Kusumi , Fumihiko Noro , Hiromasa Fujimoto , Akihiro Kamada , Shinji Odanaka , Seiki Ogura
IPC分类号： H01L29788
CPC分类号： H01L29/66825 , H01L21/28273 , H01L29/42324 , H01L29/7885
摘要： A nonvolatile semiconductor memory device has a protective insulating film deposited on each of the side surfaces of a control gate electrode to protect the control gate electrode during the formation of a floating gate electrode, the floating gate electrode opposed to one of the side surfaces of the control gate electrode with the protective insulating film interposed therebetween so as to be capacitively coupled to the control gate electrode, a tunnel insulating film formed between the floating gate electrode and the semiconductor substrate, a drain region formed in a region of the semiconductor substrate containing a portion underlying the floating gate electrode, and a source region formed in a region of the semiconductor substrate opposite to the drain region relative to the control gate electrode.

6. 发明申请

US20100261324A1 Trap-charge non-volatile switch connector for programmable logic 有权
标题翻译：用于可编程逻辑的陷阱充电非易失性开关连接器
公开(公告)号：US20100261324A1
公开(公告)日：2010-10-14
申请号：US12802894
申请日：2010-06-16
申请人： Tomoko Ogura , Seiki Ogura , Nori Ogura
发明人： Tomoko Ogura , Seiki Ogura , Nori Ogura
IPC分类号： H01L21/336
CPC分类号： G11C16/0466 , G11C16/0475 , H01L27/115
摘要： A nonvolatile trap charge storage cell selects a logic interconnect transistor uses in programmable logic applications, such as FPGA. The nonvolatile trap charge element is an insulator located under a control gate and above an oxide on the surface of a semiconductor substrate. The preferred embodiment is an integrated device comprising a word gate portion sandwiched between two nonvolatile trap charge storage portions, wherein the integrated device is connected between a high bias, a low bias and an output. The output is formed by a diffusion connecting to the channel directly under the word gate portion. The program state of the two storage portions determines whether the high bias or the low bias is coupled to a logic interconnect transistor connected to the output diffusion.
摘要翻译：非易失性陷阱电荷存储单元选择在可编程逻辑应用中使用的逻辑互连晶体管，例如FPGA。非挥发性捕获电荷元件是位于控制栅极下方并位于半导体衬底表面上的氧化物之上的绝缘体。优选实施例是集成器件，其包括夹在两个非易失性陷阱电荷存储部分之间的字门部分，其中该集成器件连接在高偏压，低偏压和输出之间。输出由连接到字栅极下方的通道的扩散形成。两个存储部分的编程状态确定高偏压或低偏压是否耦合到连接到输出扩散的逻辑互连晶体管。

7. 发明申请

US20100259985A1 Trap-charge non-volatile switch connector for programmable logic 有权
公开(公告)号：US20100259985A1
公开(公告)日：2010-10-14
申请号：US12802895
申请日：2010-06-16
申请人： Tomoko Ogura , Seiki Ogura , Nori Ogura
发明人： Tomoko Ogura , Seiki Ogura , Nori Ogura
IPC分类号： G11C16/04
CPC分类号： G11C16/0466 , G11C16/0475 , H01L27/115
摘要： A nonvolatile trap charge storage cell selects a logic interconnect transistor uses in programmable logic applications, such as FPGA. The nonvolatile trap charge element is an insulator located under a control gate and above an oxide on the surface of a semiconductor substrate. The preferred embodiment is an integrated device comprising a word gate portion sandwiched between two nonvolatile trap charge storage portions, wherein the integrated device is connected between a high bias, a low bias and an output. The output is formed by a diffusion connecting to the channel directly under the word gate portion. The program state of the two storage portions determines whether the high bias or the low bias is coupled to a logic interconnect transistor connected to the output diffusion.

8. 发明授权

US07382662B2 Twin insulator charge storage device operation and its fabrication method 有权
标题翻译：双绝缘子电荷存储装置的操作及其制作方法
公开(公告)号：US07382662B2
公开(公告)日：2008-06-03
申请号：US11409247
申请日：2006-04-21
申请人： Seiki Ogura , Kimihiro Satoh , Tomoya Saito
发明人： Seiki Ogura , Kimihiro Satoh , Tomoya Saito
IPC分类号： G11C11/34 , H01L23/58
CPC分类号： H01L21/28282 , G11C16/0466 , G11C16/0475 , G11C16/0483 , H01L27/105 , H01L27/115 , H01L27/11568 , H01L29/4234 , H01L29/42364 , H01L29/66833 , H01L29/792 , H01L29/7923 , H01L2924/0002 , H01L2924/00
摘要： The invention proposes am improved twin MONOS memory device and its fabrication. The ONO layer is self-aligned to the control gate horizontally. The vertical insulator between the control gate and the word gate does not include a nitride layer. This prevents the problem of electron trapping. The device can be fabricated to pull the electrons out through either the top or the bottom oxide layer of the ONO insulator. The device also incorporates a raised memory bit diffusion between the control gates to reduce bit resistance. The twin MONOS memory array can be embedded into a standard CMOS circuit by the process of the present invention.
摘要翻译：本发明提出了改进的双MONOS存储器件及其制造方法。 ONO层水平自对准控制门。控制栅极和字栅之间的垂直绝缘体不包括氮化物层。这样可以防止电子捕获的问题。可以制造器件以通过ONO绝缘体的顶部或底部氧化物层拉出电子。该器件还包括在控制栅极之间的升高的存储器位扩散以减小位阻。双MONOS存储器阵列可以通过本发明的方法嵌入到标准CMOS电路中。

9. 发明申请

US20080101117A1 Trap-charge non-volatile switch connector for programmable logic 有权
标题翻译：用于可编程逻辑的陷阱充电非易失性开关连接器
公开(公告)号：US20080101117A1
公开(公告)日：2008-05-01
申请号：US11982172
申请日：2007-11-01
申请人： Tomoko Ogura , Seiki Ogura , Nori Ogura
发明人： Tomoko Ogura , Seiki Ogura , Nori Ogura
IPC分类号： G11C16/04 , H01L21/336
CPC分类号： G11C16/0466 , G11C16/0475 , H01L27/115
摘要： A nonvolatile trap charge storage cell selects a logic interconnect transistor uses in programmable logic applications, such as FPGA. The nonvolatile trap charge element is an insulator located under a control gate and above an oxide on the surface of a semiconductor substrate. The preferred embodiment is an integrated device comprising a word gate portion sandwiched between two nonvolatile trap charge storage portions, wherein the integrated device is connected between a high bias, a low bias and an output. The output is formed by a diffusion connecting to the channel directly under the word gate portion. The program state of the two storage portions determines whether the high bias or the low bias is coupled to a logic interconnect transistor connected to the output diffusion.
摘要翻译：非易失性陷阱电荷存储单元选择在可编程逻辑应用中使用的逻辑互连晶体管，例如FPGA。非挥发性捕获电荷元件是位于控制栅极下方并位于半导体衬底表面上的氧化物之上的绝缘体。优选实施例是集成器件，其包括夹在两个非易失性陷阱电荷存储部分之间的字门部分，其中该集成器件连接在高偏压，低偏压和输出之间。输出由连接到字栅极下方的通道的扩散形成。两个存储部分的编程状态确定高偏压或低偏压是否耦合到连接到输出扩散的逻辑互连晶体管。

10. 发明授权

US07359250B2 Twin insulator charge storage device operation and its fabrication method 有权
公开(公告)号：US07359250B2
公开(公告)日：2008-04-15
申请号：US11409333
申请日：2006-04-21
申请人： Seiki Ogura , Kimihiro Satoh , Tomoya Saito
发明人： Seiki Ogura , Kimihiro Satoh , Tomoya Saito
IPC分类号： G11C11/34
CPC分类号： H01L21/28282 , G11C16/0466 , G11C16/0475 , G11C16/0483 , H01L27/105 , H01L27/115 , H01L27/11568 , H01L29/4234 , H01L29/42364 , H01L29/66833 , H01L29/792 , H01L29/7923 , H01L2924/0002 , H01L2924/00
摘要： The invention proposes am improved twin MONOS memory device and its fabrication. The ONO layer is self-aligned to the control gate horizontally. The vertical insulator between the control gate and the word gate does not include a nitride layer. This prevents the problem of electron trapping. The device can be fabricated to pull the electrons out through either the top or the bottom oxide layer of the ONO insulator. The device also incorporates a raised memory bit diffusion between the control gates to reduce bit resistance. The twin MONOS memory array can be embedded into a standard CMOS circuit by the process of the present invention.

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